JPH03125525A - Multiplex signal identification system - Google Patents

Abstract

PURPOSE:To make the data transmission efficient by not using any special identification ID bit but using other bit in a frame for the ID bit in common. CONSTITUTION:An even number parity is used for one multiplexer 10A and an odd number parity is used for other multiplexer 10B. The parity bit is used for an identification ID bit and no special bit is used for the identification ID bit. Exclusive OR gates 13A, 13B implement the even parity and odd parity processing. That is, the Exclusive OR gate 13A receives '0' at one input terminal and passes the output of a parity calculation section 14A as it is, while the Exclusive OR gate 13B receives '1' at one input terminal and passes the output of a parity calculation section 14B after inversion. Thus, efficient data transmission is attained.

Description

[Detailed Description of the Invention] [Summary of the Invention] Serial signals composed of two or more frames are multiplexed by parallel/serial conversion without configuring an upper frame, and each channel is assigned an identification ID on the frame. Regarding a multiplexed signal identification method that distinguishes by bits, the purpose is to improve the efficiency of data transmission by not using a special ID bit for identification, but by having it be used for other bits in the frame, 2
In a multiplexed signal identification method, serial signals composed of frames of more than one system are multiplexed by parallel/serial conversion without forming upper frames, and each system is distinguished by an identification ID bit on the frame. The parities for transmission path error detection of the frame-structured serial signals are set to even parity on one side and odd parity on the other, and the parity bits added to the frame-structured serial signals of each system are set to the even parity on one side and the parity on the other to odd parity. Each odd parity bit is used as an ID bit for identification.

[Industrial application field]

The present invention provides multiplexed signal identification, in which serial signals composed of two or more systems of frames are multiplexed by parallel/serial conversion without forming upper frames, and each system is distinguished by identification ID bits on the frame. Regarding the method.

When multiplexing serial signals composed of multiple frames, it is common to assemble upper frames, but since it is not easy to implement a frame synchronization circuit for high-speed signals, multiplexing is performed using parallel/serial conversion. is taken. Even after such multiplexing, it is of course necessary to distinguish the signals of each system.
The present invention relates to this identification method.

[Conventional technology]

FIG. 5 shows an outline of a multiplexing method using parallel/serial conversion.

This is a number 100 that is not easy to implement in a frame synchronization circuit.
It is used for multiplexing high-speed signals of Mb/s or higher, or as a simple multiplexing method.

In FIG. 5, numeral 10 (subscripts A and B are used to distinguish each system and will be omitted as appropriate) is a MUX board, which includes a multiplexing section 12, a parity calculation section 14, and the like. Di
l+I)iz is the input data of each system, and M
The frame pattern F, frame identification ID signals IDO and IDI, and parity calculation results are added on the UX board.

FIG. 3 shows this added state, that is, the signal format of each system. Parity bit P I+ as shown
Pz, . . . are calculated from the data of the previous frame. The bit rate of the MUX Iwata signal is 400 Mb/s in this example. These are parallel/
Parallel/serial converted in serial converter 16, thus 800 M
b/s and enters the optical transmission package one day, and is sent out to the optical transmission line 20 as an optical signal.

On the receiving side, the signal is received by an optical receiving package 22, serial/parallel converted by a serial/parallel converter 24, and sent to a demux (DMX; separation) board 30 of each system by a switch 26. D
The MX board has a frame synchronization detection section 32, a parity check section 34, an identification ID signal check section 36, and the like.

The detection section 32 detects the frame pattern 14 to know the classification of the frame, and then extracts the frame identification ID signal and checks whether it is the expected one. In this example, 1
If it is a system (Di+ system), if it is an IDO 12 system, it is D1, so the check sections 36A and 36B perform this check (take the EOR with the preset ID0ID1). If they are the same, no output is produced, but if they are different, an output is produced, which switches the switch 26 to switch the destination of the serial/parallel converted frame data. Now ID Chee'7 should be OK. Parity check section 3
In step 4, a parity check is performed on the received data (checking whether the parity found from the received data matches the sent parity), and if there is an error, an error signal ERR is output. ID check is OK, parity check is also OK.
received data D. l+ DoZ (This is transmission data D
(corresponding to l1 Dl) is received and used.

As is known, there are two types of parity: even parity and odd parity. Even parity is when ``1'' in a binary data block is added and the lowest 1 or 0 is used as a parity bit, and odd parity is when it is inverted and used as a parity bit. It is as shown in Figure 6. ■ Each bit of frame m-bit binary human input data D1... is an exclusive OR gate G.

Simple addition with flip-flops (addition without carry)
The result is exclusive or two (exclusive or two) G2, and if it is an even parity, it is left as is, and if it is an odd parity, it is inverted and becomes a parity bit Sp, which is added to the transmission data SDi and sent out. Note that CLK and fi are the speed clock of D in, C
LKo,, Hari. . speed clock.

On the receiving side, receive data RD8 is similarly simply added to obtain parity bit RP (exclusive OR gate G3 and flip-flop FF are circuits for this purpose), and exclusive OR gate G
If the parity is even, it is inverted (0 and 1 are for this purpose), and compared with the received transmitter parity bit 8P. If they match, the output of gate G4 is O, but if they do not match, it becomes L, which is the error signal E.
Become RR. R is a flip-flop FF for each frame
This is the signal to reset the . Expressed mathematically, even parity output P QVQll is odd parity Pond is SP Odd ”” sP QVQFI■1-Σ sD
Lxf is the number of bits in the parity calculation area of one frame. The receiving side also performs similar calculations on the received data RDi and calculates the sent parity bit PIII,l.
Also, if it is the same as 5Pod, it is normal, and if it is different, it is abnormal.

[Problem to be solved by the invention]

When ID bits for identification are inserted into each frame as shown in FIG. 3, the number of data bits that can be packed into each frame decreases accordingly, and the more this can be reduced, the more effectively data transmission can be performed.

The present invention focuses on this point, and aims to improve the efficiency of data transmission by not using a special ID bit for identification, but by having it be used for other bits in the frame. This is the purpose.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, one multiplexer 10A uses even parity, and the other multiplexer 10B uses odd parity. Of course, on the contrary, odd parity may be used in one multiplexer and even parity may be used in the other multiplexer. The parity bit also serves as an ID bit for identification, and no special ID bit is used as the ID bit for identification.

(exclusive or two) 13A and 13B perform this even parity conversion and odd parity conversion. That is, the exclusive OR gate 13A receives "0" at one input terminal and passes the output of the parity calculation section 14A as it is.The exclusive OR gate 13B receives "'1" at one input terminal and passes the output of the parity calculation section 14A as is. The output of is inverted and passed through.

[Effect]

If one of each frame of the signal multiplexed by parallel/serial conversion has even parity, and all the others have odd parity, or one has odd parity and all the others have even parity, then the receiving side determines the even parity and odd parity. If there is no abnormality after detection, then frame identification (1 system or 2 systems...
), and no special ID bits are used, which increases the number of data bits that can be packed into a frame, making efficient data transmission possible.

〔Example〕

An embodiment of the invention is shown in FIG. 1, in which the same parts as in FIG. 5 are given the same reference numerals. 1 frame f bit human power data D, □I+ Di, Z are MtJX board 1
Parity is calculated at 0A and IOB, even parity bits are determined at IOA, and odd parity bits are determined at IOB, and these are added to the manual data together with frame pattern F at multiplexing units 12A and 12B. FIG. 2 shows multiplexing sections 12A and 1.
2B shows the format of the output signal. This corresponds to FIG. 3, but the identification TD bits IDO, ID
There is no I, and instead, system 1 has even parity and system 2 has odd parity. In FIG. 3, both systems 1 and 2 are either even parity or odd parity.

The output signals of the multiplexing unit 10A and IOB are parallel/serial converted by a parallel/serial converter 16, and converted into electric/serial signals by an optical transmission package 18.
The light is converted into an optical signal and sent to the optical cable 20. If the bit rate of the output signals of the multiplexers 10A and 10B is 400 Mb/s, the bit rate of the output signal of the parallel/serial converter 16 is 800 Mb/s.

On the receiving side, optical/electrical conversion is performed by the optical receiving package 22, serial/parallel conversion is performed by the serial/parallel converter 24, and the 1st system is sent to the DMUX board 30A by the switch 26, and the 2nd system is sent to the DMIIX board 3.
Sent to 0B. This distribution is reversed, and the protection circuits 36A, 3
It is switched by the output of 6B and returned to the correct distribution state.

That is, the parity check section 34A performs an exclusive or game) 35
Compare the parity obtained from the received data that passed through A (non-inverted and unchanged\) and the parity P sent from the transmitting side and take an exclusive OR), and the results are “1” (abnormal) and “0”.
(normal) is output.

In other words, find even parity. In the protection circuit 36A, the output
[Notice that "0" appears consecutively (although not necessarily consecutively) a predetermined number n times, an output is generated and the switch 26 is switched. In the parity check section 34B, Inverted with exclusive OR gate 35B,
Exclusive OR is performed between the parity obtained from the received data and the parity P sent from the transmitting side, and the results "1" (abnormal) and 0 (normal) are output. That is, odd parity is obtained. In the protection circuit 36B. Paying attention to the output "1", if this continuously appears a predetermined number n times, the switch 26 is switched.

When the frame distribution is reversed, the protection circuit 36A
and protection circuit 36B should produce an output at the same time. Therefore, under the condition that the output is generated at the same time, the switch 26
It is also possible to switch between the two.

The parity check circuit 34 outputs an error detection signal ERR when a parity error is detected, for example, once every three times. The protection circuit 36 outputs a switching signal for the switch 26 when this signal is output, for example, five times (n=5). This is to distinguish between a regular parity error (unrelated to frame allocation) and a parity error due to frame allocation.If the latter is the case, it is expected that each frame will have an error, so even if n is large. It does not take much time, and by increasing n, it is possible to more reliably distinguish it from regular parity errors.

The appropriateness/inappropriateness of frame allocation is determined when the line is set up (when the power is turned on) and does not change during the process, so it is conceivable to lock the switch in that state after a predetermined period of time after the line is set up.

Multiplexing by parallel/serial conversion can be applied to three or more systems, and an embodiment in this case is shown in FIG.

There are three or more MUX boards and DMUX boards, and they can be used in parallel/
The serial converter 16 performs parallel/serial conversion by sequentially arranging three or more frames, and the serial/parallel converter 24 on the receiving side
performs serial/parallel conversion by sending each frame to three or more applicable paths.

For even/odd parity, only one system is different from the other systems. In this example, only MUX1 has even parity (the data added to the exclusive OR gate is 0), and the remaining MUX2 to MUχ! is odd parity (the data added to the exclusive OR gate is 1). On the receiving side, DMUX 1 has 1 2 even parity detection, and the remaining DMUX 2~! 2 performs odd parity detection and sends a control signal to the rotation control unit 38 to switch the switch 26 until no parity error is detected. Each system 11.12 on the inlet side of the switch 26.・・・
···bow! , each output system is 01 02,...
If ○l, the switching operation is as follows.

■,......

■ ■ ■ ■1→0111-0211→03 I2-02 ■2→03 I2→04 In this example, the even parity serves as a mark indicating the Baum position, and the order of each system is fixed, so All systems can be matched by matching the home position.

It is also possible to use multiple parity bits to distinguish between multiple systems. For example, 1 in units of 2 frames.
The systems are even and even, the 2 systems are even and odd, the 3 systems are odd and even, and the 4 system is odd and odd parity.

In this case, it is somewhat similar to ID bits for identification, and frame allocation can be corrected quickly, but of course, as the number of parity bits increases, the frame focus that can be used for data decreases.

Such multiple parity bits are sometimes used to determine parity depending on the transmission path layer classification. It is also possible to use one ID bit and one parity bit for identification.

In order to detect that n parity errors ERR have appeared consecutively in the protection circuit 36, for example, the clock generated in each frame is used as the shift clock of an n-bit shift register, and the output of the parity check circuit is input to the shift register. Then, each bit of the shift register may be ANDed, and the output of the AND gate may be used.

〔Effect of the invention〕

As explained above, according to the present invention, the parity bit is used instead of inserting the ID bit for identification, so other information can be allocated to the frame accordingly.

Since multiplexing using parallel/serial conversion is generally used for high-speed signals, the amount of information for ID bits is large.

For example, with a 400 Mb/s serial signal, 400 bits/
When a frame, the ID bit is IMb even if it is 1 bit.
/s becomes. The fact that so many bits are simply used for frame identification is a loss that cannot be overlooked. According to the present invention, this problem can be remedied. Further, parity detection is generally performed in units of one frame, and due to the limit of the error detection rate, the number of bits cannot be very large (one parity detection section minus the number of bits of one frame). Therefore, ID in one frame
The bit transmission rate is not small, and we don't want to waste it. It is significant to effectively utilize this parity pit as in the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the multiplexed signal identification method of the present invention, FIG. 2 is an explanatory diagram of the signal format of the present invention, FIG. 3 is an explanatory diagram of the conventional signal format, and FIG. 4 is an implementation of the present invention. FIG. 5 is a block diagram showing an example, FIG. 5 is a block diagram showing a conventional example, and FIG. 6 is an explanatory diagram of parity creation/detection. In Figure 1, IOA and IOB are one system, MUX board of other system,
13A and 14A are even parity, 13B. 14B is an odd parity generation circuit.

Claims (1)

[Claims] In a multiplexed signal identification method in which serial signals composed of one or more frames are multiplexed by parallel/serial conversion without forming upper frames, and each system is distinguished by an ID bit for identification on the frame. , the parity for transmission path error detection of the frame-structured serial signal of each system is set to even parity on one side and odd parity on the other, and the parity bit added to the frame-structured serial signal of each system is the even parity on one side. , and the other is a multiplexed signal identification method characterized in that each bit of the odd parity is used as an ID bit for identification.