JPH03123915A - High frequency power source controller - Google Patents

Abstract

PURPOSE:To attain stable feedback control in which a peak ripple is small in a normal state and which has high response by feeding back a high frequency output from a power detection circuit through the use of a sample-hole circuit. CONSTITUTION:The output of a clock signal generation circuit 14 is inputted to a switching circuit 2 through a synchronous circuit 16, synchronously charges the high frequency output and inputs it to a delay circuit 17. The output of the circuit 14 is inputted to the circuit 17 through a frequency-dividing circuit 16 and supplies a sampling pulse to the sample-hold circuit 30 through a synchronous circuit 21. The circuit 30 sample-holds the output of the power detection circuit 8 and outputs it to an error amplifier circuit 13. The circuit 13 compares the output of the circuit 30 with the output of a power setting circuit 12, amplifies it and controls feedback. Thus, stable feedback control whose peak ripple is small in the normal state and which has high response can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high frequency power supply control device, and particularly to peak value control of high frequency output in pulse mode and continuous mode.

Conventional technology Conventionally, to control the peak value of high-frequency output, the output of a power setting circuit that sets the magnitude of high-frequency output and the output of a power detection circuit that detects the magnitude of high-frequency output are input to an error amplifier circuit, and the error The output of the amplifier circuit was used as the input of the attenuator.

A control block diagram of a conventional high frequency power supply device will be explained below with reference to FIG. The output of the oscillation circuit 1 shown in FIG. 3 passes through a switch circuit 2 and then is input to an attenuation circuit 3 that controls the magnitude of the RF small output. The output of the attenuation circuit 3 is input to a preamplifier 4, and the output of the preamplifier 4 is input to a driver 6. The output of the driver 6 is an amplifier circuit 6 using a vacuum tube or the like.
The output of the amplifier circuit 6 is input to a tuning circuit (tank circuit) 7. The output of the tuning circuit 7 is the power detection circuit 8
After passing through, it is outputted to the outside from the coaxial cable connector 9.

Further, the output of the starting circuit 1Q is input to the pulse mode or continuous mode waveform setting circuit 11, and the waveform setting circuit 11
A signal is output from which the pulse frequency and pulse width in pulse mode are set, or the energization and output period in continuous mode are set. The switch circuit 2 opens and closes in conjunction with the output of the waveform setting circuit 11, and when the switch circuit 2 is open, the high RF output is instantaneously cut off.

The output of the power setting circuit 12 that sets the RF high output level is input to the non-inverting terminal of the error amplification circuit 13. On the other hand, the output of the power detection circuit 8 is input to the inverting terminal of the error amplifier 13, and the output of the error amplifier 13 is input to the attenuator 3. The input of the attenuator 3 changes from Q to 6v, etc., and the higher the input, the higher the RF output, controlling the RF high output.

Problems to be Solved by the Invention When the gain of the feedback system is increased in order to reduce the peak ripple value of the high-frequency output in a steady state with a rising pulse mode or CW mode waveform, disturbances such as environmental fluctuations such as voltage fluctuations When the peak output is triggered, damping occurs.

In addition, if the feedback system is made highly responsive, phase compensation,
In other words, a phase shift occurs between the phase of the high-frequency output or the output of the detector that detects the high-frequency output and the output of the error amplifier circuit that performs feedback control, and in some cases, positive feedback is applied, resulting in damping and oscillation. occurs.

Also, if the gain of the feedback system is set high and the feedback system is made high response, if several products are produced,
Since the gain is high and the response is high, some parts may cause damping or oscillation due to component variations.

The present invention eliminates the conventional drawbacks and provides stable feedback control with a small peak ripple value and high response in a steady state.

Means for Solving the Problems In order to solve the above problems, the high frequency power supply control device of the present invention includes a power detection circuit that detects high frequency output, and a sample hold circuit that samples and holds the output of the power detection circuit. , a power setting circuit that sets the magnitude of the high frequency output, an error amplifier circuit that feedback controls the high frequency output so that the magnitude is set by the power setting circuit, and a clock signal that sets the sampling frequency of the sample and hold circuit. a generation circuit, the output of the power detection circuit is input to a sample hold circuit, the output of the sample hold circuit and the output of the power setting circuit are input to the error amplification circuit, and the output of the power detection circuit is input to the error amplifier circuit; The output of the sample and hold circuit is input to the sample and hold circuit.

Further, the waveform setting circuit for setting the pulse mode or CW mode waveform is provided with a delay circuit, and the output of the nTJ waveform setting circuit and the output of the clock signal generation circuit are input to the delay circuit, The output is input to the sample and hold circuit.

Further, the output of the clock signal generation circuit is input to a frequency dividing circuit, and the output of the frequency dividing circuit is input to the sample hold circuit or the delay circuit.

Further, the output of the clock signal generation circuit and the output of the waveform setting circuit are input to a synchronous circuit, and the output of the synchronous circuit is input to a switch circuit that turns on/off high frequency output.

Further, a second synchronization circuit is provided in the delay circuit, and the second synchronization circuit is provided in the delay circuit.
an output of a delay timer circuit in the delay circuit to a synchronous circuit of the synchronous circuit;
The output of the clock signal generation circuit or the output of the frequency dividing circuit is input.

Effect In the above means, an appropriate sample time and hold time are set in consideration of the signal transmission delay time of the power start-up system including the power detection circuit, and the appropriate sample time and hold time are set.
By using a sample-and-hold circuit with a set hold time, the input to the error amplifier will not fluctuate during the hold period.
Since it is constant, stable X feedback control is possible.

Appropriate sample time and hold time can be set using the clock signal generation circuit and frequency divider circuit.

Also, a delay circuit is used to start feedback control using a sample hold circuit after a delay, and a synchronization circuit is used to synchronize the high frequency output and start sample hold at the same time. In addition, a second synchronization circuit is provided within the delay circuit so that the output of the delay circuit is started up in synchronization.From the above, it is possible to synchronize the power start-up system and the sample and hold circuit. Therefore, the feedback system becomes stable even when the high frequency output waveform rises or falls in a state other than the steady state, and the drawbacks of using a sample and hold circuit can be eliminated without any problems.

Embodiment FIG. 1 shows a control block diagram of the high frequency power supply of the present invention,
FIG. 2 is a waveform diagram of the main part of FIG. 2 of the present invention. Components that are the same as those in FIG. 3 of the prior art and FIG. 1 of the present invention are given the same numbers.

Comparing and explaining the main part waveform diagrams of FIG. 1 and FIG. 2, first, the output of the waveform setting circuit 11 as shown in FIG. As shown in Figure 2 (B), the output from the lock signal generation circuit 14 is also synchronously input to the circuit 15, and the output is synchronized with the clock signal 24 in Figure 2 (C) as shown in Figure 2 (C). The output of the synchronization circuit 16 rises.The output of the synchronization circuit 16 is input to the switch circuit 2, and the high frequency output is input in synchronization.The output of the synchronization circuit 15 is also input to the delay circuit 17.

On the other hand, the output of the clock signal generation circuit 14 is also input to the frequency dividing circuit 16, and the frequency dividing flip-flop 18 and AND element 19 in that circuit are used to input the output of the clock signal generating circuit 14 to the frequency dividing circuit 16 (see FIG. 2). You will get the output shown.

The output of the frequency divider circuit 16 is input to the delay circuit 17, and when the output of the synchronization circuit 15 mentioned above is input to the delay circuit 17, the delay time circuit 20 counts the delay time, and the output of the delay time circuit 20 is input to the delay circuit 17. The signal is input to the synchronous circuit 21, and the output of the second synchronous circuit rises in synchronization with the output of the frequency dividing circuit 16. The output of the second synchronous circuit 21 is inputted to the NOR element 23 after passing through the inverter element 22, and the output of the frequency dividing circuit 16 is also inputted to the NOR element 23, and the delay time TSD
After 31 lapses, the delay circuit 17 obtains an output as shown in FIG. 2 (e). In the case of this sample hold circuit 3o, as shown in FIG. 2 (e), the sample 26.3
2. Like the hold 27, the sample hold circuit 30
performs sampling. When the delay time count starts,
The control signal of the sample hold circuit 3° is the sample state. Here, the frequency divider circuit 1 without the delay circuit 17
6 may be directly input to the sample hold circuit 30 and used as a sample hold control signal. In this case, as shown in 26 of Figure 2), the sample contains H
Since a level signal is output, it is sufficient to input this signal to the inverter element and input the output of the inverter element to the sample-and-hold circuit 30.

The output of the sample and hold circuit 30 to which the output of the power detection circuit 8 is input is as shown in FIG. Thick line part 28° 33.34 in Figure 2 (f)
indicates the sample period. The output of the sample and hold circuit 30 is compared with the output of the power setting circuit 12 and amplified by the error amplification circuit 13, and the error amplification circuit 13 performs feedback control using the sample and hold circuit 3o. The output shown in Figure 2 (g) is obtained. Overshoot 2 in Figure 2 (G)
9, when the waveform rises, there is a signal transmission delay in the power start-up system, and due to this delay, the output of the error amplification circuit 13 remains large for a very short time (for example, 1 to 2μ5ec). There is no problem with the above.

Further, the sample-hold circuit of the present invention always starts from a sample as shown in FIG. 2(E) at the rising edge of the waveform, and is designed to reduce the overshoot 29 shown in FIG. 2(G).

Furthermore, the delay circuit 17 is designed to prevent the overshoot 29 shown in FIG. , is effective when the waveform rise is extremely fast.

In other words, in the case of a combination where the waveform rise is extremely fast and the sampling frequency is low, if the hold period is long, the output will be extended during the hold period, and closed-loop feedback control will be performed in the subsequent sample period, resulting in the extended output. It takes a while to hold down the output, but the output increases and is slow. If the delay circuit 17 is used, closed-loop feedback control is performed in the sample period during the delay time, so the problem of output increase is solved.

Further, the output is synchronously input using the synchronous circuit 16, and at the same time, sample and hold is started in synchronization with the rising edge of the synchronous circuit 15. Also, a second
The provision of a synchronization circuit 21 to synchronize the output of the delay circuit 17 so that it starts up repeatedly with an accurate delay time without variation was also taken into consideration in order to reduce the overshoot 29 shown in Fig. 2 (g). It is.

In addition, ignoring the above synchronization, the waveform setting circuit 1
1 is input to the delay time circuit 20 of the delay circuit 17,
The output of the delay time circuit 20 may be directly input to the inverter element 22. Furthermore, when the output of the synchronization circuit 16 is input to the delay time circuit 20 and the output of the delay time circuit 2o is directly input to the inverter element 22, only the start of counting the delay time can be synchronized, and repeat fluctuations can be reduced. Furthermore, the output of the synchronous circuit 16 causes the second synchronous circuit 2 of the delay circuit 17 to
If 1 is used, the start and end of delay time counting can be synchronized, and an accurate delay time of 1 with little variation can be provided. Furthermore, the clock signal generation circuit 14 in FIG.
The output may be directly input to the sample and hold circuit without the delay circuit 1γ and the frequency dividing circuit 16.

The clock signal generation circuit 14 and frequency division circuit 16 in FIG.
The sample time and hold time of the sample and hold circuit 3o are set. Here, we will explain the setting guideline for the sampling time +1fi and the hold time.
When the gain is 10 to 20 times, the sampling time is set to 1/1 to V3 of the signal transmission delay time TD of the power start-up system including the high frequency output detection circuit, although it depends on the gain. As for the sampling time, if the sample-and-hold IC element used in the sample-and-hold circuit 30 is fast, a fast and short sampling time is preferred. As the sample time becomes longer, the disadvantages of the closed system appear because the input to the error amplifier circuit varies. Further, the hold time is set to 2 to 3 times the TD. If TD is set to less than twice TD, for example, the same value as TD, positive feedback may occur and damping may occur.In addition, if it is made shorter than 2 times TD, the effect of using the sample and hold circuit is lost. On the other hand, if the hold time is long, it becomes impossible to compensate for instantaneous spike-like disturbances.

From the above, set the sample time to 1/1 to Koma of TI), set the hold time to 2 to 3 times TI), and check with the actual machine.
Reconfigure the settings taking into account the above trends. As an actual example, the sample time is 1.5 μsec, and the hold time is 3 μ5e.
SC, therefore, the sampling frequency is 222Kl (z, etc. can be considered as 0). Note that FIG. 3 shows the case where the waveform setting is in pulse mode.

Effects of the Invention As described above, in the present invention, by using the sample and hold circuit, the input to the error amplifier circuit does not fluctuate and remains constant during the hold period, so that stable semi-closed feedback control can be performed. In addition, by using a delay circuit and a synchronization circuit, the power start-up system and the sample-and-hold circuit can be synchronized, so the feedbank system remains stable even when the high-frequency output is rising or falling in a waveform other than the steady state, and the sample-and-hold circuit The disadvantages of using can be removed without any problems.

[Brief explanation of the drawing]

FIG. 1 is a control diagram of a high frequency power source according to the present invention, FIG. 2 is a signal waveform diagram of the main part of FIG. 2, and FIG. 3 is a control block diagram of a conventional high frequency power source. 11...Waveform setting circuit, 13...-Error amplifier circuit, 15...Synchronization circuit, 16...Frequency division circuit, 17...Delay circuit, 30 ...Sample and hold circuit. Figure 2 - Leap → 96-

Claims (6)

[Claims] (1) A power detection circuit that detects high frequency output, a sample hold circuit that samples and holds the output of the power detection circuit, a power setting circuit that sets the magnitude of the high frequency output, and a power detection circuit that samples and holds the output of the power detection circuit, and a power setting circuit that sets the magnitude of the high frequency output. an error amplifier circuit that feedback-controls the high-frequency output so that the
a clock signal generation circuit for setting the sampling frequency of the sample and hold circuit, the output of the power detection circuit is input to the sample and hold circuit, and the output of the sample and hold circuit and the output of the power setting circuit are connected to A high frequency power supply control device, characterized in that the signal is input to an error amplifier circuit, the output of the clock signal generation circuit is input to the sample hold circuit, and the high frequency output is feedback-controlled using the sample hold circuit. (2) A waveform setting circuit for setting a pulse mode or CW mode waveform is provided with a delay circuit, and the output of the waveform setting circuit and the output of the clock signal generation circuit are input to the delay circuit, and the output of the delay circuit is 2. The high frequency power supply control device according to claim 1, wherein the output is input to the sample and hold circuit, and feedback control of the high frequency output using the sample and hold circuit is started with a delay. (3) The output of the clock signal generation circuit is input to a frequency divider circuit, the output of the frequency divider circuit is input to the sample hold circuit or the delay circuit, and the frequency divider circuit is used for the sampling frequency of the sample hold circuit. A high frequency power supply control device according to claim 1 or 2, characterized in that: (4) Input the output of the clock signal generation circuit and the output of the waveform setting circuit into a synchronous circuit, input the output of the synchronous circuit into a switch circuit that turns on/off the high frequency output, and synchronize the high frequency output. The high frequency power supply control device according to any one of claims 1 to 3, characterized in that the high frequency power supply control device performs sampling and holding in synchronization at the same time as when the power is turned on. (5) The output of the synchronous circuit is input to the input of the delay circuit instead of the output of the waveform setting circuit, and the delay time is counted from the rise of the output of the synchronous circuit. The high frequency power supply control device according to any one of the first to fourth items. (6) A second synchronization circuit is provided in the delay circuit, and the second synchronization circuit is provided in the delay circuit.
an output of a delay timer circuit in the delay circuit to a synchronous circuit of the synchronous circuit;
Claims 1 to 5 are characterized in that the output of the clock signal generation circuit or the output of the frequency dividing circuit is input, and the output of the delay circuit is raised in synchronization. The high frequency power supply control device according to any one of the above.