JPH03123136A - Burst synchronizing circuit - Google Patents

Abstract

PURPOSE:To correctly obtain the timing of data brought to multivalued FM demodulation even in the case there are many noises by detecting the receiving data obtained by a binary frequency modulation(FM) demodulator by a unique word(UW) detecting circuit. CONSTITUTION:A bit timing extracting circuit 4 outputs a clock 104 being a bit timing of receiving data 103. A binary FM demodulator 9 uses this clock 104 and executes a binary frequency demodulation from a signal 102, and outputs receiving data 106. A UW detecting circuit 5 detects a UW 202 of a burst signal 200 from in the receiving data 106, and outputs a timing signal 105 for showing the timing for starting the data 203. In such a way, even in the case there are many noises, the timing of data brought to multivalued FM demodulation can be obtained correctly, and the data can be demodulated correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a burst synchronization circuit, and particularly to a synchronization device for burst communication using a multilevel frequency modulation method in wireless communication.

[Conventional technology]

In the field of wireless communication, burst communication is performed as is well known. A burst signal used in this burst communication has a format as shown in FIG.

The burst signal 200 shown in FIG. 2 is composed of a clock extraction signal (BTR) 201, a unique word (UW) 202 for burst timing extraction, and data 203. Here, when using a multi-value frequency modulation (FM) method, the entire burst signal 200 is
M is multiplied.

FIG. 3 is a block diagram showing a burst synchronization circuit of an apparatus for demodulating burst signal 200.

The burst synchronization circuit shown in FIG. 3 includes a frequency discriminator 2 that demodulates the frequency from a multi-value FM signal 101 applied to an input terminal 1, and a multi-value FM signal that takes in a signal 102 from the frequency discriminator 2 and converts it into received data 103. A demodulator 3, a bit timing extraction circuit 4 that reproduces a clock 104 from a signal 102 from the frequency discriminator 2, and a timing extraction circuit 4 that receives received data 103 from the multilevel FM demodulator 3 and the clock 104 from the bit timing extraction circuit 4. signal 10
5 and a unique word (UW) detection circuit 5 that generates a clock 10.
4 can be output from the output terminal 7, and a timing signal 105 can be output from the output terminal 8.

Next, the operation of such a burst synchronization circuit will be explained.

In order to correctly demodulate the burst signal 200, the BTR
Get the timing of 1 bit with 201, then UW
In step 202, the timing at which the data 203 starts must be obtained.

A multilevel FM signal 101 applied to an input terminal 1 is frequency demodulated by a frequency discriminator 2 and output as a signal 102. The signal 102 is supplied to the multilevel FM demodulator 3 and the bit timing extraction circuit 4. The multilevel FM demodulator 3 converts the signal 202 into received data 103 and supplies the received data 103 to the UW detection circuit 5 and output terminal 6.

On the other hand, the bit timing extraction circuit 4 extracts the burst signal 2 from the burst signal 2.
Extract the bit timing from BTR201 of 00,
A clock 10 is connected to the multilevel FM demodulator 3 and the UW detection circuit 5.
4. The UW detection circuit 5 monitors the captured received data 103 and clock 104, and thereby
The position of the UW 202 is detected and the detected position is output from the output terminal 8 as a timing signal 1°5.

By using this clock 104 and timing signal 1°5, a multi-value FM signal 101 (
Received data 10 which is a demodulated signal of burst signal 200)
Data 203 can be obtained from the data 203 from 3 without error.

[Problem to be solved by the invention]

In the conventional burst synchronization circuit described above, since the UW detection circuit 5 extracts the timing from the reception data 103 output from the multilevel FM demodulator 3, the timing cannot be extracted correctly when there is a lot of noise. There was a drawback.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a burst communication synchronization port that can reliably acquire data timing without being affected by noise or the like.

[Means to solve the problem]

The burst synchronization circuit of the present invention includes a frequency discriminator that demodulates the frequency from a multilevel FM signal, a bit timing extraction circuit that reproduces a clock from the output signal from the frequency discriminator, and an output signal and bit timing from the frequency discriminator. A multilevel FM demodulator that takes in the clock from the extraction circuit and converts it into received data; a binary FM demodulator that takes in the output signal from the frequency discriminator and the clock from the bit timing extraction circuit and outputs the received data; value F
It is equipped with a unique word detection circuit that generates a timing signal from data received from the M demodulator.

As described above, the present invention uses a binary FM demodulator to demodulate a unique word subjected to binary FM, and the received data obtained thereby is detected by a unique word detection circuit. Also, the timing of multilevel FM demodulated data can be correctly acquired.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Components shown in FIG. 1 that are the same as those in FIG. 3 will be described with the same reference numerals.

The burst synchronization circuit shown in FIG. 1 includes a frequency discriminator 2♂ that demodulates the frequency from a multi-level FM signal 101 applied to an input terminal 1, and a bit timing that reproduces a clock 104 from an output signal 102 from the frequency discriminator 2. An extraction circuit 4, a multi-level FM demodulator 3 that takes in the output signal 102 from the frequency discriminator 2 and the clock 104 from the bit timing extraction circuit 4 and converts it into received data 103, and an output signal 102 from the frequency discriminator 2 and It includes a binary FM demodulator 9 that takes in a clock 104 from the bit timing extraction circuit 4 and outputs received data 106, and a UW detection circuit 5 that generates a timing signal 105 from the received data 106 from the binary FM demodulator 9. , the received data 103 can be outputted from the output terminal 6, the clock 104 can be outputted from the output terminal 7, and the timing signal 105 can be outputted from the output terminal 8.

The operation of such an embodiment will be explained.

The bit timing extraction circuit 4 outputs a clock 104 that is the bit timing of the received data 103. The binary FM demodulator 9 uses this clock 104 to generate the signal 10
Binary frequency demodulation is performed from 2 and outputs received data 106. The received data 106 is supplied to the UW detection circuit 5. The UW detection circuit 5 detects the UW 202 of the burst signal 200 from the captured received data 106, and detects the timing signal 10 representing the start timing of the data 203.
Outputs 5. This timing signal 105 is output from the output terminal 8.
is output from. Therefore, using the timing signal 105 and the clock 104, the data 203 of the burst signal 200 can be correctly demodulated from the received data 103.

In this way, in this embodiment, the binary FM demodulator 9 is used to demodulate the unique word subjected to binary FM, and the UW detection circuit 5 extracts the unique word 202 from the received data 106 obtained by the binary FM demodulator 9. Since the detection is performed, the multi-level FM demodulated data 203 can be correctly demodulated even when there is a lot of noise.

〔Effect of the invention〕

As explained above, in the present invention, a binary FM demodulator is used to demodulate a unique word subjected to binary FM, and a unique word detection circuit detects the unique word from the received data obtained thereby, so that noise is eliminated. Even when there are many signals, the timing of multi-level FM demodulated data can be correctly acquired and the data can be demodulated correctly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the burst synchronization circuit of the present invention, FIG. 2 is a diagram showing the format of a burst synchronization signal, and FIG. 3 is a block diagram showing a conventional burst synchronization circuit. 2...Frequency discriminator, 3...Multi-value FM
Demodulator, 4...Bit timing extraction circuit, 5
... UW detection circuit, 9 ... Binary FM demodulator.

Claims (1)

[Scope of Claims] A frequency discriminator that performs frequency demodulation from a multilevel FM signal, a bit timing extraction circuit that reproduces a clock from an output signal from the frequency discriminator, an output signal from the frequency discriminator, and the bit timing. a multilevel FM demodulator that takes in the clock from the extraction circuit and converts it into received data; a binary FM demodulator that takes in the output signal from the frequency discriminator and the clock from the bit timing extraction circuit and outputs the received data; A burst synchronization circuit comprising a unique word detection circuit that generates a timing signal from data received from the binary FM demodulator.