JPH08331118A - Method and device for reference clock regeneration of digital radio telephone system - Google Patents

Abstract

PURPOSE: To judge whether or not a reference clock is regenerated (synchronism is established) by using data in a stable area in the latter half of data for clock regeneration. CONSTITUTION: The regeneration of the reference clock from the data for clock regeneration by a reference clock generating part 13 is performed by executing the regeneration in a mode with speed higher than that when ordinary data is obtained. A data string of data for clock regeneration demodulated based on a regenerated clock is judged whether or not it coincides with prescribed comparison digital data. It is judged that the reference clock is regenerated correctly and the synchronism is established when the number of times of coincidence of a judged result reaches at a prescribed value. Moreover, the comparison digital data consists of the same or double number of bits of one time of a repeating part in the data for clock regeneration. Also, it is desirable to set the same number of bits. Moreover, the data in an unstable area between prescribed number of bits at a time to start the reception of a slot is inhibited to use in judgement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for reproducing a reference clock for a digital radio telephone device, and more specifically, determining whether or not the reference clock has been correctly reproduced (synchronization has been established). Regarding the improvement of the method.

[0002]

2. Description of the Related Art In a digital radio telephone apparatus of a type that shares one frequency band when transmitting PHS and other transmission / reception signals to each other, for example, transmission / reception signals are compressed to perform time division multiplexing (TDM) communication. Be seen. Then, on the receiving side, the compressed signal is reproduced. At this time, the synchronous clock is reproduced based on the synchronous signal included in the received signal, and the received signal of the frame of the slot is reproduced based on the reproduced clock. I am supposed to do it.

To recover the clock, a general received signal is differentiated to detect a level change of the signal, the differential waveform is full-wave rectified to repeatedly generate frequency components, and the full-wave rectified waveform is resonated. The frequency component is extracted by applying it to a circuit (also using a PLL circuit if necessary), a rectangular wave whose resonance circuit output waveform is leveled to a certain level through a limiter is generated, and the rectangular wave is used as a reproduction clock. ing. Then, the reference clock in the modem (demodulator) is adjusted to the reproduced clock (pulse width and phase are matched).

The above-mentioned clock reproduction is performed using the data in the preamble PR transmitted to the head portion of one slot. That is, 1 of the received data
The structure of one slot as a unit is 240 bits in the case of PHS, and the specific data structure is as shown in FIG. As shown in the figure, one slot has 4 bits as the ramp time R for transient response in order from the beginning.
There are 2 bits as the start symbol SS and then 62 bits as the preamble PR for the clock reproduction data. After that, a word synchronization signal (for controlling the frame or for determining the slot type (control / communication)) In case of PHS, 3 as unique word UW)
There are 2 bits, and the above is the overhead signal. Then, following this overhead signal portion, there are 108 bits as an actual communication data portion CAC, and further there are 16 bits as an error check CRC, and finally there is a guard bit (processing delay of a communication terminal occupying the slot between slots). Of 16 bits is secured as a non-signal section for allowing the deviation of (1) and the deviation of transmission delay.

The start symbol SS and the preamble PR are composed of data in which "1001" is repeated as shown in the figure. Therefore, the synchronization is established by comparing the synchronization data received from the beginning of the start symbol SS with the comparison digital data (1001100110011001), and if they match, it is assumed that the synchronization is completed, the clock information at that time is stored, and thereafter, the slot is stored. Is read based on the stored clock information.

[0006]

However, the above-mentioned conventional method has the following problems. That is, during normal clock reproduction (when acquiring preamble data)
Is to increase the gain of the PLL to read data in the high-speed mode so that the synchronization is established quickly, and when the actual data is read after the establishment, the gain of the PLL is adjusted so that the synchronization is not lost due to fading noise. Set to low to read data in low speed mode. And
On the receiving side, the communication data portion CA for a certain slot
C, error check CRC, etc. are read in the low speed mode, and in the next slot, the reading is first started in the high speed mode for establishing synchronization. Therefore, the low speed mode is switched to the high speed mode at the boundary between the slots. Then
Since this switching is handled by changing the gain of the PLL, an unstable operation state occurs immediately after switching. And
The unstable state continues for about 32 bits.

That is, the first half of the preamble PR is unstable and easily causes an error, and the clock information detected in this area is inaccurate. Therefore, FIG.
As shown in, the first 12 bits cause an error and the clock cannot be recovered (synchronization cannot be established).
Further, even if it is determined that 12 bits of the clock reproduced based on the input data of the preamble PR in the unstable area coincides with the comparison digital data, and that synchronization is established without error (the second 12 bits shown in the figure). Min), because it is based on the data of the unstable region as described above,
It is not always suitable as a reference clock that is used as a reference for reading the stable region thereafter. That is, if the subsequent processing is performed based on the clock information in which the synchronization is established in the unstable area, the data may not be read correctly.

On the other hand, in order to solve such a problem, the unstable area (32 bits from the beginning) is not used for the determination of synchronization establishment, but the latter 32 bits of the preamble PR data may be used for the determination. Conceivable. But conventionally,
If it does not match the comparison digital data continuously for 12 bits, it will not be considered as the establishment of synchronization, so there are only two opportunities for comparison (the third time there are only 8 bits and the number of bits is insufficient), and for some reason the first occurrence happens to occur. If even one bit out of 12 bits may have different data, an error will occur there, and the chance of establishing synchronization is only the next 12 bits. Therefore, there is a high possibility that synchronization cannot be established,
Lack of practicality.

In order to solve the above problem, if the number of bits of the comparison digital data is reduced, the chances of determining the synchronization establishment can be increased to three times or more even if the latter half 32 bits (4 bits tentatively). If it is lowered to 8 times, there is an opportunity for determination 8 times), and the possibility that synchronization cannot be established is reduced. However, if the number of bits is small, there is a possibility that the synchronization coincides with the comparison digital data even though the synchronization is not established, and the synchronization is erroneously recognized.

The present invention has been made in view of the above background. An object of the present invention is to solve the above problems and to reproduce a clock generated based on data in the stable region in the latter half of the clock reproduction data. Whether or not it is possible to accurately judge the suitability based on the input data detected according to the clock as compared with the comparison data, and by making the number of bits of the comparison digital data shorter, the judgment cannot be made, and the number of bits is small. Another object of the present invention is to provide a reference clock recovery method and device for a digital wireless telephone device that can make a correct determination.

[0011]

In order to achieve the above object, in a reference clock reproducing method and apparatus for a digital wireless telephone device according to the present invention, a reference clock is reproduced from clock reproducing data (preamble data in the embodiment). In this case, the high speed mode, which is higher than the speed at the time of the normal data acquisition, is used. Then, it is determined whether or not the data string of the clock reproduction data demodulated based on the reproduced clock matches a predetermined comparison digital data, and when the number of times the judgment result is a predetermined value, the reference clock Was correctly played and the synchronization was established. Further, the comparison digital data is configured to have a bit number that is the same as or twice the number of bits of the repeated portion in the clock reproduction data. It is more preferable that they are the same. Furthermore, the data in the unstable region between the predetermined number of bits at the beginning of reception of the slot is not used for the determination (claim 1).

[0012] Further, after it is determined that the synchronization has been established, it is more preferable to reduce the speed to the normal data acquisition time during the reception of the clock reproduction data, and thereafter acquire the data in the low speed mode ( Claim 2).

Further, as a clock reproducing apparatus suitable for carrying out the above method, a clock extracting means for reproducing a clock from the clock reproducing data, a receiving speed switchable between a high speed mode and a low speed mode, and A reference clock generating means for generating a reference clock in synchronization with the clock signal extracted by the clock extracting means and for timing data acquisition in the slot, and input data forming the slot are generated by the reference clock generating means. And a demodulating means for demodulating based on the reference clock. Then, the clock regenerating data demodulated by the demodulating means is obtained, and the detecting means (in the embodiment, the shift register 2) for detecting the data portion that matches the comparison digital data in the data.
0, exclusive OR elements 21a to 21d and AND element 2
2), counting means for counting the detection result by the detecting means, and certifying means for certifying that the synchronization is established when the counting result by the counting means reaches a reference value (in the embodiment, an n-time counting counter 25). However, the counting means and the recognizing means are used in combination, and the canceling means for preventing the data in the unstable area between the predetermined number of bits at the beginning of reception of the slot from contributing to the determination (in the embodiment, Counter 2
3 and a comparator 24) (claim 3).

[0014]

When the clock is reproduced, the data is acquired in the high speed mode, the noise is allowed, and the synchronization is quickly established. Therefore, the initial data after switching to the high speed mode is unstable. Therefore, the unstable area from the beginning to the predetermined number of bits is not used for determining whether or not synchronization is established. Therefore, erroneous determination is suppressed.

On the other hand, by canceling the first half of the clock recovery data, the number of data actually used for the determination is reduced. However, the comparison digital data for certifying that the clock can be reproduced is the same as the repeated data part or doubled, so the number of opportunities for comparison increases, so that it is possible to reliably establish the synchronization without failing to certify. Certified as unestablished.

Further, it is determined that the clock has been correctly reproduced only by detecting the comparison digital data having the predetermined number of bits a plurality of times. Therefore, even if the number of bits of one comparison digital data is short, there is no possibility of erroneous recognition.

According to a second aspect of the present invention, if the synchronization is established, the high speed mode is switched to the low speed mode to receive even if the clock reproduction data is being received. As a result, the subsequent data acquisition is stable in the state of being strong against noise and not out of synchronization.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a reference clock reproducing method and device for a digital radio telephone apparatus according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a clock recovery device according to the present invention. As shown in the figure,
The received input data is given to the modem 10, demodulated there, and then sent to a data content detection unit (not shown).

Then, the input data input into the modem 10 is transferred in parallel to the demodulation section 11 and the clock data extraction section 12. The demodulation section 11 reads input data based on the reference clock signal from the reference clock generation section 13, performs demodulation processing, and outputs the demodulated data. Since the demodulation process is the same as the conventional one, its description is omitted.

The reference clock signal generated and output by the reference clock generation unit 13 is also given to the comparison unit 13 and compared with the clock signal generated from the received input data extracted by the clock data extraction unit 12. Then, feedback control is performed based on the detection result from the comparison unit 13 so that the phase and pulse width match the clock signal. The process of matching the phase is shown in FIG. 2, and the process of matching the pulse width is shown in FIG.

By controlling in this way, the demodulation unit 1
The reference clock that is the read timing in 1 is
It becomes possible to demodulate correct data by matching the data timing of the input data. Note that the adjustment of the reference clock signal based on the determination result from the comparison unit 13 is performed by appropriately adjusting the gain of the PLL or the like, but since the specific processing is the same as the conventional one, the description thereof is omitted. To do.

Then, in the clock data extraction unit 12,
As shown in the conventional example, the received signal (input data) is differentiated to detect the level change of the signal, the differential waveform is full-wave rectified to repeatedly generate frequency components, and the full-wave rectified waveform is used as a resonance circuit. (A PLL circuit is also used if necessary) to extract a frequency component and generate a rectangular wave whose resonance circuit output waveform is leveled to a constant level through a limiter.

Further, when the clock is reproduced as described above, the PL
The gain of L is increased, the preamble data PR in the input data is acquired at high speed in the high speed mode, and the PLL is used after the reproduction.
The gain of is reduced to acquire the unique word UW in the input data and the subsequent communication content in the low speed mode without being affected by noise (see FIG. 3).

Here, in the present invention, the PR detection circuit 15 for judging whether or not the clock reproduction is correctly performed is connected in parallel to the output of the modem 10. This PR
The detection circuit 15 detects when there is a data string in which the input data is continuous with “1001”, counts the number of times of detection, and certifies that the clock can be correctly reproduced when the number of times is four. The circuit configuration is shown in FIG.

That is, as shown in the figure, first, the demodulated signal output from the modem 10 is the shift register 2
The values are sequentially input to 0. The shift register 20 is a serial input parallel output type in which four stages are connected in series, and shifts every time the reproduced reference clock signal CLK is input. As a result, the reproduced reference clock signal is based on the preamble PR data. Therefore, when reproduced normally, the timing at which the input data is input matches the timing at which the reference clock signal shifts. To do.

Each output of the shift register 20 is connected to one input terminal of each of the exclusive OR elements 21a to 21d. Further, the other input terminals of the exclusive OR elements 21a and 21d on both sides (elements to which the outputs of the first-stage and fourth-stage shift registers are input) are grounded (L), while the other input terminals are left. Exclusive OR element 21
The other input terminals of b and 21c are connected to the power supply voltage Vcc (H). Thus, when the outputs of the four shift registers 20 are "1001", all the exclusive OR elements 2
The outputs of 1a to 21d become H.

Then, the exclusive OR elements 21a to 21
Each output of 1d is connected to the input terminal of the AND element 22. Further, the reference clock CLK is inputted to the counter 23, counts the number of clocks, and the output of the counter 23 is given to the comparator 24, where the reference value (32) is given.
When the output value of the counter 23 becomes larger than 32, the output of the comparator 24 becomes H, and the output of the comparator 24 is also given to the AND element 22.

The counter 23 is reset when the reception of each slot is started (start symbol SS reception). As a result, the output of the comparator 24 is always L for the 32 bits from the beginning of the input data for a certain slot, and the output of the AND element 22 is L regardless of the data string of the input data. And 33
After the bit, the output of the comparator 24 becomes H. Therefore, when the output of the shift register 20 is "1001", all the input terminals of the AND element 22 become H, so that the output is also H.
Becomes

Further, the output of the AND element 22 is given to the n-time counting counter 25, and the n-time counting counter 25
Then, the number of times the input becomes H is counted, and when n = 4,
The detection signal (H) is outputted, and the output of the n-time counting counter 25 is given to the reference clock generator 13. Then, the reference clock generation unit 13 is configured to, when receiving the detection signal, determine that the clock reproduction for the slot is completed, store the clock state at that time, and convert to the low speed mode based on that. It

Next, an embodiment of the reference clock reproducing method of the digital radio telephone apparatus according to the present invention will be described based on the above-mentioned embodiment. When you first receive a slot,
Switch to high-speed mode and get input data. That is, at the beginning of reception, the preamble P for clock recovery is used.
Since it is R data, it is demodulated by the demodulation unit 11 in the modem 10, and the demodulated signal is given to the PR detection unit 15. At the same time, the clock data extraction unit 12 reproduces a clock signal from the input data, and the comparison unit 14 compares the reference clocks generated by the reference clock generation unit 13 incorporated in the modem 10, and the two match. As described above, the reference clock is adjusted to the extracted and reproduced clock signal. Then, the PR detection unit 15 determines whether or not the matching process, that is, the clock reproduction is correctly performed.

Then, the demodulated data is sequentially shifted from the first bit to the shift register 2 in the PR detection circuit 15.
0, the shift register 20 shifts according to the reproduced clock signal CLK. As a result, assuming that the demodulated preamble PR data is “10011001 ...” As shown in FIG. 4, the output of the shift register when the clock signal is input four times becomes “1001”, which is exclusive. OR element 21
The outputs of a to 21d are all H. Further, when the clock signal is input five times, since the data of the second to fifth bits from the beginning, that is, "0011", is stored in the shift register, the exclusive OR element 21a, The output of 21c becomes L. Therefore, if the output of the counter 24 is H, the shift register 2
AND element 2 when "1001" is stored in 0
The output of 2 becomes H. Therefore, in the present embodiment, four consecutive bits of input data are subject to inspection, and the number of times that the data string of the input data includes "1001" is n.
It is counted by the counting counter 25.

On the other hand, the counter 23 is reset with the start of reception of each slot, the clock signal is counted, the count value is given to the comparator 24, and the reference value (3
Compare with 2). Therefore, the output from the AND element 22 is always L from the first 32 bits, and even if the data string "1001" exists in the input data during that period, the n-count counter 25 does not count.
After the first 33 bits, the count value of the counter 23 becomes larger than 32, so that the output of the comparator 24 is always H. Therefore, the number of times that there are 4 bits consecutive "1001" in the input data 33 bits or more after the start of reception of the slot is counted by the n-count counter 25 and detected when the count value becomes 4. The signal is output. Based on the detection signal, it is determined that the clock reproduction is completed, the reference clock generation unit 13 stores the clock condition at that time, and then the reference clock signal is generated based on that (actual clock timing is changed from the high speed mode to the low speed mode). Different).

That is, assuming that the data string to be acquired is as shown in FIG. 5, the initial data after switching to the high speed mode is noisy and unstable, and as shown in the figure, 32 bits from the beginning are not stored. It is often a stable region. Therefore, in this embodiment, the leading 3
The two bits are canceled so as not to be used for determining whether or not the clock can be reproduced, thereby suppressing an erroneous determination. Furthermore, by using the first half portion of the preamble data as the cancel portion in this way, the number of data actually used for the determination is reduced to 32 bits, but as comparison digital data for certifying that the clock can be reproduced, Since it was reduced to 4 bits of "1001", the opportunity to compare 8 times in total increased,
The risk of being unable to be certified is suppressed as much as possible.

Further, since the comparison digital data is shortened to 4 bits, the possibility of erroneous recognition increases when there is an accidental data string. However, in this embodiment, the 4-bit comparison digital data is detected four times in total. As a result, it is determined that the clock reproduction is correctly performed for the first time. Therefore, even if the comparison digital data for one time is as short as 4 bits, the clock data is present multiple times (4 times in the embodiment) between 32 bits. There is no risk of accidentally recognizing other data, so there is no risk of misidentification. Moreover, since it is only necessary to match four times in total (not four consecutive times), a detection error (no match) may occur four times.
(Continuing to match the conventional 12 bits consecutively, the first 3
If two bits are canceled, only one error is recognized), and even at that point, the possibility of being undetectable is suppressed as much as possible.

Further, in this embodiment, when the reference clock generator 13 receives the detection signal, the high speed mode is switched to the low speed mode. That is, in the prior art, in the preamble area, data was acquired in the high-speed mode, and the unique word was switched to the low-speed mode. However, in this embodiment, the preamble data is switched to the low-speed mode even during acquisition of the preamble data, and the synchronization is strong against noise and the synchronization is not lost. Then, the subsequent data acquisition is performed.

As an example, as shown in FIG. 5, in the shortest case, synchronization is established at the 48th bit (no error), then the low speed mode is set, and after the acquisition of the unique word, Even if there is an error in the middle of the process, synchronization is established if a match with "1001" is detected four times in total, then the low speed mode is entered, and the process proceeds to the acquisition of a uniword.

In the above-described embodiment, the comparison digital data which coincides once is 4 bits of "1001", and when the number of coincidences with such data is 4 times, the establishment of synchronization is recognized. However, the present invention is not limited to this, and can take any combination other than 4 bits and other than 4 times. In addition, the cancellation part in the first half is 3
The number of bits is not limited to 2 bits, and various values can be taken according to the situation.

Further, in the above-mentioned embodiment, the clock reproduction processing is carried out from the beginning of the slot reception, and the processing for judging whether or not the clock is established is not carried out in the first half (32 bits). However, the clock recovery itself may not be performed in the first half of the cancellation portion (in that case, the clock for the demodulation processing is performed by the internal clock signal). However, in such a case, there is a high possibility that the read timing of the input data cannot be performed correctly.

[0039]

As described above, in the reference clock reproducing method and device for the digital radio telephone apparatus according to the present invention, the first half of the clock reproducing data is used for judging whether or not the synchronization is established. The input data detected according to the reproduction clock generated based on the data in the stable region can be accurately identified. Moreover, the number of pieces of comparison digital data, which is a reference for whether or not they match,
Since the number of bits of the repeated portion is equal to or twice that of the repeated portion, the continuous data string is short, and it is possible to suppress the possibility of undecidable as there are many opportunities for comparison. Moreover, not only is the length shortened, but since synchronization is established by detecting a data string that matches the comparison digital data multiple times, even if the number of bits of one reference data is small, correct identification is possible. It can be carried out.

Further, if the mode is switched to the low speed mode even after receiving the data for clock reproduction after the establishment of the synchronization is established, it is possible to ensure the reliability based on the once determined reference clock without being affected by noise. The data can be acquired at any time, and the loss of synchronization after that can be suppressed as much as possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a reference clock reproducing device of a digital wireless telephone device according to the present invention.

FIG. 2 is a time chart diagram illustrating how a clock and a reference clock are matched when forming a reference clock.

FIG. 3 is a diagram illustrating a high speed mode and a low speed mode.

FIG. 4 is a diagram showing an internal configuration of a PR detection circuit.

FIG. 5 is a diagram illustrating an embodiment of the method of the present invention.

FIG. 6 is a diagram illustrating a conventional method.

[Explanation of symbols]

 10 modem 11 demodulator 12 clock extractor 13 reference clock generator 14 comparator 15 PR detection circuit 20 shift register 21a to 21d exclusive OR 22 AND element 23 counter 24 comparator 25 n-count counter

Claims (3)

[Claims] 1. A reference clock used in a digital radiotelephone device, which is transmitted / received in slot units including at least clock reproduction data and then normal communication data, and is reproduced based on the clock reproduction data when the slot is received. In the method of reproducing the reference clock in the communication method for acquiring data based on the above, when the reference clock is reproduced from the clock reproduction data, the reproduction is performed at a higher speed than the speed at the time of the normal data acquisition. It is determined whether the data string of the clock reproduction data demodulated based on the generated clock matches the predetermined comparison digital data, and when the number of times the judgment result matches is a predetermined value, the reference clock is correct. It is confirmed that the data has been reproduced and synchronization has been established, and the comparison digital data is for the clock reproduction. The number of bits is the same as or twice as many as the number of bits of the repeated part in the data, and the data in the unstable area between the predetermined number of bits at the beginning of reception of the slot is not used for the determination. A method for recovering a reference clock for a digital wireless telephone device characterized by the above. 2. The digital radio according to claim 1, wherein after deciding that the synchronization has been established, the speed is reduced to the normal data acquisition speed during reception of the clock reproduction data. Reference clock recovery method for telephone equipment. 3. A reference clock mounted in a digital radio telephone device, which transmits / receives in slot units including at least clock reproduction data and then normal communication data, and reproduces based on the clock reproduction data when the slot is received. In the reference clock reproducing device in a communication system for acquiring data based on the above, in addition to the clock extracting means for reproducing a clock from the clock reproducing data, the receiving speed can be switched between a high speed mode and a low speed mode, and A reference clock generating means for generating a reference clock in synchronization with the clock signal extracted by the clock extracting means and for timing the data acquisition in the slot, and input data forming the slot are generated by the reference clock generating means. Demodulate based on the reference clock Demodulation means, detection means for acquiring the clock reproduction data demodulated by the demodulation means, and detecting a data portion that matches the comparison digital data existing in the data, and counting for counting the detection results by the detection means Means, a certifying means for certifying whether or not the synchronization is established based on the counting result by the counting means, and a canceling means for preventing the data in the unstable area between the predetermined number of bits at the beginning of the reception of the slot from contributing to the determination. And a reference clock regenerating device for a digital wireless telephone device.