JPH03116945A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To eliminate the leakage of a charge in a capacitor part and to make it possible to correspond to an increase in the integration of a semiconductor storage device by a method wherein the device is provided with an element isolation electrode layer, which is formed on the main surface of a semiconductor substrate in an isolation region through an insulating film and is arranged so as not to overlap with first and second impurity diffused regions. CONSTITUTION:An insulating film 21 is formed on the surface of a semiconductor substrate 1 in an element isolation region S, an electrostatic shielding electrode 22 is formed on the film 21 and low-concentration impurity diffused layers 7b and 7c are formed so as not to overlap partially with a high-concentration impurity diffused layer 6b. There is no overlap between the electrode 22 and the layer 7c and the electrode 22 and the layer 7c are in an offset state spaced from each other by a dimension (d). In such a way, the element isolation electrode layer is formed so as not to overlap with the high-concentration impurity diffused region and the low concentration impurity diffused regions. Thereby, a shielding effect due to the element isolation electrode layer is increased and the leakage of charge from the high-concentration impurity diffused region to a semiconductor substrate is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an improved element isolation structure.

[Background Art] In recent years, the demand for semiconductor memory devices has been rapidly increasing due to the remarkable spread of information devices such as computers. Furthermore, in terms of functionality, it is required to have a large storage capacity and be capable of high-speed operation. Along with this, technological development regarding higher integration, high-speed response, and high reliability of semiconductor memory devices is progressing.

Among semiconductor memory devices, DRAM (Dynamic RAM) is one that can input and output memory information randomly.
m Access Memory). In general, a DRAM is composed of a memory cell array, which has a storage capacity for storing a large amount of stored information, and peripheral circuits necessary for input/output with the outside.

FIG. 5 is a sectional view of a stunted capacitor memory cell in a conventional DRAM disclosed in, for example, Japanese Patent Publication No. 60-2784. As shown in FIG. 5, one memory cell 100 has one access transistor 20.
and one capacitor 30. For example, the memory cell 100 is surrounded by a field oxide film 2 formed on the surface of a p-type semiconductor substrate 1,
It is insulated and separated from adjacent memory cells. The access transistor 20 is located between, for example, n-type impurity diffusion layers 6a and 7a, and n-type impurity diffusion layers 6b and 7b formed on the surface of the semiconductor substrate 1, and has a thin gate. A gate electrode (word line) 4a is formed through an oxide film 3.

Impurity diffusion layers 6a and 6b are regions with high impurity concentration, and impurity diffusion layers 7a and 7b are regions with low impurity concentration.

The capacitor 30 is made of a conductive material such as polycrystalline silicon, and is formed by depositing a charge storage layer 8 for storing charges, a dielectric film 9 made of a dielectric material such as a nitride film or an oxide film, and a counter electrode 10. The charge storage layer 8 is connected to one impurity diffusion layer 6b and 7b functioning as a source-drain region of the access transistor 20. The bit line 1 is placed on the capacitor 30 via the insulating film 11.
2 is provided. Bit line 12 is electrically connected to the other impurity diffusion layers 6a and 7a.

Note that word line 4b formed on feed oxide film 2 is a word line of a memory cell (not shown) adjacent to memory cell 100 shown in FIG.

Next, the operation of the conventional DRAM will be explained.

DRAM has a charge storage layer 8. Dielectric film 9 and counter electrode 1
By controlling the voltage applied to the word line 4a to the capacitor 30 consisting of
charge is accumulated or discharged through this process.

By the way, DRAM memory cells are normally used as integrated circuits, so electrical isolation technology between each cell is important.
The CO5 method (selective oxidation method) is used on the -film surface. In this method, a p-type channel cut impurity 13 for preventing channel inversion, for example, is implanted into the isolation region between elements, and the semiconductor substrate in that region is selectively oxidized to form the isolation region. .

However, as the degree of circuit integration increases (particularly in megabit-class integrated circuits), the separation length of the isolation region becomes smaller than 1.0μ.
A portion below m is generated, and the isolation withstand voltage between elements decreases. In order to compensate for the isolation breakdown voltage that decreases due to the shortening of the isolation length and obtain a high breakdown voltage, the concentration of the channel cut impurity diffusion layer 13 must be made high.

However, the channel cut impurity diffusion layer 13
is in contact with the high concentration impurity diffusion layer 6b which is the contact part of the semiconductor substrate 1, and in this junction part 14,
A PN junction is formed. The junction breakdown voltage of this PN junction is
The higher the concentration of the channel cut impurity diffusion layer 13, the lower the concentration. Therefore, if the channel cut impurity is implanted at a high concentration to increase the isolation voltage, good isolation characteristics can be obtained between memory cells, but the p-type semiconductor substrate On the contrary, the junction breakdown voltage between 1 and the n-type high concentration impurity diffusion layer 6b decreases. Therefore, the charges accumulated in the charge storage layer 8 end up flowing out to the semiconductor substrate 1 through the channel cut impurity diffusion layer 13 as a leakage current.

[Problems to be Solved by the Invention] Conventional DRAM memory cells are configured as described above, so as the degree of integration of memory cells increases, it becomes necessary to miniaturize the isolation region to 1.0 μm or less. However, when the isolation breakdown voltage is increased, the junction breakdown voltage decreases, resulting in a problem in that the charges stored in the capacitor portion leak.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory device having an element isolation structure that prevents charge leakage from the capacitor portion and is compatible with high integration. It is said that

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a plurality of storage areas;
A semiconductor storage device comprising: a separation region provided between each storage area and electrically separating each storage area; the semiconductor storage device comprising: a semiconductor substrate having a main surface; A first impurity diffusion region with a high concentration, a second impurity diffusion region formed to extend from the first impurity diffusion region in the direction of the isolation region and with a lower concentration than the first impurity diffusion region, and a second impurity diffusion region in the isolation region. and an element isolation electrode layer formed on the main surface of the semiconductor substrate via an insulating film and arranged so as not to overlap the first and second impurity diffusion regions.

[Function] A constant voltage is constantly applied to the element isolation electrode layer in this invention. Thereby, the semiconductor regions are electrically shielded from each other by static electricity. The low concentration impurity diffusion region formed in the direction from the high concentration impurity diffusion region toward the isolation region relieves the electric field of the high concentration impurity diffusion region. This further improves the separation characteristics. Since the element bone 111m electrode layer is formed so as not to overlap with the high concentration impurity diffusion region and the low concentration impurity diffusion region, the shielding effect by the element separation electrode layer is strengthened, and the shielding effect from the high concentration impurity diffusion region to the semiconductor substrate is enhanced. leakage of charge is prevented.

[Embodiment of the Invention] FIG. 1 is a sectional view showing a portion of a memory cell array of a DRAM according to an embodiment of the invention. The memory cell 200 shown in FIG. 1 is the same as the memory cell 100 shown in FIG. 5 except for the structure of the element isolation region S, so the same parts are given the same reference numerals. The explanation will be omitted.

The element isolation method in the memory cell shown in FIG.
The method using the LOGO3 oxide film shown in the figure is changed to a method using an electrostatic shielding electrode. That is, an insulating film 2 is formed on the surface of the semiconductor substrate 1 in the element isolation region S.
1 is formed, and an electrostatic shielding electrode 22 is formed on the insulating film 21. Further, low concentration impurity diffusion layers 7b and 7c are formed so as to partially overlap the high concentration impurity diffusion layer 6b. Electrostatic shielding electrode 22 and low concentration impurity diffusion layer 7
c, there is no overlap, and they are offset by a distance d. That is, the projected portion of the electrostatic shielding electrode 22 onto the main surface of the semiconductor substrate 1 does not overlap the impurity diffusion layers 6b and 7c.

In this embodiment, the operation as a DRAM is similar to that of the conventional example.

In the device isolation method using the electrostatic shielding electrode 22, the electrostatic shielding electrode 22 is connected to ground or reverse biased (for example, in the case of an N-channel MOS memory,
negative voltage) is constantly applied. As a result, the potential of the substrate surface under the electrostatic shielding electrode 22 is made equal to or lower than the inversion threshold voltage, no current flows through the substrate surface under the electrostatic shielding electrode 22, and the elements are electrically isolated. .

If this method is used, unlike the LOGOS oxide film, there is no high concentration channel cut impurity diffusion region under the element isolation region, so when the element isolation region length is miniaturized to 1.08 m or less, high isolation In order to obtain a breakdown voltage, it is not necessary to increase the amount of impurity implanted as in the conventional example. Therefore, the junction breakdown voltage between the impurity diffusion layer 6b and the semiconductor substrate 1 is not lowered, and leakage current in the capacitor portion is not generated.

Next, the electrostatic shielding electrode 22 and the impurity diffusion layers 6b and 7C
The reason why these are set in an offset state and the reason why the low concentration impurity diffusion layer 7c is formed will be explained.

FIG. 2A shows an electrostatic shield electrode structure without an offset, and FIG. 2B shows an electrostatic shield electrode structure with an offset. In both FIGS. 2A and 2B, a word line 4b is formed on the electrostatic shielding electrode 22. In FIG.

In the isolation structure without offset shown in FIG. 2A, if the word line 4b formed above operates normally and operates at a voltage within the standard, there will be no problem with the isolation characteristics. When a high voltage is momentarily applied to the word line 4b (due to fluctuations in power supply voltage or noise, etc.), or when a voltage is locally applied to the electrostatic shielding electrode 22 itself due to noise or current due to α rays, The surface of the semiconductor substrate 1 under the element isolation region S enters a state similar to the inverted state of a MOS transistor, and that region becomes partially conductive, causing the adjacent capacitor to malfunction due to charge leakage. A problem arises in that the memory element does not function as a memory element.

On the other hand, in the offset type electrostatic shielding electrode shown in FIG. In other words, they are separated by the dimension d. Therefore, even if a voltage higher than the inversion threshold voltage is applied to the electrostatic shielding electrode 22 and the surface of the semiconductor substrate 1 directly under the electrostatic shielding electrode 22 becomes inverted, Directly below the side wall 23,
Since no inversion has occurred and the shielding state remains, as a result, the isolation region S continues to be shielded.

Therefore, compared to the structure shown in FIG. 2A, tolerance against disturbance factors such as instantaneous noise and fluctuations in power supply voltage is increased, and a highly reliable and highly integrated circuit can be obtained.

In addition, as shown in FIG. 2C, for example, a high concentration of n
When a low concentration, for example, n-type impurity diffusion layer 7C is formed so as to partially overlap the type impurity diffusion layer 6b,
Since the impurity diffusion layer 7C has a high resistance, the electric field generated by the charge applied to the high concentration impurity diffusion layer 6b is relaxed. Therefore, it becomes difficult for current to flow through the surface of the semiconductor substrate 1 under the element isolation region S, and element isolation characteristics are improved.

Note that the high concentration impurity diffusion layer 6b connected to the charge storage layer 8
The low concentration impurity diffusion layer 7b connected to the high concentration impurity diffusion layer 6b relaxes the electric field near the high concentration impurity diffusion layer 6b and prevents the generation of hot electrons flowing into the charge storage layer 8. This effect is particularly effective when the channel length under the gate is miniaturized to the extent of 1 μm or less.

Figures 38 to 3H show a DRAM according to an embodiment of the present invention.
It is a figure for explaining the manufacturing method.

Next, a method for manufacturing a DRAM according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3H.

Referring to FIG. 3A, channel impurities are implanted into semiconductor substrate 1 for threshold voltage control.

Next, referring to FIG. 3B, 5iO7 is placed on the semiconductor substrate 1.
A conductive layer 22 made of metal or polycrystalline silicon and serving as an electrostatic shielding electrode is formed on the insulating film 21, and an insulating film 24 is formed on the conductive layer 22.
is formed.

Next, referring to FIG. 3C, insulating films 21 and 24 and conductive layer 22 formed on semiconductor substrate 1 are patterned by a photolithography process and an anisotropic etching process.

Next, referring to FIG. 3D, the conductive layer 22 is formed by an insulating film.
A sidewall 23 is formed on the side of the.

Next, referring to FIG. 3E, a gate insulating film 3 for a word line is formed on the semiconductor substrate 1 and the insulating film 24 in the active region A. A conductive layer 4 and an insulating film 5 are formed.

Next, referring to FIG. 3F, the film deposited in the step shown in FIG. 3E is patterned by a photolithography process and an anisotropic etching process to form word lines 4a and 4b.
is formed. Next, the insulating film 5 on the word lines 4a and 4b is
A, 5b and the insulating films 23 and 24 of the electrostatic shielding electrode 22 are used as masks to implant impurity ions at a low concentration.

Next, referring to FIG. 3G, insulating film sidewalls 51a and 51b are formed on word lines 4a and 4b. At this time, the side wall 23 of the electrostatic shielding electrode 22
An insulating film is also deposited thereon, and the thickness of the sidewall 23 increases. Next, high concentration impurity ions are implanted using the insulating films 51a, 51b and the sidewalls 23 as masks.

The state after ion implantation is shown in FIG. 3H.

As shown in FIG. 3H, the diffusion layer formed by the implanted impurity is a low concentration implantation region 7a.

7b and 7C and heavily doped regions 6a and 6b, and the MO8 type transistor in the word line 4a portion is an LDD (Light 1y Dopped
Drain) structure.

Further, in the element isolation region S, the low concentration diffusion layer 7C does not diffuse directly under the electrostatic shielding electrode 22, and has an LDD structure with an offset structure.

Thereafter, a capacitor 30° interlayer insulating film 11 as shown in FIG. A bit line 12 is formed.

In the above embodiment, a stacked capacitor in which the charge storage layer 8 and the counter electrode 10 are simply stacked is used. However, as integrated circuits become highly miniaturized and highly integrated, the capacitance becomes extremely large. As a result, in memories such as DRAM, deterioration in refresh characteristics, soft error resistance, etc. becomes noticeable.

In order to solve this problem, a method of increasing the capacitance of the capacitor can be considered. For example, as shown in FIG. 4, by combining a cylindrical charge storage layer 15 with the charge storage layer 8, the surface area of the charge storage layer can be increased without increasing the area occupied on the substrate. , a method of increasing the capacity of charge accumulated between the electrode and the counter electrode 10 may be adopted.

By adopting the above method, the tolerance against charge leakage is increased, and the reliability with respect to refresh characteristics, soft error resistance, etc., which deteriorates due to miniaturization, can be improved by adopting the simple lamination type stacked capacitor of the above embodiment. Improved compared to the case.

Note that this invention is not limited to DRAM,
Any MOS type memory device can be applied.

[Effects of the Invention] As described above, according to the present invention, a so-called electrostatic shielding electrode is used as an element isolation method, and a method is adopted in which storage areas are isolated by electrically shielding them.
By adopting a so-called LDD structure for the drain and preventing the electrostatic shielding electrode from overlapping the impurity diffusion region having this LDD structure, the device can be miniaturized (1
, 0 μm or less), and a semiconductor memory device with less charge leakage when highly integrated can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a portion of a memory cell array of a DRAM according to an embodiment of the present invention. Figure 2A or Figure 2
FIG. C is a diagram for explaining the reason for setting the electrostatic shielding electrode and the impurity diffusion layer in an offset state and the reason for forming the low concentration impurity diffusion layer. Figures 3A to 3H
The figure is a sectional view showing a method of manufacturing a DRAM according to an embodiment of the present invention. FIG. 4 shows a DRAM according to another embodiment of the invention.
FIG. FIG. 5 is a sectional view showing a conventional DRAM. In the figure, 1 is a semiconductor substrate, 3 is a gate insulating film, and 4a
, 4b is a word line, 6a and 6b are high concentration impurity diffusion layers,
7a, 7b and 7C are low concentration impurity diffusion layers, 8 is a charge storage layer, 9 is a dielectric film, 10 is a counter electrode, 11 is an interlayer insulating film, 12 is a bit line, 21 is an insulating film, and 22 is an electrostatic shielding electrode , d indicates the offset dimension. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claim] A semiconductor memory device comprising a plurality of storage areas and an isolation area provided between each storage area and electrically isolating each storage area, comprising: a semiconductor substrate having a main surface; and each storage area. a highly concentrated first impurity diffusion region formed on the main surface of the semiconductor substrate; and a first impurity diffusion region extending from the first impurity diffusion region toward the isolation region;
a second impurity diffusion region having a lower concentration than the first impurity diffusion region; and the first and second impurity diffusion regions formed on the main surface of the semiconductor substrate in the isolation region with an insulating film interposed therebetween. and an element isolation electrode layer arranged so as not to overlap the semiconductor memory device.