JPH10189918A - Nonvolatile semiconductor storage device and its manufacture and charge accumulating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device which hardly generates hot electrons as an MIS transistor structure, does not easily accumulate charges by repeating the judging operation of conduction status, permits a large discriminating current difference to be set and performs charge accumulation at a low voltage in a short time. SOLUTION: A nonvolatile semiconductor storage device is provided with a control gate 16a, which is composed of a second conductive-type diffusion layer formed in a first conductive-type semiconductor substrate, source and drain regions 15a and 15b, which are composed of the second conductive-type diffusion layer isolated from the control gate 16a, a charge injecting layer, which is composed of a second conductive-type diffusion layer 16b, isolated from the control gate 16a and a first conductive-type diffusion layer 17, and a floating gate 14, which is formed on the semiconductor substrate on the upper region of at least the control gate 16a and the charge injection layer through an insulating film and constitutes an MIS transistor with the source and drain regions 15a and 15b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, a method for manufacturing the same, and a charge storage method, and more particularly, to a nonvolatile semiconductor memory device capable of electrically writing data, a method for manufacturing the same, and charge storage. About the method.

[0002]

2. Description of the Related Art A redundant element of a conventional mask ROM has a floating gate formed on a channel region on the surface of a semiconductor substrate via a first insulating film, and a floating gate formed on the floating gate via a second insulating film. It has a laminated structure with the control gate. Therefore, when this semiconductor device is manufactured simultaneously on the same chip as a mask ROM having a single-layer conductor gate structure, the manufacturing process becomes complicated due to the gate having the two-layer structure, and the manufacturing cost increases. There was a problem of causing.

In order to solve the above problem, for example, a single-layer conductor gate type nonvolatile semiconductor device has been proposed in Japanese Patent Application Laid-Open No. 60-260147. That is, as shown in FIGS. 8 and 9, the semiconductor device has the source / drain regions 45a formed on the surface of the semiconductor substrate 41.
45b, channel region 47, floating gate 44 formed on semiconductor substrate 41 via insulating layer 43
And a control gate 46 formed as a diffusion layer on the surface of the semiconductor substrate 41. The floating gate 44 is
It is formed so as to communicate from the channel region 47 of the IS transistor to the element isolation region 12 and the control gate 46.

This semiconductor device has a control gate 4
By applying a voltage to the drain region 45b, it is determined whether or not a channel is formed in the channel region 47 and a conduction state is established between the source region 45a and the drain region 45b when a voltage is applied to the drain region 45b. )can do. Here, when charges (electrons) are accumulated in the floating gate 44, the control gate 4
6, a channel is not formed in the channel region 47 and the MIS transistor is turned off, and if no charge is accumulated in the floating gate 44,
It becomes conductive.

On the other hand, charge accumulation (writing) in the floating gate 44 is performed by applying a higher potential to the control gate 46 and the drain region 45b by applying a higher potential than when determining whether or not there is conduction between the control gate 46 and the drain region 45b. This is realized by injecting into the gate 44.

[0006]

In the above-described nonvolatile semiconductor device, the applied voltage differs between when the conduction state is determined and when the electric charge is stored in the floating gate 44. , A voltage is applied to the drain region 45b of the MIS transistor. Therefore, when a voltage sufficient to determine whether or not the conductive state is applied is applied, a part of hot carriers generated by the repetition is accumulated in the floating gate 44,
There is a structural problem that accumulation occurs in an element where charge is not originally stored.

As described above, under the present circumstances, a non-volatile semiconductor device capable of performing a high-speed operation without generating extra hot carriers generated at the time of discrimination and accumulating charges in the floating gate due to the generation of hot carriers. Has not been realized.

[0008]

According to the present invention, there is provided a control gate comprising a second conductivity type diffusion layer formed in a first conductivity type semiconductor substrate, and a second control gate formed separately from the control gate. A source / drain region formed of a conductive type diffusion layer, a second conductive type diffusion layer formed separately from the control gate, and a first conductive type diffusion layer formed adjacent to the second conductive type diffusion layer. A charge injection layer formed on the semiconductor substrate and at least above the control gate and the charge injection layer via a thin film insulating film, and
A nonvolatile semiconductor memory device having a floating gate forming an S transistor is provided.

Further, according to the present invention, in the above-mentioned method for manufacturing a nonvolatile semiconductor memory device having a mask ROM on the same substrate, the control gate of the nonvolatile semiconductor memory device is formed by forming a bit line of the mask ROM. A method for manufacturing a nonvolatile semiconductor memory device formed by the same process is provided. Further, according to the present invention, a part of the source region is formed below the floating gate via the thin film insulating film, and the charge injection layer is shared with the source region, and the mask ROM is provided on the same substrate. In the method for manufacturing a nonvolatile semiconductor memory device, a charge injection layer shared with a control gate and a source region of the nonvolatile semiconductor memory device is formed by the same process as forming a bit line of a mask ROM. A manufacturing method is provided.

The connection withstand voltage between the second conductivity type diffusion layer forming the charge injection layer and the semiconductor substrate is lower than the junction withstand voltage between the drain region or control gate and the semiconductor substrate,
In the above-described method for manufacturing a nonvolatile semiconductor memory device having a mask ROM on the same substrate, the first conductivity type diffusion layer constituting the charge injection layer of the nonvolatile semiconductor device is formed by the same process as that for program writing of masking chrome. A method for manufacturing a nonvolatile semiconductor memory device is provided.

Further, according to the present invention, a voltage having an absolute value higher than the connection withstand voltage between the charge injection layer and the semiconductor substrate is applied to the second conductivity type diffusion layer of the charge injection layer in the semiconductor memory device, and By applying a voltage having an absolute value higher than the voltage to the gate, a method for accumulating charges in the floating gate is provided.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device according to the present invention comprises a control gate mainly formed as a diffusion layer in a semiconductor substrate, a charge injection layer formed as a diffusion layer separately from the control gate. The MIS transistor includes a source / drain region and a floating gate, and the floating gate is formed between the control gate, the charge injection layer, and the source / drain region.

As a semiconductor substrate used in the nonvolatile semiconductor memory device of the present invention, a silicon substrate, a semiconductor compound substrate such as GaAs, etc. which can be generally used as a substrate can be used. This semiconductor substrate is required to have either the N-type or the P-type as the first conductivity type, but the entire semiconductor substrate does not necessarily need to be of any conductivity type, and is formed on this semiconductor substrate. Depending on the type of the circuit or the like, it is only necessary that at least one impurity layer (well) partially showing N-type or P-type is provided. In this case, the impurity concentration of the semiconductor substrate or the impurity layer is not particularly limited, and can be appropriately adjusted depending on the application. Further, the nonvolatile semiconductor memory device of the present invention
For example, it may be a semiconductor substrate provided with other devices such as a memory cell such as a mask ROM and its peripheral circuits.

The control gate in the nonvolatile semiconductor memory device is formed in the semiconductor substrate as an impurity diffusion layer of a conductivity type opposite to that of the substrate. The control gate is electrically separated from a source / drain region of a MIS transistor described later by an element isolation film. The impurity concentration, size, shape, arrangement position, and the like of the control gate can be appropriately adjusted according to the applied voltage, the device size, and the like as long as the control gate can function as a normal nonvolatile semiconductor transistor. Is 10
^{About 18} to 10 ²¹ cm ^-3 . Note that the impurity concentration of the control gate is preferably formed to be substantially the same as the impurity concentration of the second conductivity type diffusion layer of the charge injection layer to be described later. It may be formed with an impurity concentration different from that of a layer or a source / drain region described later.

In the charge injection layer, a second conductivity type diffusion layer and a first conductivity type diffusion layer are formed adjacent to each other in a semiconductor substrate. The charge injection layer may be at least electrically separated from the control gate. Further, it may be electrically separated from a source / drain region of a MIS transistor to be described later, or may share all or a part of any one of the source / drain regions. However,
If the device is shared with the drain region, there is a possibility that unintended charge injection into the floating gate may occur during the operation of the device. Therefore, the device is preferably shared with the source region. The second conductivity type diffusion layer in the charge injection layer is:
It is preferable to have an impurity concentration capable of effectively accumulating charges in the floating gate by a voltage applied to the charge injection layer, and the first conductivity type diffusion layer is provided with a control gate or a source / drain region to be described later. It is preferable to have an impurity concentration such that the connection withstand voltage between the charge injection layer and the semiconductor substrate is lower than the junction withstand voltage with the semiconductor substrate. Specifically, the second conductivity type diffusion layer has an impurity concentration of about 10 ¹⁸ to 10 ²¹ cm ⁻³ , and the first conductivity type diffusion layer has an impurity concentration of about 10 ¹⁷ to 10 ¹⁹ cm ⁻³ . When the impurity concentration of the second conductivity type diffusion layer is not shared with the source region, the impurity concentration is within the above-described range.
It may be formed with an impurity concentration different from that of the source region.

The charge injection layer is formed by using a mask having an opening in a region where the first and second conductivity type diffusion layers are formed.
This can be performed by ion implantation of the first and second conductivity types. In this case, the two masks may be arranged such that the diffusion layers are adjacent to each other when the diffusion layers are formed, and even if a mask in which the formed diffusion layers overlap is used, the first conductivity type impurity may be used. Since the concentration is lower than the second-conductivity-type impurity concentration, the second-conductivity-type diffusion layer does not reverse to the opposite-conductivity type, and there is substantially no problem.

The MIS transistor has a source / drain region and a floating gate. The source / drain region is at least electrically isolated from the control gate and has a second conductivity type impurity concentration of, for example, about 10 ¹⁹ to 10 ²¹ cm ⁻³ . Source /
The drain region may have an LDD structure, for example, a DDD structure utilizing a difference in diffusion rate between phosphorus and arsenic, or a structure having a low concentration region by oblique ion implantation. You may.

The floating gate has these sources /
It is located between the drain regions and on the substrate with a thin insulating film interposed therebetween. The thin-film insulating film can be formed with an insulating material such as SiN, SiO _2, or a laminated film of these, with a thickness of about 6 to 20 nm. The floating gate is not particularly limited as long as it is a conductive material usually used as an electrode material. For example, polysilicon containing impurities, high melting point metal such as Ti, Ta, silicide or polycide with these high melting point metals, aluminum, platinum, and the like, among which N-type impurities 10 ^19-10
Polysilicon contained at about ²¹ cm ^-3 is preferred. The floating gate is also disposed on the control gate and the charge injection layer described above, and is further disposed on both the second and first diffusion layers that constitute the charge injection layer.

In the nonvolatile semiconductor memory device of the present invention, the positional relationship between the control gate, the source / drain regions constituting the MIS transistor, and the charge injection layer is as described above.
The shape of the source / drain region, the charge injection layer or the floating gate constituting the S transistor, or the relationship with other elements and circuits to be provided, etc.
It can be configured to function as a nonvolatile semiconductor memory device. For example, as described in the embodiment, the modification of the sharing relationship between the source region and the charge injection layer (see FIG. 7), the adoption of a two-layer gate structure, and the like are further included.

With such a structure, a method of accumulating (writing) charges in the floating gate can be realized by a method different from a method of determining (reading) the conduction state. That is, in contrast to the conventional method in which charge is accumulated by capturing hot carriers generated in the conductive state of the MIS transistor by the floating gate, in the present invention, the breakdown voltage is increased by the first impurity diffusion layer. This can be achieved by capturing electrons generated by applying a reverse voltage to the PN junction in the charge injection layer in which is reduced. Specifically, a voltage having a slightly higher absolute value than the withstand voltage of the PN junction is applied to the PN junction portion of the charge injection layer having a low withstand voltage and directly below the floating gate, and an absolute value higher than this voltage is applied to the control gate. By applying a high voltage, a part of hot carriers generated at the PN junction can be captured by the floating gate. The voltage applied to the charge injection layer and the control gate is not particularly limited as long as the above relationship is satisfied. The first and second impurity concentrations of the charge injection layer, the impurity concentration of the control gate, the size of the device, The thickness can be adjusted as appropriate depending on the thickness of the thin insulating film or the thickness of the floating gate. Specifically, about 3 to 8 V is applied to the charge injection layer, and 4 to 8 V is applied to the control gate.
Applying a voltage of about 15 V is an example.

The determination of the conduction state (reading) is performed by applying a potential lower than that at the time of charge accumulation to the control gate and causing a potential difference between the source / drain regions of the MIS transistor. This is realized by sensing the current flowing between them. That is,
When a voltage is applied to the control gate and no charge is accumulated in the floating gate, the potential of the gate (floating gate) of the MIS transistor increases due to capacitive coupling of the voltage applied to the control gate, and the channel of the MIS transistor increases. Becomes conductive.
On the other hand, when charges are stored in the floating gate, the rise in the potential of the gate of the MIS transistor is suppressed due to the stored charges, and the channel of the MIS transistor is cut off. The applied voltage at this time can also be appropriately adjusted as described above.
V, 1-5V for drain region, 3 for control gate
-8 V is applied.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, for example, a mask ROM is formed on the same semiconductor substrate.
In the case of having a control gate, the first of the charge injection layer
The bit line of the mask ROM can be formed in the same step as the formation of any or all of the conductivity type diffusion layer and the source / drain regions. Further, the program writing of the mask ROM can be performed in the same step as the formation of the second conductivity type diffusion layer of the charge injection layer. Further, even in the case of having an element other than the mask ROM, the control gate of the nonvolatile memory device of the present invention, the first conductivity type diffusion layer of the charge injection layer,
Forming any or all of the source / drain regions
This can be achieved by the same steps as those for forming other elements.

Hereinafter, a nonvolatile semiconductor memory device according to the present invention will be described.
An embodiment of the manufacturing method and the charge storage method will be described with reference to the drawings. Embodiment 1 As shown in the plan view of FIG. 1 and the cross-sectional view of FIG. 2, a nonvolatile semiconductor device according to the present invention is provided in a P-type region 18 of a silicon substrate 11 having an element isolation insulating film 12 made of silicon oxide. The control gate 16a, which is an N-type impurity diffusion layer formed, the source / drain regions 15a and 15b, which are N-type impurity diffusion layers separated by the control gate 16a and the element isolation region 12, the control gate 16a and the element isolation N-type impurity diffusion layer 16b separated by region 12 and P-type impurity diffusion layer 17 adjacent to N-type impurity diffusion layer 16b and formed for lowering the junction breakdown voltage between N-type impurity diffusion layer 16b and the substrate And a polycrystalline polysilicon containing an N-type impurity on the silicon substrate 1 with a thin film insulating film 13 interposed therebetween. And the floating gate 14 formed. The floating gate 14 extends from the N-type impurity diffusion layer 16b and the P-type impurity diffusion layer 17 constituting the charge injection layer to the element isolation region 12 and the control gate 16a.
The source / drain regions 15a, 15b are disposed over the channel region 15 disposed between the source / drain regions 15a, 15b.
b and the MIS transistor T together with the channel region 15
Is composed.

A method for manufacturing a nonvolatile semiconductor device having such a configuration will be described. In the following manufacturing method, a method of manufacturing memory cells of a NOR type mask ROM on the same substrate will be described. First, as shown in FIG. 3A, the memory cell area (MC) of the mask ROM, the P-channel area of the peripheral circuit section (PC) and the P-channel area of the peripheral circuit section (PC) are formed on the surface of the silicon substrate 11 by a known method. A P-type well 18 is formed in the nonvolatile semiconductor memory (NVM). This nonvolatile semiconductor device also has a peripheral circuit N-channel region (not shown), but is omitted in the following description.

Further, element isolation is performed on the silicon substrate 11.
After forming the edge film 12, by a known lithography method,
Forming a photoresist 22 having an opening in a desired area
Then, an N-type impurity, for example, arsenic is
Energy, 1-5 × 10^Fifteencm ^-2Dosing with a dose of
Bit line 20 in the disk ROM memory cell,
N-type impurities forming the gate 16a and the charge injection layer
The diffusion layer 16b is formed.

As shown in FIG. 3B, a gate insulating film 13 is formed by a known method, polycrystalline silicon containing an N-type impurity is subsequently deposited, and a known lithography method and an etching method are used. Thereby, the word line 20, the gate electrode 19 of the MIS transistor of the peripheral circuit, and the floating gate 14 in the mask ROM memory cell are formed. Next, a photoresist 23 having an opening in a desired region is formed in the peripheral circuit portion and the nonvolatile storage portion, and phosphorus is implanted by using the photoresist 23 as a mask,
An N ^- region 21 is formed.

As shown in FIG. 3C, the word line 2
0, a gate electrode 19 and a floating gate 14, sidewalls are formed, and As is implanted by using a photoresist 25 having an opening in a desired region as a mask, so that the source / drain region 24 and the nonvolatile The source / drain regions 15a and 15b (not shown) of the MIS transistor are formed in the memory unit.

Thereafter, as shown in FIG. 3D, a photoresist 26 having an opening in a desired region is formed, and using this photoresist 26 as a mask, 120-120.
250 keV implantation energy, 1-5 × 10 ¹⁴ cm ⁻²
The data 26 is written into the memory cells of the mask ROM by implanting boron at a dose of. Simultaneously with the injection at this time, the N-type impurity diffusion layer 1 directly under the floating gate 14 of the nonvolatile memory portion and constituting the charge injection layer is formed.
A P-type impurity diffusion layer 17 is formed in a region partially overlapping 6b, and a charge injection layer is formed.

Thereafter, an interlayer insulating film, a contact hole for wiring, a metal wiring, and the like are formed by a known method to complete a nonvolatile semiconductor memory device. Although omitted in the above description of the manufacturing method, annealing is appropriately performed after impurity implantation and etching. An operation method of the nonvolatile semiconductor device will be described below. The charge is stored (written) in the floating gate 14 by, for example, 8
V, 5 V is applied to the charge injection layer. At this time, the substrate is kept at the ground potential, and the source / drain regions 15a and 15b of the MIS transistor are kept open. That is, the voltage applied to the charge injection layer is
At least the voltage at which a leak current occurs at the PN junction whose junction breakdown voltage has been reduced by the formation of the P-type impurity layer 17 is set.

FIG. 6 shows PN in the charge injection layer measured by a test device manufactured by the same process as the above method.
Junction (N-type impurity diffusion layer 16b and P-type impurity diffusion layer 1
7) shows the reverse breakdown voltage characteristic. In FIG. 6, the case where the impurity implantation amount of the N-type impurity diffusion layer 16b is 2 × 10 ¹⁴ / cm ² is indicated by a solid line, and the case where the impurity implantation amount is 4 × 10 ¹⁴ cm ² is indicated by a broken line. The withstand voltage changes softly (smoothly) and has better controllability than general avalanche breakdown characteristics. That is, when the applied voltage is changed, hot electron injection can be performed with good controllability in accordance with the change.

With the structure of such a nonvolatile semiconductor device, the time required for charge storage can be reduced to 10 ms or less, which is about 1/10 of the conventional case, and charge storage can be realized at a low voltage. On the other hand, the determination (reading) of the conduction state is performed, for example, by setting 5V to the control gate 16a, and to 2 .V.
5 V is applied, and the source region 15a is grounded. The source / drain region 15 of the MIS transistor in this state
This is realized by detecting the current between a and 15b.
According to the above-described operation, the accumulation of electric charge is unlikely to occur due to the repetition of the operation of determining the conduction state, and the difference between the determination currents can be set large.

Example 2 This nonvolatile semiconductor device was formed in a P-type region 18 of a silicon substrate 11 having an element isolation insulating film 12, as shown in the plan view of FIG. A control gate 16a which is an N-type impurity diffusion layer, and a source / drain region 15 which is an N-type impurity diffusion layer separated by the control gate 16a and the element isolation region 12.
a and 15b, a charge injection layer comprising an N-type impurity diffusion layer 16b shared with the source region 15a and a P-type impurity diffusion layer 17 overlapping a part of the source region 15a, and a thin film insulating film 13 on the silicon substrate 1. And a floating gate 14 formed of polycrystalline polysilicon containing an N-type impurity. The floating gate 14 is an N-type impurity diffusion layer 1 forming a charge injection layer.
6b and the element isolation region 12 from above the P-type impurity diffusion layer 17.
And the control gate 16a and the source / drain regions 15a and 15b.
An S transistor T is configured.

This nonvolatile semiconductor device can be manufactured by the same method as in the first embodiment, and can be operated in the same manner as in the first embodiment.

[0034]

According to the present invention, it is possible to select an LDD structure or the like which does not easily generate hot electrons as the structure of the MIS transistor. The difference between the discrimination currents can be set large, and the charge can be efficiently stored at a low voltage in a short time.

That is, according to the present invention, in order to prevent generation of hot electrons at the time of judging the conduction state, at least a high voltage of the storage operation and a long time of hot electron injection, which are problems when the drain region has the LDD structure at least. Can be avoided, and the difference in the determination current or the complexity of the determination circuit due to the suppression of the applied voltage for preventing the generation of hot electrons at the time of the determination of the conduction state can be avoided. It is possible to realize a high single-layer conductor gate type nonvolatile semiconductor memory device.

According to the manufacturing method of the present invention, the number of manufacturing steps can be reduced, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is a schematic cross-sectional view of a main part showing a manufacturing step of the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a schematic plan view showing another nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a sectional view taken along line BB ′ of FIG. 4;

FIG. 6 is a diagram showing a reverse breakdown voltage characteristic in a charge injection layer of the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a schematic plan view showing still another nonvolatile semiconductor memory device of the present invention.

FIG. 8 is a schematic plan view showing a conventional nonvolatile semiconductor memory device.

FIG. 9 is a sectional view taken along line CC ′ of FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Silicon substrate (semiconductor substrate) 12 Element isolation insulating film 13 Thin film insulating film 14 Floating gate 15 Channel region 15a Source region 15b Drain region 16a Control gate 16b Second impurity diffusion layer 17 First impurity diffusion layer 18 P-type region 19 Gate electrode Reference Signs List 20 Bit line of mask ROM 21 N ^- region 22, 23, 25, 26 Photoresist 24 Source / drain region of peripheral circuit section

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 29/788 29/792

Claims (7)

[Claims] 1. A control gate comprising a second conductivity type diffusion layer formed in a first conductivity type semiconductor substrate, and a source / drain region comprising a second conductivity type diffusion layer formed separately from the control gate. A charge injection layer including a second conductivity type diffusion layer formed separately from the control gate and a first conductivity type diffusion layer formed adjacent to the second conductivity type diffusion layer; And formed at least above the control gate and the charge injection layer with a thin film insulating film interposed therebetween and together with the source / drain regions.
A nonvolatile semiconductor memory device comprising: a floating gate forming an IS transistor. 2. The non-volatile semiconductor memory device according to claim 1, wherein a part of the source region is formed below the floating gate via the thin-film insulating film, and the charge injection layer is shared with the source region. 3. The semiconductor device according to claim 1, wherein a withstand voltage between the second conductivity type diffusion layer forming the charge injection layer and the semiconductor substrate is lower than a junction withstand voltage between the drain region or the control gate and the semiconductor substrate. Nonvolatile semiconductor memory device. 4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein a mask ROM is provided on the same substrate.
A method for manufacturing a nonvolatile semiconductor memory device, wherein the method is performed by the same process as that for forming a bit line of a mask ROM. 5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, further comprising a mask ROM on the same substrate, wherein the charge injection layer shared with a control gate and a source region of the nonvolatile semiconductor memory device is masked. A method for manufacturing a nonvolatile semiconductor memory device, wherein the method is formed by the same process as that for forming a bit line of a ROM. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein a mask ROM is provided on the same substrate, wherein the first conductivity type diffusion layer constituting a charge injection layer of the nonvolatile semiconductor device is formed of A method for manufacturing a nonvolatile semiconductor memory device, wherein the method is formed by the same step as program writing. 7. A voltage having an absolute value higher than a connection withstand voltage between the charge injection layer and the semiconductor substrate is applied to the second conductivity type diffusion layer of the charge injection layer in the semiconductor memory device according to claim 1 or 2; And a method of accumulating charges in the floating gate by applying a voltage having an absolute value higher than the voltage to the control gate.