JPH03116930A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the coverage between a wiring layer and insulating films by a method wherein a layer to be etched is once isotropically etched and then further anisotropically etched in the vertical direction so as to form patterns having taper shaped sides on the upper part of the layer to be etched. CONSTITUTION:A layer 3 to be etched is isopropically etched meeting the low vacuumizing requirement to the extent of not sputtering an intermediate layer 5 using the layer 5 and a lower resist layer 4a as masks. Successively, the layer 3 is anisotropically etched in the vertical direction meeting the high vacuumizing requirement to the extent of sputtering the intermediate layer 5 so as to form patterns having taper shaped sides on the upper part of the layer 3. Through these procedures, the coverage of the patterned wiring layer and the insulating films formed on the wiring layer can be enhanced as well as the flatness of the insulating films formed on the wiring layer can also be enhanced.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device that can improve the coverage between a patterned wiring layer and an insulating film formed on the wiring layer, and that Aiming at providing a method for manufacturing a semiconductor device that can improve film planarization, the steps include sequentially forming a lower resist layer 4a, an intermediate layer 5, and an upper resist layer 4b on the layer to be etched 3; patterning the upper resist layer 4b, and using this as a mask, patterning the intermediate layer 5 and the lower resist N4a;
Using the intermediate layer 5 and the lower resist layer 4a as masks, the layer to be etched 3 is etched under low vacuum conditions such that the intermediate layer 5 is not sputtered to perform isotropic etching.)
Subsequently, the layer 3 to be etched is etched under high vacuum conditions such that the intermediate layer 5 is sputtered to perform anisotropic etching in the vertical direction, and a pattern with tapered side surfaces is formed on the upper part of the layer 3 to be etched. and a step of forming.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and can be applied to a method of etching a metal wiring layer, and is particularly applicable to improving the coverage between a patterned wiring layer and an insulating film formed on the wiring layer. The present invention relates to a method for manufacturing a semiconductor device that can perform the following steps.

Conventionally, since the metal wiring layer was thin, even a single layer resist had a sufficient etching selectivity with respect to the metal wiring layer, and the metal wiring layer could be sufficiently etched. Note that in order to carry out anisotropic etching, the pressure is usually set at, for example, 0.
The test was carried out under high vacuum conditions of 0 I Torr. The reason why this was carried out under high vacuum conditions is that under high vacuum conditions, the ashing rate of the resist increases, reaction products tend to adhere to the side walls of the pattern, and anisotropy increases. Pressure is 0.1 Torr
The following low vacuum conditions make it difficult for reaction products to adhere to the side walls of the pattern.

However, in recent years, there has been a demand for thicker and finer metal wiring layers made of Af or the like, especially in order to increase current capacity. As the metal wiring layer becomes thicker, there is a limit to the etching selectivity of a single layer resist, so the resist must be made thicker. However, there is a limit to how thick a single layer resist can be made, and it is usually difficult to make a rough pattern.
It was only possible to resolve objects with a thickness of approximately μm. Moreover, as miniaturization is required, the resolution must be further increased.

As a means to solve such problems, there is a technology that can etch thick metal wiring layers by forming a multilayer resist, such as two or three layers, and resolving the resist step by step. .

[Conventional technology]

A conventional technique for etching a thick metal wiring layer using a multilayer resist will be described below. Note that here, the multilayer resist has a structure of resist layer/resin layer/resist layer.

FIGS. 2(a) to 2(c) are diagrams illustrating a conventional method of manufacturing a semiconductor device.

In this figure, 31 is a substrate made of Si, for example, and 32
33 is a wiring layer made of, for example, Af (AfSi or the like may be used), 34a and 34b are resist layers, 35 is a resin layer made of, for example, spin-on glass (SOG), 36a , 36
b, 36c, and 36d are openings, and 37 is an insulating film made of, for example, Sin.

Next, the manufacturing method will be explained.

First, as shown in FIG. 2(a), on a substrate 31, an insulating film 32 having a thickness of, for example, 4000 to 5000, a wiring layer 33 having a thickness of, for example, 3 μm, and a wiring layer 33 having a thickness of, for example, 2.5 to 4 μm. After sequentially forming a resist layer 34a, a resin layer 35 having a thickness of, for example, 2,500 to 3,500 people, and a resist layer 34b having a thickness of, for example, 5,000 people, the resist layer 34b is patterned to form an opening 36a, and the opening 36a is formed by patterning the resist layer 34b. 36
The resin layer 35 is exposed within a.

Next, as shown in FIG. 2(b), the resin layer 35 in the opening 36a is anisotropically etched using the resist layer 34b as a mask to form the opening 36b, and the opening 3
After exposing the resist layer 34a in 6b, the resist layer 34b is removed. Next, using the resin layer 35 as a mask, the resist JI 34a within the opening 36b is patterned to form an opening 36c, and the wiring layer 33 is exposed within the opening 36c.

Then, the resin layer 35 and the resist layer 34 are etched by anisotropic etching under high vacuum conditions at a pressure of, for example, 0.01 TorrO.
After selectively etching the wiring layer 33 using a as a mask to form an opening 36d and exposing the insulating film 32 within the opening 36d, the wiring layer 33 is etched by, for example, a CVD method.
SiO□ is deposited so as to cover 33, and the film thickness is, for example, 1 μm.
By forming the insulating film 37, a structure as shown in FIG. 2(C) can be obtained.

[Problem to be solved by the invention]

In the above-described conventional method for manufacturing a semiconductor device, first, a multilayer resist consisting of a resist layer 34a, a resin layer 35, and a resist layer 3b is used, and the wiring layer 33 is anisotropically etched under high vacuum conditions. The side surfaces thereof formed a vertical opening 36d. However, when the wiring layer 33 becomes thicker and the height difference becomes more severe, there is a problem that the coverage between the wiring layer 33 and the insulating film 37 formed on the wiring layer 33 deteriorates. The problem was that it got worse. Wiring layer 3
Regarding the coverage of 3 and the dead film 37, especially the side surface (shoulder part) of the upper part of the wiring layer 33, as shown in part 1A1 in FIG.
Therefore, the insulating film 37 was easily formed to be thin, resulting in a coverage of m. In addition, the flatness of the insulating film 37 is 81 degrees as shown in LF FIG. was.

Note that the resist layer 34a, the resin layer 35, and the resist layer 3
It is known that if the wiring Ji 33 is isotropically etched with the low vacuum strip 1 using a multilayer resist made of 4b, the wiring layer 33 will become thinner, which is not preferable. This thinning can be solved by removing the resin 1i35, but if the wiring layer 33 becomes thicker and the steps become even more severe, the above-mentioned anisotropic etching may Similarly, the problem of coverage between the wiring layer 33 and the insulating film 37 and the problem of flatness of the insulating film 37 cannot be solved.

Therefore, the present invention provides a semiconductor that can improve the coverage between a patterned wiring layer and an insulating film formed on the wiring layer, and can improve the planarization of the insulating film formed on the wiring layer. The purpose is to provide a method for manufacturing the device.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a step of sequentially forming a lower resist layer 4a, an intermediate layer 5, and an upper resist layer 4b on the layer to be etched 3, and patterning the upper resist layer 4b. , patterning the intermediate layer 5 and the lower resist layer 4a using this as a mask, and patterning the layer to be etched under low vacuum conditions to the extent that the intermediate layer 5 is not sputtered using the intermediate layer 5 and the lower resist iJ4a as a mask. 3 to perform isotropic etching, and then the layer 3 to be etched is etched under high vacuum conditions such that the intermediate layer 5 is sputtered to perform anisotropic etching in the vertical direction. This process includes a step of forming a pattern having tapered side surfaces on the upper part of N3.

[Function] The present invention provides a lower resist layer 4a on the etching target N3,
The intermediate layer 5 and the upper resist layer 4b are sequentially formed, the upper resist layer 4b is patterned, the intermediate layer 5 and the lower resist layer 4a are patterned using this as a mask, and the intermediate layer 5 and the lower resist layer 4a are used as a mask. The layer 3 to be etched is etched under low vacuum conditions such that the intermediate layer 5 is not sputtered to perform isotropic etching, and then the layer 3 to be etched is etched under high vacuum conditions such that the intermediate layer 5 is not sputtered. Anisotropic etching is performed in the vertical direction, and a pattern having tapered side surfaces is formed on the etched surface N3.

Therefore, it is possible to improve the coverage between the patterned wiring layer and the insulating film formed on the wiring layer, and it is also possible to improve the planarization of the insulating film formed on the wiring layer. become. Details will be explained in Examples.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings. Here again, the case of etching a thick metal wiring layer using a multilayer resist will be described. The multilayer resist has a structure of resist layer/resin layer/resist layer.

FIGS. 1(a) to 1(c) are diagrams illustrating a manufacturing method of an embodiment of a semiconductor device manufacturing method according to the present invention.

In this figure, 1 is a substrate made of, for example, Si, 2 is an insulating film made of, for example, SiOz (PSO or the like may be used), and 3 is, for example, A/! (Also may be A/!Si, etc.), and corresponds to the layer to be etched according to the present invention. 4a and 4b are resist layers, the resist layer 4a corresponds to the lower resist layer according to the present invention, and the resist Ji4b corresponds to the upper resist layer according to the present invention. Reference numeral 5 denotes a resin layer made of, for example, spin-on glass (SOG), which corresponds to the intermediate layer according to the present invention. 6a, 6b, 6c are openings,
The opening 6a is an opening formed in the resist layer 4b, the opening 6b is an opening formed in the resin layer 5, and the opening 6c is an opening formed in the resist layer 4a.

7 is a groove formed in the wiring N3, and 8 is an opening formed in the wiring layer 3, which has a tapered portion 9 on its upper side surface (shoulder portion). 10 is an insulating film made of, for example, Sin.

Next, the manufacturing method will be explained.

First, as shown in FIG.
After sequentially forming a wiring N3 of 2.5 to 4 .mu.m in thickness, a resist layer 4a with a thickness of 2.5 to 4 .mu.m, a resin layer 5 with a thickness of 2500 to 3500 .mu.m, and a resist layer 4b of 5000 .mu.m in thickness, the resist layer 4b is patterned to form an opening 6a, and the resin layer 5 is exposed within the opening 6a.

Next, as shown in FIG. 1(b), the resin layer 5 within the opening 6a is anisotropically etched using the resist layer 4b as a mask to form an opening 6b, and the resist layer 5 is etched within the opening 6b. After exposing resist layer 4a, resist layer 4b is removed. Next, using the resin layer 5 as a mask, the resist Jff14a within the opening 6b is patterned to form an opening 6C, and the wiring layer 3 is exposed within the opening 6C.

Next, as shown in FIG. 1(C), the pressure is, for example, 0.1
The etching gas is e.g. B at a low vacuum of ~0.2 Torr.
(1. By isotropic etching with a mixed gas of gas, 5iCj24 gas, and Cρ2 gas, the wiring layer 3 in the openings 6b and 6c is etched using the resin layer 5 and resist layer 4a as a mask.
A groove 7 is formed in the upper part of the wiring layer 3 by selectively etching. Specifically, the groove 7 here is formed by side etching by isotropic etching, and has a width X2 larger than the width X1 of the opening 60.

Next, in the same chamber where the above-mentioned isotropic etching was performed, the pressure inside the chamber is set to 0.01 to 0.05 To, for example.
rr high vacuum, and the etching gas is, for example, BCf, gas, 5iCj2. A mixed gas of gas and C12 gas (Si
Using the resin layer 5 and resist N4a as masks, the openings 6b, 6c and grooves 7 are etched by anisotropic etching using a mixed gas of Cffi4 gas and C2□ gas, etc.).
The wiring layer 3 is further selectively etched through the wafer to form an opening 8 and the insulating film 2 is exposed within the opening 8.

Specifically, the opening 8 here is formed by etching in the vertical direction by anisotropic etching.
It is formed to have a width X3 that is the same as the zero width X, and further a tapered portion 9 is formed on the upper side surface (shoulder portion) of the wiring layer 3.

As described above, the reason why the process is switched from isotropic etching to anisotropic etching by simply changing the vacuum conditions using the resin layer 5 and resist layer 4a as a mask is as follows.

In the etching process shown in FIG. 1(C), the pressure is 0.
Since the vacuum is as low as 1 to 0.2 Torr, the resin layer 5 is not sputtered by the etching gas, and the accompanying scatterings do not adhere to the wiring layer 5.

For this reason, it is difficult for scattered objects (deposits) to form on the wiring layer 5, and the etching progresses isotropically.

Next, in the etching process shown in FIG. 1(d), since the pressure is a high vacuum of 0.01 to 0.05 Torr, the resin layer 5 is sputtered by the etching gas, and the scattered materials are scattered on the side surface of the wiring layer 5. Since the deposited material suppresses the progress of etching in the lateral direction, etching progresses anisotropically. In addition, under high vacuum conditions, the velocity of particles is also fast, so
More particles perpendicularly enter the wiring layer 5, and this also causes anisotropic etching. In other words, since the resin layer 5 is present, it is possible to appropriately select between isotropic etching and anisotropic etching as described above.

Next, by removing the resist N4a with an organic solvent, the resin layer 5 is also removed at the same time. Then, by depositing 5i02 to cover the wiring layer 3 by, for example, the CVD method to form an insulating film 10 having a thickness of, for example, 1 μm, the first
A structure as shown in Figure (e) can be obtained.

That is, in the above embodiment, the resin layer 5 and the resist JW
4a as a mask, the wiring N3 is isotropically etched to form a trench 7 on the upper part of the wiring layer 3, and then the wiring layer 3 is anisotropically etched to form the wiring layer 3, as shown in FIG. 1(d). A vertical opening 8 having a tapered portion 9 can be formed on the side surface of the upper portion of the opening 8 . Therefore, since the side surface of the upper part of the wiring layer 3 has a tapered part 9, it is possible to improve the coverage between the wiring layer 3 and the insulating film 10 on the side surface of the upper part of the wiring layer 3, which has been a problem in the past. . Moreover, the insulating film 10 formed on the wiring layer 3 can be planarized well. Here, the coverage between the wiring layer 3 and the insulating film is made good. Specifically, this is possible because the tapered portion 9 is formed on the side surface of the upper part of the wiring layer 3, as shown in FIG. 1(e).
As shown in part A2 shown in FIG.
This is because the thickness of the wiring layer 3 can be formed.Furthermore, the planarization of the insulating film 10 can be improved because the wiring layer 3
Since the tapered part 9 is formed on the side surface of the upper part, the shape shown in FIG. 1(e)
This is because the insulating film can be formed thickly on the side surface of the upper part of the wiring layer 3, as shown in B2 shown in FIG.

〔Effect of the invention〕

According to the present invention, it is possible to improve the coverage between the patterned wiring layer and the insulating film formed on the wiring layer, and to improve the planarization of the insulating film formed on the wiring layer. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating an embodiment of a semiconductor device manufacturing method according to the present invention, and FIG. 2 is a diagram illustrating a conventional manufacturing method. 1...Substrate, 2...Insulating film, 3...Wiring layer, 4a, 4b...Resist layer, 5...Resin layer , 6a, 6b, 6C... opening, 7...
Groove, 8...opening, 9...tapered portion, 10...insulating film. 6a: Opening Figure 1 for explaining the manufacturing method of one embodiment. Figure 1 for explaining the manufacturing method for one embodiment. Figure 1 for explaining the manufacturing method for the embodiment. Figure 2 Diagram explaining the conventional manufacturing method Figure 2

Claims (1)

[Claims] A lower resist layer (4a) on the layer to be etched (3),
A step of sequentially forming an intermediate layer (5) and an upper resist layer (4b), and a step of patterning the upper resist layer (4b), and using this as a mask, patterning an intermediate layer (5) and a lower resist layer (4a). Then, using the intermediate layer (5) and the lower resist layer (4a) as masks, the layer to be etched (3) is etched under low vacuum conditions such that the intermediate layer (5) is not sputtered to perform isotropic etching. Next, the layer to be etched (3) is etched under high vacuum conditions such that the intermediate layer (5) is sputtered to perform anisotropic etching in the vertical direction. 1. A method of manufacturing a semiconductor device, comprising: forming a pattern with tapered side surfaces.