KR100277858B1 - Gap Filling Method for Semiconductor Devices - Google Patents
Gap Filling Method for Semiconductor Devices Download PDFInfo
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- KR100277858B1 KR100277858B1 KR1019980044020A KR19980044020A KR100277858B1 KR 100277858 B1 KR100277858 B1 KR 100277858B1 KR 1019980044020 A KR1019980044020 A KR 1019980044020A KR 19980044020 A KR19980044020 A KR 19980044020A KR 100277858 B1 KR100277858 B1 KR 100277858B1
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 238000004544 sputter deposition Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- 229910052814 silicon oxide Inorganic materials 0.000 description 21
- 239000010410 layer Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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Abstract
높은 종횡비를 갖는 좁은폭의 갭을 채우기에 알맞은 반도체소자의 갭필링(gap filling)방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 반도체소자의 갭필링방법은 반도체소자에 형성된 갭(gap)에 고밀도 플라즈마 상태의 장비에서 동시에 증착공정과 스퍼터링공정을 진행하여 절연막을 부분 증착하는 단계, 상기 갭 측면 부분의 상기 절연막이 제거되고 상기 갭의 바닥에 제 1 절연막이 남도록 부분식각 공정을 하는 단계, 상기 갭을 채우기 위해 상기 고밀도 플라즈마 장비에서 상기 갭에 절연막을 부분 증착하는 공정과 부분식각하는 공정을 반복하여 진행하는 것을 특징으로 한다.In order to provide a gap filling method of a semiconductor device suitable for filling a narrow gap having a high aspect ratio, a gap filling method of a semiconductor device for achieving the above object is a gap formed in the semiconductor device (gap) Performing partial deposition and sputtering at the same time in a high density plasma apparatus to partially deposit an insulating film, and performing a partial etching process so that the insulating film is removed from the gap side portion and the first insulating film remains at the bottom of the gap. In order to fill the gap, the process of partially depositing and partially etching the insulating film in the gap in the high-density plasma equipment may be repeated.
Description
본 발명은 반도체소자의 콘택홀에 대한 것으로, 특히 높은 종횡비(aspect ratio)를 갖는 좁은폭의 갭을 채우기에 알맞은 반도체소자의 갭필링방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact hole of a semiconductor device, and more particularly, to a gap filling method of a semiconductor device suitable for filling a narrow gap having a high aspect ratio.
첨부 도면을 참조하여 종래 반도체소자의 갭필링(gap filling)방법에 대하여 설명하면 다음과 같다.Hereinafter, a gap filling method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a와 도 1b는 종래 제 1 방법에 의한 갭필링방법을 나타낸 공정단면도이고, 도 2a는 종래 제 2 방법에 의해 증착/스퍼터링의 비가 크게 나타난 경우를 나타낸 단면도이며, 도 2b는 종래 제 2 방법에 의해 증착/스퍼터링의 비가 작게 나타난 경우를 나타낸 단면도이다.1A and 1B are cross-sectional views illustrating a gap filling method according to a first method, and FIG. 2A is a cross-sectional view illustrating a case where a deposition / sputtering ratio is large by a second method, and FIG. 2B is a second method. Is a cross-sectional view showing a case where the deposition / sputtering ratio is small due to.
그리고 도 3은 종래 제 2 방법에 의한 갭필링시 문제점을 나타낸 단면도이다.3 is a cross-sectional view showing a problem in gap filling according to the conventional second method.
먼저 반도체소자의 갭을 채우는 종래 제 1 방법은 도 1a에 도시한 바와 같이 트랜치(갭(Gap))가 형성된 반도체기판(1)의 전면에 증착장비를 이용하여 국부적인 증착법(예;화학기상증착법)으로 실리콘산화막(2)을 증착한다.First, a method of filling a gap of a semiconductor device is a local deposition method (e.g., chemical vapor deposition method) using a deposition apparatus on the front surface of a semiconductor substrate 1 on which a trench (gap) is formed, as shown in FIG. 1A. A silicon oxide film 2 is deposited.
이후에 도 1b에 도시한 바와 같이 상기 증착장비와 다른 장비에서 국부적인 에치백공정(스퍼터링(sputtering)공정)으로 산화막을 식각하여 트랜치(갭) 측벽의 프로파일이 향상된 실리콘산화막(2)을 형성한다.Subsequently, as illustrated in FIG. 1B, the oxide film is etched by a local etch back process (sputtering process) in the deposition apparatus and other equipment to form a silicon oxide film 2 having an improved profile of the trench sidewalls. .
이와 같이 국부적인 증착법과 국부적인 스퍼터링법을 각각 다른장비를 이용하여 반복적으로 진행하므로써 트랜치를 채우는 공정을 한다.As described above, the process of filling the trench is performed by repeatedly performing the local deposition method and the local sputtering method using different equipment.
다음에 갭필링을 위한 종래 제 2 방법은 종래 제 1 방법에서와 같이 국부적인 증착법과 국부적인 스퍼터링법을 각각 다른장비에서 번갈아 가면서 진행하는 것이 아니고 증착공정과 스퍼터링을 같은 장비(고밀도 플라즈마 장비)에서 동시에 진행하는 것이다.Next, the conventional second method for gap filling does not alternately perform the local deposition method and the local sputtering method in different equipment as in the conventional first method, but the deposition process and the sputtering are performed in the same equipment (high density plasma equipment). It is going to be done at the same time.
이와 같은 종래 제 2 방법에 따라 트랜치(갭)를 채우는 공정을 진행하였을 때 도 2a에 도시한 바와 같이 트랜치 측벽에 매우 작은 두께로 산화막이 증착되어 종래 제 1 방법보다 갭필링공정이 더 용이해지거나 도 2b에 도시한 바와 같이 트랜치 측벽에 작은 두께로 산화막이 증착되지가 않고 트랜치 상부 코너 부분만 산화막이 작은 두께로 증착된다. 여기서 도 2a는 증착두께/스퍼터링 두께가 높은 경우이고, 도 2b는 증착두께/ 스퍼터링 두께가 낮은 경우이다.When the process of filling the trench (gap) is performed according to the second conventional method as described above, as shown in FIG. 2A, an oxide film is deposited on the sidewall of the trench at a very small thickness, thereby making the gap filling process easier than the first method. As shown in FIG. 2B, the oxide film is not deposited on the trench sidewalls with a small thickness, but only the oxide upper portion is deposited with a small thickness on the upper corner portion of the trench. 2A illustrates a case where the deposition thickness / sputtering thickness is high, and FIG. 2B illustrates a case where the deposition thickness / sputtering thickness is low.
이와 같이 종래 제 2 방법은 고밀도 플라즈마 장비에서 국부적인 증착법과 국부적인 스퍼터링방법을 트랜치를 채울 때까지 동시에 진행한다.As described above, the conventional second method simultaneously performs the local deposition method and the local sputtering method until the trench fills in the high density plasma apparatus.
그러나 좁은 폭을 갖는 갭(트랜치)을 채우기 위해서 종래 제 2 방법을 이용할 경우에는 도 3에 도시한 바와 같이 트랜치 입구에 스퍼터링된 물질들이 재증착되어서 반대편 측벽과 붙어버리므로써 트랜치 입구 즉, 갭 입구를 막게 되어 보이드(void)가 형성된다.However, when the conventional second method is used to fill the narrow gap, the sputtered materials are redeposited at the trench inlet and stuck to the opposite sidewall as shown in FIG. To prevent voids.
상기와 같은 종래 반도체소자의 갭필링방법은 다음과 같은 문제가 있다.The gap filling method of the conventional semiconductor device as described above has the following problems.
첫째, 일반적으로 다른장비에서 화학기상증착공정과 스퍼터링 공정을 번갈아 가면서 진행하므로써 갭을 채우는 방법은 사이드 스텝 커버리지가 1/종횡비 이상이상이 되는 갭을 필링(filling)하기가 어렵다.First, it is difficult to fill gaps in which side step coverage is greater than 1 / aspect ratio by alternately proceeding chemical vapor deposition and sputtering processes in other equipment.
둘째, 하나의 고밀도 플라즈마 장비를 이용하여 증착과 스퍼터링을 동시에 진행하여 높은 종횡비를 갖는 갭(gap) 및 0.1㎛이하의 갭을 채우는 공정을 하면 갭의 코너(corner)에서 재증착 현상이 발생하므로 보이드(void)가 발생할 수 있다.Second, when the process of filling and filling the gap having a high aspect ratio and the gap of 0.1 μm or less by performing deposition and sputtering at the same time using a single high-density plasma equipment, redeposition occurs at the corner of the gap. void may occur.
셋째, 하나의 고밀도 플라즈마 장비를 이용하여 증착과 스퍼터링을 동시에 진행하여 넓은 사이즈의 갭을 채우는 공정을 하면 갭을 형성한 상부 코너가 클리핑(clipping)되는 현상이 발생된다.Third, when the deposition and sputtering process is performed at the same time using one high-density plasma equipment to fill a gap of a wide size, a phenomenon occurs in which the upper corners in which the gap is formed are clipped.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 높은 종횡비를 갖는 좁은폭의 갭을 채우기에 알맞은 반도체소자의 갭필링(gap filling)방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a gap filling method of a semiconductor device suitable for filling a narrow gap having a high aspect ratio.
도 1a와 도 1b는 종래 제 1 방법에 의한 갭필링방법을 나타낸 공정단면도1A and 1B are cross-sectional views illustrating a gap filling method according to a first method.
도 2a는 종래 제 2 방법에 의해 증착/스퍼터링의 비가 크게 나타난 경우를 나타낸 단면도Figure 2a is a cross-sectional view showing a case where the ratio of deposition / sputtering is large by the conventional second method
도 2b는 종래 제 2 방법에 의해 증착/스퍼터링의 비가 작게 나타난 경우를 나타낸 단면도Figure 2b is a cross-sectional view showing a case where the ratio of deposition / sputtering is small by the conventional second method
도 3은 종래 제 2 방법에 의한 갭필링시 문제점을 나타낸 단면도Figure 3 is a cross-sectional view showing a problem when gap filling by the second conventional method
도 4a 내지 도 4c는 본 발명 반도체소자의 갭필링방법을 나타낸 공정단면도4A through 4C are cross-sectional views illustrating a gap filling method of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
11 : 반도체기판 12 : 제 1 실리콘산화막11 semiconductor substrate 12 first silicon oxide film
13 : 제 2 실리콘산화막 14 : 제 3 실리콘산화막13: 2nd silicon oxide film 14: 3rd silicon oxide film
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 갭필링방법은 반도체소자에 형성된 갭(gap)에 고밀도 플라즈마 상태의 장비에서 동시에 증착공정과 스퍼터링공정을 진행하여 절연막을 부분 증착하는 단계, 상기 갭 측면 부분의 상기 절연막이 제거되고 상기 갭의 바닥에 제 1 절연막이 남도록 부분식각 공정을 하는 단계, 상기 갭을 채우기 위해 상기 고밀도 플라즈마 장비에서 상기 갭에 절연막을 부분 증착하는 공정과 부분식각하는 공정을 반복하여 진행하는 것을 특징으로 한다.In the gap filling method of the semiconductor device of the present invention for achieving the above object, the step of partially depositing an insulating film by performing a deposition process and a sputtering process at the same time in a high-density plasma state in the gap (gap) formed in the semiconductor device, the gap Performing a partial etching process such that the insulating film on the side portion is removed and the first insulating film remains at the bottom of the gap; and partially depositing the insulating film on the gap in the high density plasma equipment to fill the gap. It is characterized by proceeding repeatedly.
첨부 도면을 참조하여 본 발명 반도체소자의 갭필링(gap filling)방법에 대하여 설명하면 다음과 같다.A gap filling method of the semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 4a 내지 도 4c는 본 발명 반도체소자의 갭필링방법을 나타낸 공정단면도이다.4A to 4C are cross-sectional views illustrating a gap filling method of a semiconductor device of the present invention.
본 발명 반도체소자의 갭필링방법은 도 4a에 도시한 바와 같이 트랜치(갭)가 형성된 반도체기판(11)에 고밀도 플라즈마 상태의 한 장비에서 화학기상증착과 스퍼터링을 동시에(in-situ) 진행하여 제 1 실리콘산화막(12)을 증착한다. 이와 같은 공정을 하면 트랜치 측벽에서의 스텝커버리지가 좋지 않기 때문에 트랜치 측벽에 얇은 두께의 제 1 실리콘산화막(12)이 형성된다.According to the gap filling method of the semiconductor device of the present invention, chemical vapor deposition and sputtering are performed simultaneously on a semiconductor substrate 11 having a trench (gap) in a high density plasma state as shown in FIG. 4A. 1 Silicon oxide film 12 is deposited. In this process, since the step coverage of the trench sidewalls is not good, a thin silicon oxide film 12 is formed on the trench sidewalls.
이후에 도 4b에 도시한 바와 같이 습식각(Wet etch)이나 반응성 이온식각으로 제 1 실리콘산화막(12)을 등방성식각하면 트랜치 측벽에 형성된 제 1 실리콘산화막(12)은 거의 제거되고 트랜치 하부에는 제 1 실리콘산화막(12)이 남아 있다. 이에 따라서 차후 실리콘산화막을 증착할 때 종횡비가 처음보다 줄어든다.Subsequently, as shown in FIG. 4B, when the first silicon oxide layer 12 is isotropically etched by wet etching or reactive ion etching, the first silicon oxide layer 12 formed on the sidewalls of the trench is almost removed. 1 silicon oxide film 12 remains. This reduces the aspect ratio than the first time when the silicon oxide film is subsequently deposited.
다음에 고밀도 플라즈마 장비에서 화학기상증착법과 스퍼터링 공정을 동시에(in-situ) 행하여 트랜치(갭)에 제 2 실리콘산화막(13)을 증착한다.Next, a chemical vapor deposition method and a sputtering process are performed in-situ in a high density plasma apparatus to deposit the second silicon oxide film 13 in the trench (gap).
그리고 도 4c와 같이 습식각이나 반응성 이온식각으로 제 2 실리콘산화막(13)을 등방성식각하면 트랜치 측벽에 형성된 제 2 실리콘산화막(13)은 거의 제거되고 트랜치 바닥에는 제 2 실리콘산화막(13)이 이전의 제 1 실리콘산화막(12)이 남아있던 위에 남아 있다. 이에 따라서 다음 증착공정을 할 때 종횡비가 더 줄어들게된다. 이후에 고밀도 플라즈마 상태의 장비에서 화학기상증착법과 스퍼터링 공정을 동시에(in-situ) 진행하여 제 3 실리콘산화막(14)을 증착한다.If the second silicon oxide film 13 isotropically etched by wet etching or reactive ion etching as shown in FIG. 4C, the second silicon oxide film 13 formed on the trench sidewalls is almost removed, and the second silicon oxide film 13 is transferred to the bottom of the trench. Of the first silicon oxide film 12 remains. As a result, the aspect ratio is further reduced during the next deposition process. Thereafter, the third silicon oxide layer 14 is deposited by performing a chemical vapor deposition method and a sputtering process in-situ in a high density plasma apparatus.
또는 상기 각 실리콘산화막을 증착할 때 트랜치 측벽의 스텝 커버리지가 열악하게 하기 위해서 저압의 플라즈마 상태에서 증착한 후에 캐미컬 에치할 수도 있다.Alternatively, chemical deposition may be performed after deposition in a low pressure plasma state in order to reduce the step coverage of the trench sidewalls when the silicon oxide films are deposited.
그리고 상기 트랜치 측벽의 실리콘산화막을 식각할 경우에 반도체기판이 식각 방지막의 역할을 한다. 또한 실리콘산화막을 식각할 때 식각방지막의 역할을 하도록 트랜치에 실리콘산화막과 식각선택성이 다른 물질을 먼저 증착할 수도 있다.When etching the silicon oxide film on the sidewalls of the trench, the semiconductor substrate serves as an etch stop layer. In addition, a material having a different etching selectivity from the silicon oxide layer may be deposited on the trench to serve as an etch stop layer when the silicon oxide layer is etched.
이와 같이 한 장비에서 연속하여 증착과 스퍼터링공정을 진행하고 이후에 등방성 식각공정 반복하여 진행하므로써 0.1㎛미만의 매우좁은 갭이나 사이드 스텝 커버리지(side step coverage)가 0.3이하로 작고 갭 내부의 바텀 스텝 커버리지(bottom step coverage)가 0.8이상으로 큰경우의 갭을 용이하게 채울 수 있다.As described above, the deposition and sputtering processes are continuously performed in one device, and then the isotropic etching process is repeatedly performed so that a very narrow gap or side step coverage of less than 0.1 µm is smaller than 0.3 and the bottom step coverage within the gap is small. If the bottom step coverage is larger than 0.8, the gap can be easily filled.
이와 같은 갭 필링방법은 격리영역(예;트랜치 격리영역)이나 층간절연막이나 금속층간 절연막 등에 형성된 갭을 채우는 공정에 모두 사용할 수 있다.Such a gap filling method can be used both for filling gaps formed in an isolation region (for example, a trench isolation region), an interlayer insulating film, a metal interlayer insulating film, or the like.
상기와 같은 본 발명 반도체소자의 갭필링방법은 다음과 같은 효과가 있다.The gap filling method of the semiconductor device of the present invention as described above has the following effects.
고밀도 플라즈마 장비에서 화학기상증착과 스퍼터링공정을 동시에 진행한 후 등방성으로 식각하여 갭의 측벽에 형성된 산화막을 제거하는 공정을 반복하여 0.1㎛미만의 매우좁은폭의 갭(gap)이나 3이상의 종횡비를 갖는 갭을 보이드(void) 없이 채우기에 용이하다.After performing chemical vapor deposition and sputtering process in high density plasma equipment at the same time, it isotropically etched to remove the oxide film formed on the side wall of the gap, and has a very narrow gap of less than 0.1 μm or an aspect ratio of 3 or more. Easy to fill gaps without voids.
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