JPH03116776A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:In a semiconductor storage device wherein sense amplifiers are arranged adjacently to memory cell arrays, to prevent the imbalance of a sense amplifier so as to equalize the properties of a semiconductor storage device by arranging common connection lines for sense amplifiers at the outermost ends of sense amplifier rows. CONSTITUTION:The source region of a transistor Q11 is connected to a common connection line 1 with contacts C, and the drain region is connected to a digit line D1, similarly. And, the digit line D1 is connected to the drain of Q11, and is also connected to the gate of Q12, and similarly - D1 is connected to the gate of Q11 and the drain of Q12. Moreover, D1 and D1 are intercrossed. Q11, Q12, D1, and -D1 constitute the sense amplifier row at the leftmost end, and Qn1, Qn2, Dn, and -Dn constitute the sense amplifier row at the rightmost end. This way, mutually adjacent sense amplifier rows have approximately mirror symmetrical shape. In these sense amplifier rows, common connection lines are arranged at outermost ends, but digit lines are not arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a sense amplifier array arranged adjacent to a memory cell array.

[Conventional technology]

FIG. 4 is a circuit diagram of a sense amplifier of a conventional dynamic semiconductor memory device. By making the potential the same as that of the common connection line 1, it serves to amplify the minute potential difference that occurs between the digit line and the digit line (2) and transmit it to the next stage. Therefore, slight differences in conditions can greatly affect its performance.

For this reason, conventionally, when this type of sense amplifiers are arranged in a row, devises have been made to reduce variations in digit line and 100 degrees that occur during manufacturing, and to reduce parasitic capacitance.

Both FIGS. 2 and 3 are pattern layout diagrams showing examples of conventional sense amplifier arrays.

In the figure, digit line D11 (made of polycrystalline silicon film), transistors Q11, Ql
2 constitutes the sense amplifier shown in FIG. Similarly, digit lines Dn, Dn, transistors Qnl, Qn
2 constitutes another sense amplifier. Note that, for convenience, the portions marked with parallel hatching are aluminum wiring, and the portions surrounded by thick lines are transistors formed.

[Problem to be solved by the invention]

As integrated circuits become increasingly finer, it has become impossible to ignore the influence of not only the parasitic capacitance that occurs at the bottom of interconnects, but also the parasitic capacitance that occurs between parallel interconnects.

In the conventional sense amplifier array described above, the digit line of the sense amplifier at the end has no adjacent signal line, and has different conditions from other sense amplifiers. Therefore, there is a drawback that an imbalance occurs in the sense amplifier, and the uniformity of the semiconductor memory device is impaired.

[Means to solve the problem]

According to the present invention, in a semiconductor memory device in which a sense amplifier column is arranged adjacent to a memory cell array, a common connection line of the sense amplifiers is arranged at the end of the sense amplifier column.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a pattern layout diagram showing a sense amplifier array according to an embodiment of the present invention.

For example, the transistor Qll is provided in a region surrounded by a thick line, and the digit line T is the gate, and the source region and the drain region are provided on the left side and right side of the gate, respectively. The source region of Qll is a contact) common connection line 1 at C.
, and the drain region is similarly connected to the digit line D.
Connected to 1. Then the digit line D1 becomes Q'
It is connected to the drain of l1 and to the gate of Ql2, and similarly DI is connected to the gate of Qll and the drain of Ql2. Further, Dl and D1 are arranged to intersect with each other as shown in the figure.

Ql 1. Ql 2. DI, DI left ')it end')
A sense amplifier array is configured, Qnl, , Qn2 . Dn.

The cloves make up the farthest sense amplifier row on the right. Thus, adjacent rows of sense amplifiers are substantially mirror symmetrical in shape.

In this sense amplifier array, a common connection line is arranged at the end, and no digit line is arranged.

Therefore, the endmost sense amplifier, especially the digit line, is prevented from becoming unbalanced with other sense amplifiers with respect to its parasitic capacitance.

〔Effect of the invention〕

As explained above, the present invention prevents unbalance of the sense amplifiers by alternately making the sense amplifiers mirror-symmetrical and arranging the common connection line at the end of the sense amplifier array, thereby improving the characteristics of the semiconductor memory device. This has the effect of making it more uniform.

[Brief explanation of drawings]

FIG. 1 is a pattern layout diagram showing one embodiment of the present invention, FIGS. 2 and 3 are pattern layout diagrams showing two conventional sense amplifier arrays, and FIG. 4 is a circuit diagram of the sense amplifiers. 1...Common connection line, D, D, DI, Ding T,...
・Dn, clove... digit line, Ql, Q2.
Ql 1゜Q 12 , -, Qn 1 , Qn 2
= MO3) transistor.

Claims (2)

[Claims] (1) A semiconductor memory device in which a sense amplifier row is arranged adjacent to a memory cell array, wherein a common connection line of the sense amplifiers is arranged at the end of the sense amplifier row. . (2) The semiconductor memory device according to claim (1), wherein the shapes of adjacent sense amplifiers are mirror symmetrical to each other.