JP2904082B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including a circuit requiring a transistor pair such as a differential amplifier circuit or a current mirror circuit.
The present invention relates to a layout of a gate electrode in the case of using a field effect transistor.

[0002]

2. Description of the Related Art When a circuit is formed on a semiconductor substrate using a MOS type field effect transistor (hereinafter, referred to as a MOS transistor), a current mirror circuit, a differential amplifier circuit whose circuit diagram is shown in FIG. A pair MOS transistor is often used in a circuit that requires a transistor pair as described above. As an example of the layout of such a paired MOS transistor, the aluminum distribution of the n-channel type MOS transistors M ₁ and M _{2 in} the differential amplifier circuit shown in FIG.
The layout including the lines is shown in FIG.

Referring to FIG. 3, these MOS transistors are so-called silicon gate MOS transistors. Some of the polysilicon wiring G ₁₀ serves as a gate electrode of the transistor M _1. Similarly, the polysilicon wiring G
Some of the ₂₀ serves as a gate electrode of the transistor M _2. These two polysilicon wirings G ₁₀ , G ₂₀ are both bent into a U-shape, and the respective transistors M ₁ , M 20
_{The two} gate electrodes are arranged in parallel. That is, if the polysilicon wiring G ₁₀ and the polysilicon wiring G ₂₀ has a symmetrical layout with respect to the portion of the gate electrode. On both sides of each gate electrode, an n ⁺ diffusion layer region 1 is formed to serve as a source region or a drain region of each transistor. Each diffusion layer region 1 is connected to an aluminum wiring 3 through a contact hole 6.
4 and 5 are connected. In the case of FIG. 3, the aluminum wiring 3 is a wiring for connecting the source electrodes of the transistors M ₁ and M ₂ in FIG. On the other hand, the aluminum wiring 4 is a wiring for connecting the drain electrode of the transistor M ₁ to the resistor R _1. Further, the aluminum wiring 5 is a wiring for connecting the drain electrode of the transistor M ₂ to the resistor R _2.

[0004]

In the paired MOS transistor of the conventional layout described above, the transistor M ₁
And easily unbalance occurs in electric characteristics between the transistor M _2. This is a photolithographic process at the time of manufacturing, and the dimension (hereinafter referred to as the gate direction) of the transistors M ₁ and M _{2 in} the channel length direction (in this case, the horizontal direction in FIG. 3 ) is between the polysilicon wirings G ₁₀ and G ₂₀ . This is because a difference occurs in the electrode length).

That is, in a semiconductor integrated circuit, various signal processing circuits are formed on the same substrate in addition to the differential amplifier circuit using the paired MOS transistors M ₁ and M ₂ . Therefore, although only the paired MOS transistors M ₁ and M ₂ are shown in FIG. 3 , many other circuits exist around these paired MOS transistors. However, circuits arranged around such paired MOS transistors are not necessarily all arranged symmetrically with respect to the paired MOS transistors M ₁ and M ₂ . That is, before the gate electrode forming step, the optical state and the hydrodynamic state around the paired MOS transistors M ₁ and M ₂ , such as the three-dimensional unevenness and the surface roughness of the substrate, are changed to the paired MOS transistors. It is not necessarily symmetrical across the transistor. As a result, in the gate electrode forming step, the outermost polysilicon wirings G _1L and G _2R of the paired MOS transistors are affected by the asymmetry of the adjacent regions, and the gate electrode lengths are different. When exposing the resist, the degree of light interference varies from place to place, and at the time of development, there is a difference in the amount of developer supplied or the amount of resist dissolved in the development that has been removed from the spot, resulting in a difference in the resist pattern. This is because there is a difference in dimensions between locations. Further, at the time of etching, a difference in the supply amount of the etchant gas and a difference in the discharge amount of the gas generated by the etching are generated, which causes a difference in the etching amount for each location.

[0006] If there is such a variation in the size of the gate electrode of each transistor, the electrical characteristics of the paired MOS transistors M ₁ and M ₂ will differ. As a result, an offset occurs in the differential amplifier circuit using the paired MOS transistors, and the accuracy of the mirror ratio decreases in the current mirror circuit.

SUMMARY OF THE INVENTION Accordingly, the present invention provides a semiconductor integrated circuit having a paired MOS transistor, in which the dimensional variation of the gate electrode during exposure and etching in a photolithographic process is improved, and the relative accuracy of the electrical characteristics of the paired MOS transistor is increased. It is intended for.

[0008]

The semiconductor integrated circuit of the present invention According to an aspect of the met semiconductor integrated circuit including a first and an transistor pair of the second MOS field effect transistors to each other each of the gate electrodes are juxtaposed to each other Above
For the first and second MOS field effect transistors,
Each gate electrode is arranged in parallel with the first and second gate electrodes.
The first and second MOS field effect transistors are arranged in rows.
Third and fourth MOS field effect devices sandwiching a transistor from both sides
This is a semiconductor integrated circuit provided with a transistor. Thereby, when the layout of the circuits arranged around the transistor pair is asymmetric, the asymmetric optical and hydrodynamic influence that the asymmetry has on the inside of the region of the transistor pair when forming the gate electrode is cut off. Therefore, there is no variation in the gate electrode length.

[0009] In the semiconductor integrated circuit of the present invention , the third and the third aspect are provided.
And the gate electrode of the fourth MOS field effect transistor is
The gates of the first and second MOS field effect transistors are
The first MOS transistor is made of the same material as the gate electrode material.
The gate electrode of the field effect transistor and the second M
Impurities outside the gate electrode of OS type field effect transistors
They are arranged in parallel in the object area. As a result, the underlying state of the gate electrode wirings of the newly provided third and fourth MOS field effect transistors becomes the same as the underlying state of the original MOS field effect transistor forming the transistor pair. In this case, the variation in the gate electrode length is further reduced.

[0010] The semiconductor integrated circuit according to the present invention is the semiconductor integrated circuit according to the above , wherein the third and fourth MOS field-effect devices are used.
The gate electrodes of the transistor are connected to the third and
4 is connected to a potential point at which the MOS field effect transistor is turned off. If the gate electrode is left floating, the conduction state may be unstable due to electrical influences from other circuits on the same substrate.In the present invention, however, since the gate potential is fixed, The operation of this MOS field effect transistor is stable.
In addition, since the gate potential and the source potential are set to the same potential and the transistor is turned off, there is no need to consider this transistor when designing a circuit.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings. 1, a pair of MOS transistors according to an embodiment of the present invention, aluminum
It is a layout diagram including wiring . Referring to FIG. 1, the original pair MOS transistors M _1, that one by one new MOS transistors on both sides of the M ₂ M _3, M ₄ is provided with a conventional pair MOS transistor shown in FIG. 2 Is different. The gate electrodes G ₃ , G ₄ of these MOS transistors M ₃ , M ₄ are parallel to the gate electrodes G ₁₀ , G ₂₀ of the original paired MOS transistors M ₁ , M ₂ and are connected to the gate electrodes G ₁₀ , G ₂₀ . It is arranged so as to sandwich it. That is, the gate electrode G ₃ of the transistor M ₃ are,
Further left outside the gate electrode G _1L of the gate electrode G ₁₀ of the transistor M _1, they are arranged in parallel. Similarly, the gate electrode G ₄ of the transistor M ₄ is outside the gate electrode G _2R of the gate electrode G20 of the transistor M ₂
Are arranged in parallel on the further right side of. These gate electrodes G ₃ and G ₄ are made of a polysilicon layer, and
_10, during the formation of G _20, simultaneously forming a resist pattern, is etched.

[0012] polysilicon wiring for the gate electrode G ₃ of the transistor M ₃ are, through a contact hole connected to the aluminum wiring 7, and further connected to the n ⁺ diffusion layer regions 1L via the contact hole 6. The aluminum wiring 7 is normally connected to the lowest potential point V _SS (not shown) in the circuit. That is, the transistor M ₃ are being the lowest potential in the same circuit and the gate electrode and the source electrode, a transistor which is in blocking state. Similarly, the polysilicon wiring for the gate electrode G ₄ of the transistor M ₄ is connected to the aluminum wiring 8 via the contact hole, and further connected to the n ⁺ diffusion layer region 1 R via the contact hole 6. The aluminum wiring 8 is connected to the lowest potential point V _SS in the circuit. Thus, the transistor M ₄ is, and a gate electrode and a source electrode is the minimum potential in the same circuit, a transistor which is in blocking state.

As described above, the silicon gate MOS transistors M ₃ and M ₄ are further outside the paired MOS transistors M ₁ and M ₂ , the gate electrode G ₃ is parallel to the gate electrode G _1L , and the gate electrode G ₄ is the gate electrode. By arranging the electrodes so as to be parallel to the electrode G _2R , the polysilicon lines G ₁₀ and G ₂₀ for the gate electrodes of the paired MOS transistors M ₁ and M ₂ must be adjacently arranged on both sides. Silicon wiring will be present. Therefore, even if the irregularities and surface states around the paired MOS transistors are asymmetric, the gate electrodes G _1L and G _2R outside the original transistors M ₁ and M ₂ are not directly affected by the asymmetry. There is no. Therefore, when forming the gate electrode, there is no difference in the formation and etching of the resist pattern for each gate electrode portion.

In this embodiment, the original pair M
Although the silicon gate MOS transistors M ₃ and M ₄ are formed on both sides of the OS transistors M ₁ and M ₂ , the transistors need not be transistors from the above description.
Obviously, it may simply be a polysilicon wiring. However, when the gate electrode length of the MOS transistor is very small, on the order of submicrons, subtle differences such as the state of irregularities around the gate electrode and the surface state of the base on which the gate electrode is formed may be caused by the resist pattern size and A large influence on the amount of etching, the final MOS
The channel length of the transistor, in other words, the transistor characteristics vary greatly. From this point of view, the polysilicon wirings G ₃ , G ₄ provided outside the gate electrodes G _1L , G _2R outside the original paired MOS transistors M ₁ , M ₂
It is preferable that the state of the base and the periphery of the transistor M ₁ and M ₂ be the same as the state of the base and the periphery of the transistors M ₁ and M ₂ , that is, it is desirable to provide a transistor structure by providing a diffusion layer region. In this case, if the gate electrode is in a floating state, the conductive state may be unstable due to electrical influences from other circuits on the same substrate. Therefore, it is better to fix the gate potential. good. If the gate potential and the source potential are set to the same potential, this MOS transistor is cut off, so that it is not necessary to consider this transistor in circuit design, which is convenient.

[0015]

As described above, in the semiconductor integrated circuit of the present invention, two wirings made of a gate electrode material are provided so as to sandwich the gate electrode pair of the paired MOS transistor in the semiconductor integrated circuit including the paired MOS transistor. In parallel with each gate electrode of the paired MOS transistors,
It is arranged. As a result, according to the present invention, the optical and hydrodynamic effects received from peripheral circuits when forming the gate electrode in the original paired MOS transistors are equal for all the gate electrodes, so that variations in the gate electrode length are reduced. Disappears.

In the semiconductor integrated circuit of the present invention, the two wirings made of the above-mentioned gate electrode material are replaced with the original pair MO.
MOS field effect transistors are formed in the diffusion layer regions on both sides of the S transistor, respectively.
As a result, according to the present invention, the base state of the newly provided gate electrode wiring becomes equal to the base state of the original paired MOS transistors, so that the variation in the gate electrode length in the photolithographic process is further reduced.

According to the semiconductor integrated circuit of the present invention, a wiring made of a gate electrode material is connected to the above-mentioned semiconductor integrated circuit at a potential point at which a MOS transistor whose gate electrode is a gate electrode is turned off. doing. Thus, according to the present invention, the newly provided MOS transistor for equalizing the dimensions of the gate electrode becomes a transistor in a cut-off state in which the gate potential is fixed, so that the operation of the circuit is not disturbed. It is not necessary to consider this transistor when designing the circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout of a paired MOS transistor used in a semiconductor integrated circuit according to an embodiment of the present invention, and a circuit diagram of a differential amplifier circuit using the same.

FIG. 2 is a circuit diagram of an example of a differential amplifier circuit.

FIG. 3 is a diagram showing an example of a layout conventionally used for a paired MOS transistor used in the circuit shown in FIG. 2 ;

[Explanation of symbols]

1, 1 L, 1R n ⁺ diffusion layer region 3,4,5,7,8 aluminum wiring _{M 1, M 2, M 3} , M 4 MOS transistors _{G 10, G 20, G 1L} , G 2R, G 3, G ₄ polysilicon wiring R ₁ , R ₂ resistance I constant current source

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit including a transistor pair composed of first and second MOS field effect transistors in which respective gate electrodes are arranged in parallel with each other, wherein each gate electrode is connected to the first and second gate electrodes. Parallel to the gate electrode
The first and second MOS field effect transistors are arranged in rows.
Two MOS field effect transistors sandwiching the transistor from both sides
A gate electrode having the first and second MOs.
Same material as the gate electrode material of S-type field effect transistor
Said first MOS field effect transistor
Gate electrode and the second MOS field effect transistor
Parallel in the impurity region outside the gate electrode of the
Third and fourth MOS field effect transistors are provided.
Only, gate of said third and fourth MOS field effect transistor
A gate electrode connected to a potential point at which the third and fourth MOS field-effect transistors are turned off. 2. The semiconductor integrated circuit according to claim 1 , wherein
A semiconductor integrated circuit, wherein the gate electrode material of the first to fourth MOS field effect transistors is polycrystalline silicon.