JPH03116034U - - Google Patents

Info

Publication number
JPH03116034U
JPH03116034U JP1990025766U JP2576690U JPH03116034U JP H03116034 U JPH03116034 U JP H03116034U JP 1990025766 U JP1990025766 U JP 1990025766U JP 2576690 U JP2576690 U JP 2576690U JP H03116034 U JPH03116034 U JP H03116034U
Authority
JP
Japan
Prior art keywords
chips
circuit board
bonded onto
presser plate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990025766U
Other languages
English (en)
Other versions
JPH083006Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990025766U priority Critical patent/JPH083006Y2/ja
Publication of JPH03116034U publication Critical patent/JPH03116034U/ja
Application granted granted Critical
Publication of JPH083006Y2 publication Critical patent/JPH083006Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図ａは、この考案の一実施例に係る半導体
装置の実装構造を側方より見た図、第１図ｂは、
同半導体装置の実装構造を上方より見た図、第２
図ａ及び第２図ｂは、それぞれ順に同半導体装置
の実装構造の実装工程を説明する図、第３図は、
同半導体装置の実装構造の変形例を示す図、第４
図ａは、先願に係る半導体装置の実装構造を側方
より見た図、第４図ｂは、同半導体装置の実装構
造を上方より見た図である。 １……チツプ、１ａ……パツド、２……バンプ
、３……基材、４……押さえ板、５……シリコン
ゴム、６，７……接着剤、Ａ……配線パターン、
Ｂ……回路基板。

Claims (1)

    【実用新案登録請求の範囲】
  1. 回路基板上に複数個並べて搭載されるチツプと
    、これら各チツプのパツド上に形成され、前記回
    路基板上の配線パターンに圧接されるバンプと、
    前記回路基板上に接着され、前記チツプの配列方
    向に沿つて延伸する１対の基材と、前記チツプの
    それぞれに備えられ、両端部が前記基材上に接着
    される押さえ板と、この押さえ板に設けられ、前
    記各チツプの背面を押圧して、前記バンプと配線
    パターンとの圧接状態を保持する弾性体とからな
    る半導体装置の実装構造。
JP1990025766U 1990-03-14 1990-03-14 半導体装置の実装構造 Expired - Fee Related JPH083006Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990025766U JPH083006Y2 (ja) 1990-03-14 1990-03-14 半導体装置の実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990025766U JPH083006Y2 (ja) 1990-03-14 1990-03-14 半導体装置の実装構造

Publications (2)

Publication Number Publication Date
JPH03116034U true JPH03116034U (ja) 1991-12-02
JPH083006Y2 JPH083006Y2 (ja) 1996-01-29

Family

ID=31528689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990025766U Expired - Fee Related JPH083006Y2 (ja) 1990-03-14 1990-03-14 半導体装置の実装構造

Country Status (1)

Country Link
JP (1) JPH083006Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008029802A (ja) * 2006-06-29 2008-02-14 Sadao Kiyomiya 遊技媒体数量表示システム、並びに遊技媒体数量測定装置及び同方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008029802A (ja) * 2006-06-29 2008-02-14 Sadao Kiyomiya 遊技媒体数量表示システム、並びに遊技媒体数量測定装置及び同方法

Also Published As

Publication number Publication date
JPH083006Y2 (ja) 1996-01-29

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Legal Events

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