JPH0311453A - Multi cpu device - Google Patents

Abstract

PURPOSE:To perform multi CPU interruption even without providing an interruption signal on a system bus by generating the interruption signal with an address decoder and an iD number comparator in a control unit. CONSTITUTION:When interruption on the control unit 30 is performed with the control unit 20, the iD number set at the unit 30 and an interruption level are generated on the system bus 10 by issuing an interruption request from the CPU of the unit 20. Each control unit checks whether or not the part of the iD number on the address coincides with the iD number set at its own iD switch 55 with a comparator 54 via a local bus. At such a case, the fact that they coincide in the unit, and the part of the iD number on the address coincides with its own iD number to the address decoder 53 via a control line 64. The decoder 53 decodes the part of a level, and informs a requested interruption level to a controller 52 via the interruption signal 62, then the interruption on the unit 30 is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multi-CPU interrupt device in which a plurality of CPUs are connected on one system bus.

Conventional technology FIG. 4 shows the configuration of a conventional multi-CPU device.

In FIG. 4, 1 is a system bus, and address buses 11. Data bus 12. Control signal 131 Interrupt signal 1
It consists of 4. 2 is a control unit, CPU21i
It is mainly composed of control circuits such as an interrupt controller 22, and is connected to the system bus 1. The system bus 1 connects the control unit 3. A plurality of control units having the same configuration as control unit 2, such as control unit 4, are connected.

FIG. 6 shows a conventional interrupt method for a multi-CPU device. In FIG. 6, 22, 32, and 42 are respective interrupt controllers of the control units 2, 3, and 4 shown in FIG. 24, 26° 34.36.44.4
5 is an interrupt signal on the system bus shown in FIG.
Two wires are connected to each interrupt controller for transmission and reception between the interrupt controllers.

Next, the operation of the above conventional example will be explained. In FIG. 4, when each control unit issues an interrupt to another control unit, an interrupt signal 14 on the system bus 1 is used. For example, when interrupting the control unit 3 from the control unit 2, the interrupt signal 24, which is one of the interrupt signals in FIG. 6, is used.

In this way, the conventional multi-CPU interrupt method described above can be implemented by providing two interrupt signals between each control unit on the system bus.

Problem to be Solved by the Invention However, in the conventional multi-CPU device described above, the number of interrupt signals on the system bus depends on the number of control units, so when the number of control units increases, the system bus capacity becomes abnormal. There was a problem that it got bigger. Furthermore, in a multi-CPU device that is added to the control unit later, there is a problem in that the number of interrupt signals cannot be fixed.

The present invention solves many conventional problems.
The object of the present invention is to provide an excellent multi-CPU device that can realize multi-CPU interrupts using existing address buses and control signals without providing an interrupt signal line on a system bus.

Means for Solving the Problems In order to achieve the above object, the present invention assigns all ID numbers to each control unit, provides a comparator and an address decoder, and combines the ID number of the control unit that issues an interrupt with the interrupt level. This allows interrupt notification to be made by generating an address.

Therefore, according to the present invention, an interrupt signal can be generated by the address decoder and ID number comparator in the control unit, and multi-crtt interrupts can be performed without providing an interrupt signal on the system bus.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 10 is a system bus, which is composed of 7) "res bus 111, data bus 112, and control signal 113. 20 is a control unit, which is composed of a CPU 121 and other control circuits such as an interrupt control circuit 122. The system bus 10 connects a plurality of control units having the same configuration as the control units 1-20, such as control unit) 30 and control unit) 40.

FIG. 2 shows the main parts around the interrupt control circuit in the control unit shown in FIG. A CPU 61 has a local bus 6 and a control signal 61.

An interrupt controller 62 notifies the CPU 51 via a control line 63 that an interrupt has been generated. 63 is an address decoder which outputs an interrupt signal 62 to the interrupt controller 62 according to the conditions of the decoding result of the local bus 6.
to occur. A comparator 64 compares the ID switch 66 to which the ID number is set and the local bus 6, and if the contents match, it notifies the address decoder 63 via the control line 64. The ID number is uniquely set for each control unit. A driver/receiver 66 serves as a gate between the system bus 1 and the local bus 6.

FIG. 3 shows the address structure when each control unit issues an interrupt to another control unit.

Interrupt requests 71, 72, and 73 indicate that an address that is a combination of ID number 74 and interrupt level 76 is generated.

Next, the operation of the above embodiment will be explained. In the above embodiment, when the control unit 2o issues an interrupt to the control unit 30, the CPU of the control unit 2o first sends an interrupt request to the address that combines the ID number 74 set in the control unit 30 and the interrupt level 76. 1. generated on the system bus. Each control unit sends this address to a comparator 64 via the local bus 6.
Then, it is checked whether the 1D number 74 part on the address matches the 1D number set in its own in switch 66. In this case, there will be a match within the control unit 3, and the address decoder 63 will be notified via the control line 64 that the ID number 74 on the address matches its own ID number. And address decoder 6
3 decodes the interrupt level 76 part on the address and notifies the interrupt controller 62 of the requested interrupt level via the interrupt signal 62. and,
An interrupt is applied to the CPU of the control unit 1-30 via the control line 63. Furthermore, the control signal 1 on the system bus 1o
13 and the control signal 61 on the local bus 6 are assumed to be write signals or read signals of the CPH.

In this way, according to the above embodiment, if an address decoder and a 1D number comparator are provided in the control unit, an interrupt signal can be created in the control unit, so multi-CPU interrupts can be generated without providing an interrupt signal on the system bus. It has the effect of being able to. Further, the address decoder has the effect that a plurality of interrupt signals can be given between the same control units.

The advantages and disadvantages of the invention, as is clear from the above embodiments, are that an interrupt signal can be generated by the address decoder and ID number comparator in the control unit, and multi-channel processing can be performed without providing an interrupt signal on the system bus. This has the effect of allowing CPU interrupts.

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram of a multi-CPU device according to an embodiment of the present invention, Fig. 2 is a block diagram of main parts of each control unit of the same device, Fig. 3 is an address configuration diagram of an interrupt request, and Fig. 4 is a conventional Schematic block diagram of multi-CPU device, No. 6
The figure shows the interrupt method of the same device. 121.131.141...CPU+ 122
゜132, 142... Interrupt control circuit, 51
...CPU, 62...Interrupt controller +63...Address decoder, 64...
·comparator.

Claims (1)

[Claims] Each of the plurality of CPUs is provided with an ID number and an address decoding circuit, and means is provided for generating an address that is a combination of the ID number and interrupt level of the other CPU.
A multi-CPU device that can send interrupt notifications from U.