JPH03114222A - Union of gaas on si substrate - Google Patents

Abstract

PURPOSE: To reduce a stress in a material caused from a difference from a thermal expansion coefficient, by inducing very small cracks in a GaAs layer at a position where an electronic device or its component that integrates the GaAs on a Si substrate. CONSTITUTION: In order to attain a introduction of very small cracks at a position where the operation of the device or its component is not disturbed, part of the substrate is coated by a mask prior to the adhesion of the GaAs. The mask is preferably an SiO2 mask. Very small cracks are induced at a desired position by using a specific topography of the mask (very small structure). In a first process, an SiO2 is adhered on the Si substrate by, e.g. the plasma enhancement chemical vapor-deposition(PECVD). Part of the SiO2 layer is again removed by forming the mask with the photolithography and wet etching. Then, the GaAs is adhered onto the Si substrate that is partially coated by, e.g. the metallic organic chemistry vapor-deposition(MOCVD). Very small cracks are induced by the specific mask topography in the single crystal GaAs that is grown from an apex in a cleavage direction. No very small cracks are found on the other position.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the integration of GaAs on an 8-top substrate.
ration).

In particular, the present invention is particularly applicable to GaAs/Al! devices such as light emitting diodes on an 8-layer substrate, which can also integrate Si electronic circuits such as LED drivers (field effect transistors). Concerning the integration of GaAs electronic or optoelectronic structures.

GaAs layer or GaAs structure, e.g. GaAs /A/
GaAs light emitting diodes are made of Si at high temperatures, i.e. 700°C.
It can be grown substantially stress-free on a substrate.

However, during cooling, the differential contraction of GaAs and Sl creates stresses in the material.

These stresses cause the wafer to bend when the thickness of the GaAs layer grown on the substrate is fairly small, for example when the thickness does not exceed 3 .mu.m.

When the GaAs layer is thick, microcracks may appear in the oriented overgrowth layer on the wafer.

The presence of material stress negatively affects the electrical and/or optical properties of GaAs/Si devices. Material deviations interfere with phosphorography and subsequent processing of the wafer. Inadvertently occurring microcracks interfere with the proper operation of the electronic device being formed.

The above-mentioned problems encountered when growing GaAs layers on 8-top substrates are discussed in the following publications: Appl, Phys.

Let t, Vol. 51, No. 26 E.L.G., Yao
"Stress Variations Dew Two Microglux in Ga" announced by obi etc.
As Grown On-SiJ, and Appl, P
Hys, Lett.

``Stress Variations and L'' published by B, G, YaoObi et al. in Vol.
/ IJ-Fin Patterned GaAs Grown on Mismatched Substrates.

Several solutions are known to the painters to deal with the problems mentioned above. Appl, Phys, Lett, 53rd
In Vol. 3, a paper titled "Misalignment of GaAs on S1 and its reduction due to selective growth of GaAs through a silicon shadow mask by molecular beam oriented overlapping growth" was published. Completely covered GaAs with selective growth on GaAs (obtained by using a Si shed mask)
-Si wafers- and the deviation of Sl have been studied.

By limiting the GaAs growth region, a significant reduction in deviation is seen.

It is also known to provide a film on the backside of a silicon substrate to counteract the stresses induced by the GaAs oriented overgrowth layer.

It is an object of the present invention to provide a method for growing GaAs on an 8-top substrate, thereby obtaining a reduction in the stresses in the materials resulting from the differences in the coefficients of thermal expansion of these materials.

Another object of the invention is to provide a method for growing GaAs on a Si substrate, resulting in a flat wafer such that subsequent phosphorography is not disturbed.

Yet another object of the present invention is to provide a method for integrating GaAs electronic or optoelectronic devices on an 8-top substrate such that microcracks do not occur in the active area of the device.

Other purposes will become apparent from the description below.

The present invention is a method for forming integrated electronic devices or components thereof by growing GaAs on a substrate at a constant temperature and subsequently cooling the substrate, the device or components thereof being undisturbed. A method is provided, characterized in that microcracks are induced in the GaAs layer at locations.

By intentionally creating microcracks in an integrated device according to the invention, stress in the material can be reduced and the generation of microcracks at random locations can be avoided.

In order to achieve the aforementioned microcracking in a location where the operation of the device or its parts is not disturbed, a portion of the substrate is covered with a mask before the GaAs deposition.

This mask is Si0. Preferably it is a mask.

It has been found that by using a specific topography of the mask (as explained below with reference to the drawings), microcracks can be induced at desired locations.

C) By using a mask with a few (and one) vertices oriented in the cleavage direction of the aAs crystal, microcracks starting from said vertices and growing in said cleavage direction are induced in the single crystal layer.

Therefore, the present invention further relates to the general use of G grown on Si substrates.
A method is provided for forming microcracks at predetermined locations in an aAs layer, and prior to growth of the GaAs layer, the Si substrate is partially covered by a mask, and the mask is applied to the crystals of the GaAs layer. It is characterized by providing at least one vertex extending in the cleavage direction or substantially in the cleavage direction.

The mask topography, particularly the location and number of vertices, can be selected such that microcracks can be intentionally induced at predetermined locations.

The so-called vertices act as wedges that cleave the GaAs crystal, and are therefore also referred to herein as "wedges."

In the first step, S10. is deposited on a Si substrate, for example by plasma enhanced chemical vapor deposition (pEcvD). S
in, parts of the layer are removed again to form a mask by photolithography and wet etching.

The partially coated Si substrate is then coated with GaAs, e.g.
VD).

According to this method, GaAs is deposited on Si in a quartz reactor. For example, the metal organic source trimethyl gallium (CH
3) 3Ga can be used to transport the Group I component, ie Ga, using hydrogen as a carrier gas.

Arsine can be used to transport the Group I element As.

Selenium hydride can be used to obtain n-type doping,
Diethylzinc (transport vapor hydrogen) can be used to obtain p-type doping.

The source is heated in a quartz reactor.

GaA is produced by the following simplified thermal decomposition reaction at 700°C.
s is deposited on the Si substrate present in the reactor.

(CH3), GaAs crystal The morphology of the deposited GaAs is determined by, among other things, the properties of the underlying material. Monocrystalline GaAs is obtained on the uncovered S1 regions, while polycrystalline GaAs deposits are found on the SiO2 mask.

By using the specific mask topography according to the present invention, single crystal G
Microcracks are induced in aAs. No microcracks are found at other locations.

For a better understanding of the invention and its preferred embodiments, it will be described in detail below with reference to the accompanying drawings and photographs.

Figure 1 shows GaAs/A/G integrated on a Si substrate.
aAs light emitting diode and field effect transistor (M
osFET) is schematically illustrated.

Figure 2 is a reproduction photograph showing naturally occurring microcracks.

FIG. 3 schematically shows the location of intentionally induced microcracks on a substrate on which an electronic or optoelectronic device grows.

Figure 4 shows the use of SiO□ mask and G on the wafer.
The growth of aAs is shown.

FIG. 5 shows a mask that can be used to obtain induced microcracks.

FIG. 6 is a reproduction photograph showing the induced microcracks.

Figures 7 and 8 show another type of mask.

FIG. 9 is an enlarged view of another type of vertex.

Figures 10 to 13 show the results of experiments conducted during crack formation.

FIG. 1 shows an example of a device consisting of a first component, in particular a field effect transistor 2, which is a Si circuit, and a second component, ie a light emitting diode 3, which is a GaAs component. The image components are integrated on a common silicon substrate 1. The light emitting diode 3 has five layers grown on top of each other.

A GaAs buffer layer is first grown on the silicon substrate.

On top of the GaAs buffer layer, an A/GaAs cladding layer, an active GaAs or A/GaAs layer, a second AI!
A GaAs cladding layer and finally a GaAs contact layer are grown.

Figure 2 shows GaAsZA1GaA deposited on a Si substrate.
It shows naturally occurring microcracks in the s-layer structure. Unfortunately, this microcrack extends through the active part of the GaAs light emitting diode, rendering the device useless (photo taken with an electron microscope).

From the temperature for growing GaAs on a Si substrate to the operating temperature (
Due to the differential shrinkage of GaAs and Si during cooling to room temperature), microcracks as shown by this reproduced photograph can occur at random locations and disrupt the operation of the device.

This problem is solved by the method of the present invention, in which the material stress is reduced and the precise location of microcracks can be controlled to prevent the occurrence of microcracks in the device. Deliberately creating microcracks. Figure 3 shows that the microcracks are created at a location outside the working device. Figure 3 shows a series of light emitting diodes 4.5 integrated on a common substrate.
．． 6 and 7 are shown schematically. Lead line numbers 8 to 13 illustrate locations where microcracks could be formed outside the device so as not to affect device operation.

In order to obtain said microcracks at a location where they cannot be detrimental to the operation of the device, the following method is followed: the silicon substrate 14 is first coated with a mask, preferably SiO, mask 15, which is similar to Si0 on the Si substrate. , (Fig. 4), and by photolithography and wet chemical etching.
This is done by removing part of the i02 layer.

Next, GaAs is deposited. FIG. 4 shows different morphologies of GaAs in different planes. 310! G attached to the top
The morphology of aAs is polycrystalline 16, and it is grown on a Si substrate (Si
n, not coated) and it is single crystalline 17.

A particular method of forming a mask according to the invention will now be described.

The masks used in the experiments described below were obtained using this particular method. The masking layer can be plasma deposited on the Si wafer using, for example, plasma enhanced chemical vapor deposition ((100)+3 DEG relative to the p-9 normal (011) direction).

According to a preferred embodiment of the invention, the wafer is coated with a 50% IF solution and deionized water DI (DI) for 15 seconds before the deposition process.
1 part/9 parts) mixture. Then the wafer
into the vacuum chamber of a PD 80 device (manufactured by Plasma Technology).

The parameters of the deposition method for depositing a layer of 100 nm at a deposition rate of 33 nm/min are as follows: Total chamber pressure: 30 Q mTorr.

Sample temperature: 300°C.

RF electric crab 25W.

RF frequency: 100 kHz Gas flow: 10 SOQm SiH4+ 120 sa
om Nto.

Time: 3 minutes.

Standard photolithography methods are used for patterning the SiO2 layer. The wafers are washed in a Soxhlet in boiling solvent (15 min trichlorethylene, 15 min
min acetone, 15 min in isopropyl alcohol). The wafer is then washed in deionized water (DI) and dried in air at a temperature of 120 DEG C. for 30 minutes. After drying, the sample is spin-coated with photoresist (3000 r
pm, 40 seconds). AZ1350 resist (manufactured by 5hipley) was used for these experiments.

The resist is baked in a hot plate oven at 90° C. for 5 minutes in a nitrogen atmosphere.

Next, the resist is exposed to ultraviolet light (high-pressure mercury lamp) E through a mask as shown in FIG. 7 in a mask aligner (exposure time: 34 seconds).

Develop the exposed areas (Developer: diluted AZ2401 developer (manufactured by 5hipley), dilution: 1 part AZ 240
1 and 4 parts DI, development time 30 seconds).

Using a photoresist as a mask, remove the Sin2 layer by etching (etching solution: Transene).
BHF, etching time 50 seconds).

The next step is metal organic chemical vapor deposition (Thomas Swa
This is an oriented overlapping growth of GaAs using an nEpitor O4 device).

The reactor used supplies four metal organic sources and three hydrides. Nitrogen (inert) and Pd-purified hydrogen can be selected as carrier gas by means of a bellows-sealed pneumatic valve. Each metal organic line contains a temperature controlled bath. Gas flow in each line is controlled by an MKS mass flow controller. This device has E for rapid interfacial adhesion.
A PIFOLD rapid switch gas manifold was installed.

Growth can be controlled manually or by computer. The reactor is a horizontal quartz reactor with a rectangular cross section and operated at atmospheric pressure. During growth, the substrate is placed on a square S1 susceptor, which is heated with an IR lamp (100 OW, 100 V). Temperature is measured with a thermocouple placed in the S1 susceptor and lamp power is applied continuously via a PID regulator.

Available sources are trimethylgallium (TMG), trimethylaluminum and diethylzinc for metal organics, and 5% AsH3 (arsine) in hydrogen, 2
5IH4 (silane) of 000FI@ and H of 2000F,
se (hydrogen selenide) (both diluted with hydrogen). Normal growth conditions are Tgr=660℃, growth rate=10
0 nm/min, mole fraction (TMG) = 2-10-'
The mole fraction (AsH3)=2·10-s.

Preferably includes substrate preparation for growth of GaAs on Si. The step consisted of ex 5 itu etching for 15 s in a 1=19 mixture of I (F CDI), followed by 60 s of flowing DI (18,03 MOh).
m) consisting of washing under and blowing drying under a stream of N (HF solution 249-51%).

Immediately after this etching step, the substrate is placed in a reactor. In-situ substrate preparation consists of baking at 950° C. under H2 flow for 1 hour 11/min.

After in-situ baking, the substrate was cooled to 450°C.
Increase the H2 carrier flow to 4.417 minutes. Once the temperature stabilized at 450°C, the growth atmosphere was heated to 200°C for 2 minutes.
Flush with a flow of AsH, (5% in Hf) at C/min.

Immediately thereafter, the flow to the reactor was switched to a trimethylgallium flow and a thin GaAs nucleation layer (approximately 1° nm) was deposited at 60 nm.
Let it grow for seconds. The reactor heating set point is set at 720° C. under continuous AsHg flow. After 5 minutes the temperature reading is approximately 700°C and the set point gradually decreases to 660°C (normal growth temperature). After another 5 minutes, the temperature reading stabilized at 660°C and reached the desired GaAs/Al! Growth of the GaAs structure begins.

Deposits on the quartz reactor must be removed after each growth run of GaAs on Si. To prevent the desorption of this adhesion, in-situ baking for the substrate preparation of the second growth implementation of GaAs on Si is carried out at a high temperature (950 °C) characterized by an overpressure of AsH3. , AsH, rapidly decomposes at the exit of the reactor, saturating the dust filter and ultimately causing a pressure increase in the growth atmosphere.

After each growth run, the quartz reactor is removed from the apparatus and replaced with a clean quartz reactor. The first reactor and susceptor are then etched with aqua regia and washed in effluent DI and inpropyl alcohol. After baking at 100° C. for several hours in a vacuum oven, the reactor-susceptor combination is replaced in the system and the H? Heat to 850°C under a stream of water. This etched reactor is used for the next growth run of GaAs on Si.

Intentionally creating micro-cracks at specific locations (if no device is present), S10. The topography of the mask is of particular importance.

For this purpose, the SiO2 mask comprises at least one vertex oriented towards the cleavage direction of the GaAs crystal (i.e. Co 1 1] or (0111 direction). In a particular embodiment, said vertex is symmetrically related to this direction. be.

An example of such a mask is shown in FIG. The hidden line part is sio□
Represents a substrate covered with a mask. The working device can be created within the confines of the Si02 mask on the uncoated substrate (also referred to as the window).

Sin, the vertices in the mask (designated e.g. 18 and 19) are in the crystal cleavage direction, i.e. (:0 1 11 or C
o 1 13 Directed in direction lζ.

As a result of the vertices in the mask, microcracks appear in the GaAs layer deposited in the gates in the mask. These microcracks extend in the direction of crystal cleavage (indicated by dotted lines in Figure 5). On the one hand, microcracks reduce the material stress and do not affect the device operation, since their location is well known and these microcracks can be engineered to be located outside the device action area. It is.

FIG. 5 shows one possible mask topography. Other arrangements are possible and other examples are shown in FIGS. 7 and 8. It will be clear that at least one vertex oriented in the direction of crystal cleavage is necessary to obtain the microcracks induced according to the invention.

FIG. 6 is a reproduction photograph showing a Si substrate partially covered by a 5-inch mask 20. FIG. Microcracks extend from one vertex to the opposite vertex. The microcracks extend in the direction of crystal cleavage. Microcracks (very thin vertical lines on the reproduction photograph) are indicated, for example, by the numbers 21 and 22.

7 and 8 show another type of mask, the dimensions are given in micrometers. Figures 7a, b and c show masks in which the vertices have the same shape and the same direction, with only the width of the opening (or window) in the mask varying.

This mask also allows us to study the effects of different vertex spacings.

The distance between the vertices varies between 50 and 500 μm, and the window width varies between 100 and 500 μm.

FIGS. 7-41 and 8-e show masks in which the vertices are located on different sides (vertical sides as well as opposite sides) of the windows in the mask. In Figure 8e, the shape of the vertex has also changed.

1 and k in FIG. 8 show a mask with vertices on one side, the vertices being equally spaced. 1 in FIG. 8, the shapes of the vertices are not the same.

FIG. 8 g-j shows a mask in which the arrangement of several vertices is formed in the central part of the opening in the mask (cross-shaped, linear, summer-shaped).

FIG. 9 is an enlarged view of different shapes of vertices. The angle is about 20°
The angle varies from 60° to 60°. Other shapes of vertices are also shown.

The results of experiments on crack formation are shown in reproduction photographs 10-13.

In continuous growth experiments, different thicknesses of GaAs layers were deposited on a p-Si substrate using a mask defined by a 100 nm thick SiO2 layer.

After cooling the substrate from the growth temperature to room temperature and removing it, crack formation was studied by Nomarski interference microscopy. The cracks can be seen as very fine lines in the single crystalline zone.

The growth structures were immersed in liquid nitrogen (77K) for 30 seconds to also observe the resulting growth of crack formation due to thermal strain at these low temperatures. The crack is H, So, : H, O, :H! It is well revealed by very short etching in an O mixture.

The dimensions in the photographic reproduction correspond to the dimensions shown in the shape of the mask in FIGS. 7 and 8.

Reproduction 10 shows a 6 μm thick GaAs substrate (substructure). The masks used are shown in FIG. 8k and FIG. 81. Crack formation starts from the apex and continues in the cleavage direction. No cracks that do not start from the apex (start spontaneously) are found.

Reproduction 11 shows another 6 μm thick GaAs structure.

The mask used is shown in Figure 8f. Cracks originating from vertices located on the same or parallel sides of the mask run parallel, while cracks originating from vertices on vertical sides are mutually perpendicular.

A slight contact misorientation of about 3° can be seen between the crack and the mask edge. This result from misorientation of the rectangular S1 sample was induced during cutting. As a result, cracks induced from vertices located on opposite sides of the substrate do not coalesce into each other.

Reproduction 12 shows a crack formed on a 3 μm thick GaAs structure, while reproduction 13 shows a crack formed on a 6 μm thick structure. The same mask topography (see Figure 8e) was used for both structures. The crack exhibits the same behavior as described above.

However, the number of cracks across the entire single crystalline region is
It is larger in a 6 μm thick structure than in a 3 μm thick structure.

Since the mask of FIG. 8 is used to obtain the results of reproductions 12 and 13, the influence of the shape of the vertices can also be studied in these reproductions.

In these growth experiments, it is established that there is no consistent relationship between apex shape and resulting crack formation. Experiments also show that there is no special relationship between vertex spacing and microcrystal formation. Experiments using the mask of FIG. 8g+1 teach that mask sharp angles in the center of the growth zone also induce cracks in the oriented overlapping growth layer (not pictured). Masks in Figure 8 g+1 and J induce microcracks in two vertical directions, while according to the mask in Figure 8, microcracks are induced only in one valve opening direction (microcracks originate from acute angle points). do). In the experiment, S
It has been shown that microcracks can be introduced into the GaAs layer on the i-substrate. Microcracks originate from the apex in the mask and are not visible at other locations. The distance of lateral opening does not show a significant effect. The generation of microcracks is insensitive to the shape of the apex, and the use of vertical strokes produces vertical microcracks. Variations in layer thickness affect the density of microcracks. Cross, line, and diamond formations in the center of the mask window can also generate microcracks.

[Brief explanation of drawings]

Figure 1 shows GaAs/klGa integrated on a Si substrate.
As light emitting diode and field effect transistor (MOS)
FET ) topography is shown. Figure 2 is a reproduction photograph showing naturally occurring microcracks. FIG. 3 schematically illustrates the location of intentionally induced microcracks on a substrate on which electronic or optoelectronic devices are grown. Figure 4 shows S10. Use of mask and Ga on wafer
The growth of A3 is shown. FIG. 5 shows a mask that can be used to obtain induced microcracks. FIG. 6 is a reproduction photograph showing the induced microcracks. Figures 7 and 8 show different types of masks. FIG. 9 is an enlarged view of vertices of different shapes. Figures 10-13 show the results of experiments conducted on crack formation. 1... Silicon substrate, 2... Field effect transistor,
3... Light emitting diode, 4, 5, 6 and 7... Light emitting diode, 8-13... Position where micro cracks can be formed, 14... Silicon substrate, 15... sio, mask,
16...Polycrystalline adhesion 5in2.17...Single crystal SiO2.18.19...Vertex. Engraving of the drawings (no changes to the contents) Fig. 1,, J,: Sshi (') Kamijiro Fig. - Fig. 'ji-,, 6 + Fig. 7 Fig. Fig. - Theft Fig. Fig. 12

Claims (1)

[Claims] 1. In a method for forming microcracks at predetermined positions during growth of a GaAs layer on a Si substrate, the Si substrate is partially covered with a mask before the growth of the GaAs layer. . A method characterized in that the coating has at least one vertex extending in or approximately in the crystal cleavage direction of the GaAs layer. 2. In a method of forming an integrated electronic device or a component thereof by forming GaAs on a Si substrate at a constant temperature and subsequently cooling the substrate, microcracks are created at locations that do not interfere with the operation of the device or component. A method characterized in that the induction is carried out in the GaAs layer. 3. Before the growth of GaAs, the Si substrate is partially covered with a mask, and the mask is set to have at least one vertex extending substantially in the cleavage direction of the crystal of the GaAs layer. Method. 4. The method of claim 1 or 3, wherein the setting mask is obtained by depositing SiO_2 on the Si substrate, followed by photolithography and wet chemical etching. 5. The method of claim 4, wherein the SiO_2 deposit is formed on the Si substrate by plasma enhanced chemical vapor deposition. 6. The method according to claim 1 or any one of claims 3 to 5, wherein the substrate is cleaned by HF:DI cleaning before forming the mask. 7. The method according to any one of claims 1 to 6, wherein the GaAs is deposited by metal organic chemical vapor deposition. 8. The method of claim 7, wherein the substrate is cleaned by an HF:DI wash prior to depositing the GaAs. 9. The method according to claim 1 or any one of claims 3 to 8, wherein the apex is provided on the opening side in the mask to which GaAs is deposited. 10. A method according to claim 1 or any one of claims 3 to 9, characterized in that the opening in the mask in which GaAs is deposited is provided with a second mask arrangement having at least one vertex oriented approximately in the direction of cleavage of the GaAs crystal.