JPH0311222B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a device that generates a heartbeat sound synchronized with the heartbeat cycle and further changes the generation cycle of the heartbeat sound over time.

(Prior Art) Conventionally, as described in Japanese Patent Application Laid-Open No. 54-98651, a pulse wave, that is, a heartbeat is detected by a pulse wave detection device, and a heartbeat sound corresponding to this detection signal is generated. Measuring devices are known.

By the way, the heart rate under normal conditions is 70-80 beats per minute.
It is known that this number decreases to about 50 to 60 times per minute during sleep or in a relaxed state of mind, and increases to about 90 to 100 times per minute when excited or mentally tense. It is said that it is possible to control one's own heartbeat and mental state by concentrating on a certain sound.

(Objective of the Invention) The present invention is a further development of the conventional heart rate measuring device described above, and its purpose is to provide a device that can easily control the mental state of the user.

(Structure of the Invention) In order to achieve the above object, the present invention is characterized in that after a heartbeat sound synchronized with the heartbeat cycle is generated, the generation cycle of the heartbeat sound is changed over time.

(Embodiments) Preferred embodiments of the present invention will be described below based on the drawings. FIG. 1 shows an embodiment in which a heartbeat sound generating device according to the present invention is combined with a watch with an alarm function.

The oscillation circuit 2, the frequency dividing circuit 4, the waveform shaping circuit 6, the motor 8, the wheel train 10, and the pointer display 12 constitute a conventionally well-known analog timepiece. The reference mechanism 14 is built into the wheel train 10, and supplies the AND gate 16 with an alarm start signal that remains "H" for about 20 minutes when the set time arrives. The AND gate 16 is also supplied with the output of a ring stop switch 18, and when an alarm start signal is generated when the switch 18 is closed, a heartbeat signal is supplied to the sound generation circuit 19 from a heartbeat signal generation circuit 70, which will be described later.
The sound generation circuit 19 is a circuit that converts a heartbeat signal into a heartbeat sound.

The heartbeat detection unit 20 is a device that detects a heartbeat and outputs a detection signal as shown in FIG. When applied to a fingertip, a phototransistor detects reflected and transmitted light whose intensity is modulated by blood flow. The output a of the heartbeat detection section 20 is supplied to a waveform shaping circuit 22, and the supplied detection signal is shaped into a square wave with a constant pulse width and outputted as an output b.

The heart rate storage circuit 24 is a circuit that counts the detection signal from the heartbeat detection section 20 for a certain period of time, one minute in this case, and stores the count value. The detection signal via the waveform shaping circuit 22 is supplied to a counter 28 via an AND gate 26, and when the AND gate 26 is open, the detection signal, that is, the heart rate is counted by the counter 28. The output G of a flip-flop (hereinafter referred to as FF) 30 is supplied to the other input terminal of the AND gate 26, and when the output G is "H", the AND gate 26 is in an open state. Note that the output G is also supplied to the heartbeat detection section 20, and the detection operation of the heartbeat detection section 20 is enabled only when the output G is "H". Further, the output H of the FF 30 is supplied to the reset terminal R of the counter 28. The set terminal S of the FF 30 is supplied with an output D of an OR gate 54 in an operation control circuit 48, which will be described later, and the reset terminal R is supplied with a timer circuit 5.
6 is supplied via a delay circuit 32. Further, the latch circuit 34 is supplied with the count value of the counter 28, and stores the count value when a single pulse is outputted to the output E of the timer circuit 56.

The counting circuit 36 is a circuit that performs a counting operation of a constant periodic signal after the heart rate storage circuit 24 finishes counting operation. The counter 38 counts the clock signal supplied from the AND gate 40, and the output I of the FF 44 is supplied to the AND gate 40 together with the clock signal selected by the switching gate 42. The switching gate 42 includes a frequency dividing circuit 4 that further divides the 1Hz signal of the frequency dividing circuit 4.
6 clock signal φ ₁ (1/2Hz) and clock signal φ ₂
(1/30Hz) and output B is supplied to the switching control terminal.
is supplied. Then, if the output B is "H", the clock signal φ ₁ is selectively output, and if the output B is "L", the clock signal φ ₂ is selectively output.

The operation control circuit 48 is a circuit that outputs a control signal for controlling the operations of the heart rate storage circuit 24 and the counting circuit 36. One shot circuit 5
The single pulses generated from 0 and 52 are both supplied to the OR gate 54, and the single pulse generated at the output D of the OR gate 54 is applied to the set terminal S of FF30 as a control signal to start counting the heart rate. Supplied. Further, the single pulse generated at the output D starts the operation of the timer circuit 56,
After one minute has elapsed, output E generates a single pulse again. This single pulse generated at the output E is used to store the count value of the counter 28 in the latch circuit 34 as described above, to terminate the counting of the heart rate, and to start the counting operation in the counting circuit 36. Latch circuit 3 as control signal
4, the delay circuit 32, and the set terminal S of the FF 44. The one-shot circuit 50 is supplied with an output A, and the one-shot circuit 52 is supplied with an output B.

Further, the output A is inverted and supplied to the OR gate 58, and the output C of the OR gate 58 is supplied to the reset terminal R of the counter 38 as a control signal for resetting the counter 38. The output L of a timer circuit 60, which will be described later, is also supplied to this OR gate 58.

Furthermore, the comparison circuit 62 is a circuit that compares an output signal from an arithmetic circuit 68, which will be described later, and a code signal from the encoder 64. When the output B is "H", the value of the code signal from the encoder 64 is compared to the arithmetic circuit 68. A single pulse is generated at output K when the value of the output signal from B becomes large, and conversely, when the output B becomes small, a single pulse is generated at output K. In this embodiment, the code signal of the encoder 64 is set to be "80" if the output B is "H" and "50" if the output B is "L". The single pulse generated at the output K is supplied to the reset terminal R of the FF 44 as a control signal for stopping the counting operation of the counting circuit 36. Further, the output K is supplied to the other input terminal of the AND gate 66, which is an inverted version of the output B, and when the output B is "L", the single pulse generated at the output K is used to control the timer circuit 60. is operated, and a single pulse is generated at the output L after one minute has elapsed.

The arithmetic circuit 68 is a circuit that can add and subtract the heart rate stored in the heart rate storage circuit 24 and the count value of the count circuit 36, and if the output B is "H", it adds the heart rate and the count value. And the output B is
If "L", the count value is subtracted from the heart rate.
The calculation output of the calculation circuit 68 is supplied as a period setting signal to the comparison circuit 62 and the frequency division ratio converter 72 in the heartbeat signal generation circuit 70.

The heartbeat signal generation circuit 70 is a circuit that generates a heartbeat signal for generating a heartbeat sound with a period corresponding to the calculation output of the calculation circuit 68. The programmable counter 74 composed of 8 bits and the frequency dividing circuit 76 composed of 8 stages divide the clock signal φ ₃ (32768Hz) from the frequency dividing circuit 4, and the frequency division ratio of the programmable counter 74 is as follows. Division ratio converter 7
The output of the lower 4 bits of the frequency divider circuit 76 is set by the frequency division ratio setting signal from the AND gate 7.
8. The frequency division ratio converter 72 converts the period setting signal into a frequency division ratio setting signal for setting the frequency division ratio necessary for counting the period corresponding to the period setting signal. The relationship is expressed by the following relationship. In other words, if the value of the period setting signal is N1 and the value of the division ratio setting signal is N2, then
It is approximately expressed by the relationship N2 = 32768Hz/256÷N1/60sec. This frequency dividing ratio setting signal is transmitted to the programmable counter 7 every 4 seconds by the clock signal φ ₄ (1/4Hz) from the frequency dividing circuit 46.
Preset to 4. The above clock signal _φ3 ,
_φ4 is supplied to the clock input terminal _φ1 preset terminal PE via AND gates 80 and 82, respectively.
The output J of the FF 84 is also supplied to the AND gates 80 and 82. Further, the output E is supplied to the set terminal S of the FF 84, and the output C is supplied to the reset terminal R.

On the other hand, a pulse signal with a duty ratio of 1/16 corresponding to the period setting signal is generated at the output M of the AND gate 78, and this output M is further supplied to the AND gate 86. The AND gate 86 is also supplied with an audible frequency signal φ ₅ (for example, 2048 Hz) from the frequency dividing circuit 4, and supplies an output N from which a heartbeat signal is generated to the sound generation circuit 19.

This embodiment is constructed as described above, and the operation of this embodiment will be explained below using the time chart shown in FIG.

At time _t1 , when the ring stop switch 18 is closed, the output C becomes "L", so the counter 38 and
The reset of FF84 is released. At the same time, a single pulse from the one-shot circuit 50 is generated at the output D, FF30 is set, and the output G becomes "H".
At the same time, the output H is inverted to "L" and the timer circuit 56 starts operating. Therefore, heartbeat detection section 2
0 detection operation is started, and the counter 28 counts the detection signal via the waveform shaping circuit 22.

Then, at time t ₂ , one minute after time t ₁ , a single pulse from the timer circuit 56 is generated at the output E, so the latch circuit 34 stores the count value of the counter 28, that is, the heart rate per minute. Then, the FF 30 is reset via the delay circuit 32, and the output G is inverted to "L" and the output H to "H". Therefore, the detection operation of the heartbeat detecting section 20 is stopped and the counter 28 is reset. At time _t2 , the single pulse generated at the output E sets the FF 44 to start the operation of the counting circuit 36, and also sets the FF 84 to start the operation of the heartbeat signal generation circuit 70. That is, in the count circuit 36, the output I is inverted to "H", allowing the counter 38 to perform a counting operation, and since the output B is "L" at this time, the clock signal _φ2 is counted. Therefore, the count value of the counter 38 is added at a rate of 1 every 30 seconds. On the other hand, in the heartbeat signal generation circuit 70, the output J is inverted to "H" and the programmable counter 74 is operated. At time _t2 , the count value of the counter 38 is "0", so the heart rate (for example, "70") stored in the latch circuit 34 is directly supplied to the frequency division ratio converter 72 as a period setting signal. Therefore, the programmable counter 74 is preset with a division ratio of "110".
As a result, a pulse signal with a period of approximately 0.86 seconds is generated at the output M. As a result, a heartbeat signal is similarly generated at the output N at a period of 0.86 seconds, and this is converted into a heartbeat sound by the sound generation circuit 19.

By the way, since the output B is "L", the arithmetic circuit 68 calculates the counter 38 from the heart rate of the latch circuit 34.
It is understood that the period setting signal and the frequency division ratio setting signal become smaller every 30 seconds. Furthermore, since the programmable counter 74 performs a preset operation every 4 seconds, if the division ratio setting signal becomes small, the output M
The generation cycle of the pulse signal that is generated becomes longer, and the generation cycle of the heartbeat sound also becomes longer. For example, after 5 minutes have elapsed from time _t2 , the count value of the counter 38 is "10", the period setting signal is "60", and the frequency division ratio setting signal is "128", which is generated at the output M. The period of the pulse signal is 1 second, and similarly the period of generation of the heartbeat sound is also 1 second. It will be understood that the generation cycle of the heartbeat sound gradually becomes longer in the same way.

Then, at time _t3 , when the cycle setting signal becomes smaller than "50" as the signal from the encoder 64, here the output B is "L", a single pulse is generated at the output K, the FF 44 is reset, and the output I
is inverted to "L", so the counting operation of the counter 38 is stopped. At the same time, and gate 66
Since the timer circuit 60 is in an open state, the operation of the timer circuit 60 is started, and a heartbeat sound is generated at the same period while the timer circuit 60 is operating. and time t ₃
At time _t4 , one minute has passed since then, a single pulse from the timer circuit 60 generated at the output L is generated at the output C, and the FF 84 is reset and the operation of the heartbeat signal generation circuit 70 is stopped, so that the heartbeat sound is no longer heard. Occurrence is also stopped. At the same time, the count value of the counter 38 is also cleared.

On the other hand, when the set time arrives at time _t5 , the output B becomes "H" due to the alarm start signal from the reference mechanism 14, and the output D is connected to the one-shot circuit 5.
A single pulse from 2 is generated. Therefore, like the operation from time t ₁ to time t ₂ , the number of heartbeats per minute is counted and stored in the latch circuit 34 . Then, at time _t6 , the single pulse generated at output E causes the counting circuit 36 and heartbeat signal generation circuit 70 to start operating in the same manner as at time _t2 . If the heart rate stored in the latch circuit 34 is, for example, "50", the division ratio setting signal becomes "154" at time _t6 , so the output M receives a pulse signal with a period of about 1.2 seconds. Occur. At this time, since the output B is "H", the clock signal φ ₁ is supplied to the counter 38, and the arithmetic circuit 68 adds the heart rate stored in the latch circuit 34 and the count value of the counter 38. act. Therefore, since the count value of the counter 38 is added at a rate of 1 every 2 seconds,
It is understood that the period setting signal and the frequency division ratio setting signal increase every two seconds. Since the programmable counter 74 performs a preset operation every 4 seconds, as the frequency division ratio setting signal increases, the generation cycle of the pulse signal and heartbeat sound generated at the output M becomes shorter. For example, after 30 seconds have elapsed from time t ₆ , the count value of the counter 38 is "15", the period setting signal is "65", and the frequency division ratio setting signal is "118", which is generated at the output M. The period of the pulse signal is approximately 0.92 seconds, and similarly the period of generation of the heartbeat sound is approximately 0.92 seconds. It will be understood that the generation cycle of the heartbeat sound gradually becomes shorter in the same way.

Then, at time _t7 , when the period setting signal becomes greater than "80" from the encoder 64, here since the output B is "H", a single pulse is generated at the output K, the FF 44 is reset, and the output I
is inverted to "L", so the counting operation of the counter 38 is stopped. Therefore, since the cycle setting signal does not change thereafter, the generation cycle of the heartbeat sound is also kept constant. Then, at time _t8 , when the ring stop switch 18 is opened, the output C becomes "H", the FF 84 is reset, and the operation of the heartbeat signal generation circuit 70 is stopped, so that the generation of the heartbeat sound is also stopped. At the same time, the counter 38 is also reset. .

As described above, according to this embodiment, the heartbeat sound generating device according to the present invention is combined with a watch with an alarm function, and after setting the alarm, a heartbeat sound synchronized with the heartbeat cycle is generated, and then a heartbeat sound is generated every 30 seconds. By lengthening the period of occurrence of , the heart rate of the user gradually decreases and acts to relax the user's mental state, thereby inducing a comfortable sleepiness in the user. In addition, when the set time arrives, a heartbeat sound synchronized with the heartbeat cycle is generated, and then the heartbeat sound generation cycle is shortened every 4 seconds to gradually increase the user's heartbeat and bring the user's mental state back to normal. Since it acts to make you feel comfortable, it can induce a comfortable awakening.

In addition, in the heartbeat sound generating device according to the present invention, an external switch can be provided in place of the ring stop switch 18 so that the sound can be operated independently, and a changeover switch can also be provided and the generation cycle can be lengthened by the changeover signal of the switch. It is also possible to switch between short and short.

(Effects of the Invention) As described above, according to the present invention, an alarm sound synchronized with the heartbeat cycle is generated, and the generation cycle of the alarm sound is changed over time, thereby improving the mental state. It is possible to gradually relax, tense, or return to a normal state, allowing the user's mental state to be easily controlled.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a timepiece with an alarm function to which a heartbeat sound generator according to the present invention is applied. 2 and 3 are time charts showing the operation of FIG. 1. 14...Guide mechanism, 16...And gate, 1
8...Sound stop switch, 19...Sound generation circuit, 20
... Heart rate detection unit, 24 ... Heart rate storage circuit, 36
... Count circuit, 48 ... Operation control circuit, 68
... Arithmetic circuit, 70 ... Heartbeat signal generation circuit.

Claims (1)

[Scope of Claims] 1. A heartbeat sound generating device comprising: a heartbeat detection section that detects a heartbeat and outputs a detection signal thereof; and a sound generation circuit that converts the detection signal into a sound as a heartbeat signal; inputs an external signal, outputs an operation start signal in response to input of a first external signal or inputs a second external signal when the first external signal is input, and responds to the second external signal; The upper or lower limit of the heart rate per predetermined time set in advance is varied, and the operation is terminated when the heart rate per predetermined time of the heartbeat signal becomes larger or smaller than the upper or lower limit set value. an operation control circuit that outputs a signal; a heart rate storage circuit that counts the detection signal for a certain period of time after receiving the operation start signal and stores it as an initial heart rate; a counting circuit that counts a reference signal until an operation end signal is generated; an arithmetic circuit that adds or subtracts the initial heart rate and the count value of the counting circuit at regular intervals in response to the second external signal; A heartbeat sound generation device comprising: a heartbeat signal generation circuit that outputs a heartbeat signal having a period corresponding to the heartbeat rate per predetermined time calculated by the calculation circuit to the sound generation circuit.