JPH03111978A - Parallel picture processor - Google Patents

Abstract

PURPOSE:To cope with various picture processing procedures by providing a look-up table (LUT) means to logically couple a picture storing means with a parallel arithmetic means and a means to change the coupled state of these means. CONSTITUTION:According to a control signal 34, a CPU 30 switches arithmetic address selectors 13, 14 and 15 to the CPU 30 side and sets arithmetic contents to be processed to arithmetic LUT 16, 17 and 18. Coupling information area set to an input LUT 4 and an output LUT 20 and a reference memory data selector 21, reference memory address selectors 26 and 27 and reference memory control signal selectors 28 and 29 are switched to the CPU 30 side. Then, the picture data to be processed are transferred from a storage device 35 to the 0-th bit of data in a reference memory 1. In a state that the picture data are set to the referring memory 1, an arithmetic control circuit 22 is driven and a parallel arithmetic processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a parallel image processing device, and more specifically, a parallel image processing device that has a plurality of parallel arithmetic circuits and can change the connection state between them. It is related to.

[Prior art 1] Conventionally, as a technology for performing high-speed image processing, there has been a device in which multiple locally parallel image processing circuits, each with a single function, are connected in a pipeline configuration and these parallel processing circuits operate simultaneously. Ta.

[Problem to be solved by the invention 1 However, since the actual image processing procedures are diverse, in order to realize various functions, the connections between each locally parallel arithmetic circuit must be changed to 7 flexibilities, or multiple connections can be made. Despite the need for processing to combine the output results of two arithmetic circuits, no method of coupling such arithmetic circuits has been proposed in the past.

The present invention has been made to solve the above-mentioned problems, and includes installing a look-up table memory at the input or output section of a plurality of locally parallel image processing circuits, thereby creating a logical connection between the processing circuits. The object of the present invention is to provide a parallel image processing VC system that can accommodate various image processing procedures by flexibly changing the image processing system.

[Means for Solving the Problems 1 To achieve this object, the parallel image processing device of the present invention, as shown in FIG. An operation that performs arithmetic processing based on the image data obtained! Parallel image processing V, comprising: a parallel calculation means having a parallel calculation unit; and a transfer control means for controlling image data transfer between the storage means and the parallel calculation means.
cF:n, the image storage means and n? A looker/button that performs logical combinations among f parallel calculation methods.
The present invention is characterized by comprising a pull means and a look-up table changing means for changing the connection state of the look-up table means.

[Operation 1] The look-up table means of the present invention having the above-described configuration performs a series of parallel arithmetic processing procedures through logical connection using table references between a plurality of liquid circuits and an image storage circuit. The parallel calculation processing procedure is changed by the lookup table changing means changing the reference table of the lookup table means.

[Embodiment] Hereinafter, an embodiment in which the present invention is made into a weapon will be described with reference to the drawings. First, the configuration of the 4F row image processing device will be explained with reference to FIG. The reference memory 1 and the reference memory 2 are each a random access memory with 18 bits and 7 address inputs, and their output data is connected to each other with their respective bit numbers and is sent to the address input section of the input LtJT4 through the input LUT address selector 3. It is connected. The input U T 4 is a look-up table random access memory with an address of 8 bits/bit, an input of 8 bits, and an output of 3 bits. It is connected to the other channel 12 through the register 7, the shift register 7, the shift register 10, and the latch 11 through the latch 9, shift register 7, shift register 10, and latch 11. The input of the launch 5.6 and the output of the latch 6, the input of the latch 8.9 and the output of the latch 9, each having a width of 3 pints,
The input of bit/chie 1.12 and the output of latch 12 are the 0th bit/g, f51 bit, and 2nd bit 7 of those signal lines.
The outputs of F are respectively calculated by the LUT address selector 13.
It is connected to the address input section of calculation LUT1G and 17.18 through 14.15. Operation +-U TlG, 1
7.18 are look-up table random access memories each having 9 bits of address, 1 bit of input, and 1 pin of output, and their outputs are connected to the address input part of the output LUT 20 through the output LUT address selector 19. 1, output, UT 20 is,
It is a look 77 buttable program access memory with 3 bits of address, 8 bits of input and 8 bits of output, the output of which is connected through the reference memory data selector 21 to the data input section of the reference memory 1.2.

The arithmetic control circuit 22 that controls the parallel arithmetic circuit described above includes a timing generation circuit 23, an address generation circuit 24 that independently generates the 18-bit address of the reference memory 1.2,
The reference memory control circuit 25 generates control signals for the reference memory 1.2. The address signals for the reference memory 1.2 generated by the address generation circuit 24 are connected to the address inputs of the reference memories 1 and 2 through reference memory address selectors 26, 27, respectively. Shift register 7.10, latch 5.6.8.9
．． 11 and 12, a shift operation and a launch operation are performed in synchronization with the tri signal generated by the timing generation circuit 23, respectively. The control signals generated by the reference memory control circuit 25 are applied to the control signal input sections of the reference memories 1 and 2 through reference memory control circuit signal selectors 28 and 29, respectively.

Setting of various data and various selectors to the above-mentioned parallel processing circuit is performed by the CPU 30. In the address output signal 31 of the CPU 30, an address corresponding to 18 bits and γF from the least significant bit is outputted through the input LUT address selector 3 to the address input section of the input LtJT4, and similarly, an address corresponding to 3 bits is outputted through one output LUT address selector. Similarly, the 9-bit address is calculated into the address input section of LUT20 by LUT address selector 13.14.1
5 to calculation LUTs 1G and 17.18, respectively, and similarly, 18-bit addresses are sent to reference memory 1.2 through reference memory address selectors 26.27, respectively.
connected to the address input of the The data signal 32 of the CPU 30 includes 8 bits of data from the least significant bit to the data input part of the input LUT 4, 8 bits of data to the data input part of the output LUT 20, and 0 bits, 1 bit, and 2 bits to the data input part of the output LUT 20. Each bit data is 3LU
T1. G, 17. It is connected to the data input section of 18. The 8-bit output of the reference memory 1.2 is connected to the lowest 8-bit data signal 32 of the CPLI 30 through a date circuit 33.

The control signal 34 of the CPU 30 is connected to the switching inputs of the various address selectors mentioned above, the enable input of the date circuit 31, the input/output control inputs of various memories, and the arithmetic control circuit 22, thereby controlling the parallel arithmetic circuit. Operation settings are made.

- The operation of the CPU 30 is controlled by a program stored in a storage device 35 attached to the CPU 30.

As shown in FIG. 3 (,), the head reference memory 1.2 is
The image memory of 512 pixels in the direction and 512 pixels in the y direction is
The pixels 100, 101, and 102 are arranged in the right direction from the lower left end pixel, that is, in the
, 101' and 102'. Further, following the memory address 103' corresponding to the rightmost pixel 103 in the X direction, the pixel 104 one level above the pixel 100, that is, the pixel 104 moved by one in the X direction, is located at the memory address 104' next to the memory address 103'. is associated with.

The input LUT 4 and the output LUT 20 respectively map input 8-bit and 3-bit address bit information to 8-bit memory data information and output this data information, thereby changing the bits between the input and output. Perform the join.

The latch 5.6.8.9.11.12 Shift Reno Stuff 10 simultaneously calculates neighboring pixel data consisting of 3×3 pixels on the image memory L U T16.17.18
In the neighboring pixel detection circuit 36 configured to provide data to the address input part of A 512-stage pixel data shifter detects data for r three consecutive pixels in the X direction.

The O-bit, 1st-bit, and 2nd-bit data of the 3×3 pixels and 3-bit pixel data detected by the neighboring pixel detection circuit 36 are input as addresses to the calculation LtJT16.17.18, and the data are input to the addresses. The 1-bit data written in advance is output as the result of the 3×3 pixel neighborhood calculation.

Next, as an example of the operation of the parallel image processing apparatus having the above-described configuration, a case will be described in which dilation and contour extraction processing and contraction and contour extraction processing of a binary image as shown in FIG. 4 are performed.

First, the CPU 30 switches the calculation address selector 13.14.15 to the CPU side using the control signal 34, and sets the neighboring calculation result to be processed in the calculation fr, LUT 16.17.18. For example, when setting expansion processing to the calculation LUT 16, the CPU 30 switches the calculation WLUT address selector 13 to the CP tJ address side, and all of the address input bits of the calculation LUT 16 are set to 0.
If the level is 0, this is done by writing data 1 to the other addresses. Similarly, operation L
Contraction processing and calculation 1 are sent to UT17, and contour extraction processing is sent to UT18.

Next, combination information is set in the input LUT 4 and the output LUT 20. For example, if you want to combine bit 1 of the input bit with bit 2 of the output bin in U T 4, input bit O of the input address while changing input address bits P12 to O7 to all logic states.
This is done by writing the value to pin 2 of the memory data while keeping the value of bit 0.1 of the memory data fixed. Furthermore, in addition to the above connection, if you want to combine the input bit O of the input LUT4 and the output bit O of the input LUT4,
This is done by writing the value of input address bit 0 to pin 01 of memory data while changing the states of other input bits in the same way. Similarly for the output L U T 20, each input bit bin 0.2 is coupled to the output bit bit 1.2.

After the above settings, the reference memory data selector 21, reference memory address selector 26, 27, reference memory control (
The No. 3 selectors 28 and 29 are switched to CP tJ fllll, and the binary gradation image data to be processed is transferred from the storage device 35 to the 0th focus of the data in the reference memory 1.

With the image data stored in the reference memory 1 in this manner, the arithmetic control circuit 22 is driven to perform the parallel arithmetic processing described below.

First, under the control of the CPU 30, the input of the reference memory data selector 21 is placed on the output LUT side, the input of the reference memory address selector 26.27 and the reference memory control signal 28.2.
9 is the arithmetic control circuit side, input LUT address selector 3
input is on the reference memory side, calculation LUT address selector 1
3.14.15 input is nearby pixel detection circuit side, output L
The input of the UT address selector 20 is switched to the arithmetic LUT side, the outputs of the reference memory 2 and the date circuit 33 are set to be in the off state, and then the arithmetic control circuit 22 starts processing.

In the arithmetic control circuit 22, the address generation circuit 24 outputs the read address of the image data to the reference memory 1, and the data read from the reference memory 1 under the control of the reference memory control circuit 25 is input to the input LUT address selector 3. As a result, the bit combination is changed at U T 4 and input to the neighboring pixel detection circuit 36 . Neighboring pixel detection circuit 3
6 holds image data of 3×3 pixels of reference memory 1''2, and the data at the bit 0 position of these image data is stored in the LUT address selector 13 of the LUT and the LUT of the LUT.
It passes through the UT16 to undergo expansion calculation processing, and further passes through the output LUT address reno star 19 to output [, UT2
It is input to bit 0 of the 0 address input bits. Similarly, the data at bits 1 and 2 of the image data are subjected to shrinkage calculation and contour extraction calculation respectively by LUT 17.18, and are input to bit 1.2 of the address input of output LUT 20. These data are output LUT
The bit combination is changed in step 20, and the data is passed through the reference memory data selector 21 and written to the address of the reference memory 2 generated by the address generation circuit 24. Finally, the neighboring pixel detection circuit 36 is activated by the timing generation circuit 23.
The bird is given a signal, moves the neighboring pixel area to be detected by one pixel in the
The read address of the reference memory 2 and the write address of the reference memory 2 are both incremented by y. Here, the relationship between the addresses given to reference memory 1 and reference memory 2 is as shown in FIG.
The write address of the reference memory 2 is shifted by one line and one pixel in the ) direction, and this corresponds to the writing pixel 105' of the neighboring pixel detection circuit 3G. Can be written to pixels. By performing the above calculation over the entire reference memory, the first bit i of the data in the reference memory 2 stores an expanded image as shown in FIG. 4(a).

Next, by reversing the control of reference memories 1 and 2 and performing parallel arithmetic processing in the same manner as above, 2 of the data in reference memory 1 is
A binary image subjected to expansion processing and contour extraction is stored in the th bit.

On the other hand, as shown in PtIJ4 diagram (()), l, force 1-
[I T Output the bit 0.1 of the large cap of 4 to the bit 1.2 of the large cap of LUT 20 The focus of the large cap of LUT 20 is 1.2
By writing data into each LUT so as to connect the contours to each other, contour extraction can be performed after shrinkage processing.

The present invention is not limited to the embodiments described in detail above, and various changes can be made without departing from the spirit thereof.

For example, in this embodiment, input LUT4 and output LUT
T20 performs a connection between one large node and one output bit, but the logical inversion of one input bit is
:(Concatenate jfl into one output bit, combine multiple output nodes into one large node, or combine logical operation values between multiple input bits into one output bit. It is also possible to have a configuration in which they are matched and combined. In this case, for example, as shown in FIG.
By setting a ladder for performing a logical sum operation between a plurality of input nodes, a plurality of different arithmetic processing results can be output together as one.

Further, in this embodiment, a look-up table is used as the neighborhood arithmetic circuit, but a logic arithmetic circuit may be used. In addition, input of image data to be processed to the input reference memory and processing Fl! from the output reference memory are also performed. It may also be configured as a pipeline arithmetic circuit that performs subsequent extraction of image data in synchronization with parallel arithmetic processing. Mako,
A multi-gradation arithmetic circuit may be used as the neighborhood arithmetic circuit, and the multi-gradation bit combination may be changed as an input/output amplifier table. Furthermore, it is also possible to use neighboring arithmetic circuits with various gradations, and to combine the different gradations using an input/output lookup table.6 In this embodiment, an input/output lookup table for the parallel arithmetic circuit is installed. However, it is also possible to install it only on either the input or the output.

Note that the input and output images in the -luck parallel calculation process do not need to be Memo+7 as in this embodiment, but can be input/output devices in real time, such as a digital camera for image input and a D/D camera for image output. It is also possible to configure a device that performs A conversion and displays the data.

[Advantageous Effects of the Invention 1] As is clear from the above detailed description, the present invention has a configuration in which the logical connections between each arithmetic circuit can be changed by using a lookup table in the input/output section of a plurality of arithmetic circuits. Because of this, you can easily and flexibly change the combination.
Being able to easily adapt to various image processing procedures has a significant effect.

[Brief explanation of drawings]

1 to 155 show embodiments embodying the present invention, FIG. 1 is a block diagram illustrating the basic configuration of the rejection image processing apparatus of the present invention, and FIG. , is a block diagram showing the <+M configuration of the line rejection image processing device to which this embodiment is applied, fjrJ3 diagram (,) is a pixel configuration diagram of the image memory, and Pt53 diagram (b) is a pixel address diagram of the image memory. FIG. 4(a) is a block diagram showing an embodiment for performing dilation and contour extraction processing, and FIG. 14(b) is a layout diagram.
5 is a block diagram showing an embodiment for performing shrinkage and contour extraction processing, FIG. FIG. 6 is a block diagram showing an embodiment in which the output L UT performs logical operations. 51... Image storage means, 52... Parallel calculation means, 53
. . . Transfer control means, 54 . . . Look amplifier table means, 55 .
. . . Image input means, 57 . . . Image output means.

Claims (1)

[Scope of Claims] 1. An image storage means 51 for storing image data, a parallel calculation means 52 having a plurality of arithmetic units that perform calculation processing based on the image data stored in the image storage means, the storage means and the A parallel image processing device comprising: transfer control means 53 for controlling image data transfer to and from parallel calculation means; lookup table means 54 for performing logical connection between the image storage means and the parallel calculation means; A parallel image processing device comprising: and lookup table changing means 55 for changing the connection state of the lookup table means. 2. Parallel image processing according to claim 1, further comprising an image input means 56 for inputting image data to at least one of the lookup table means 54 and the parallel calculation means 52 in real time. Device. 3. Parallel image processing according to claim 1, further comprising image output means 57 for outputting image data from at least one of the lookup table means 54 and the parallel calculation means 52 in real time. Device.