JPH03109763A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable leak current of a power supply to be evaluated easily with a few additions of hardware by providing a means for setting a signal line to be precharged at a ground potential or a power supply potential. CONSTITUTION:The title item has discharge circuits 101-103 and a signal is set to a ground potential when a test signal is valid and a precharge signal is invalid, or it is set to a power supply potential when the test signal is valid or the precharge signal is valid. Thus, the precharged signal line cannot be set to be in a high-impedance state at any timing, thus preventing pass-through current from occurring on a receiving side while being still. Since this setting is possible by the use of one p-type MNOS transistor or one n-type MOS transistor for each signal line, no test vector needs to be generated for setting a large- scale inner state, thus enabling a power supply leak current which is caused by the production process to be evaluated easily.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides a complementary MOSFET that facilitates the evaluation of power supply leakage current.
8 (CMO3) Regarding semiconductor integrated circuit devices, conventional technology Even if a dynamic circuit using precharge is used in the parts of a semiconductor integrated circuit device that require high-speed operation, for example These include memories, adder carry propagation circuits, etc. Fig. 3 shows a block diagram of a conventional semiconductor integrated circuit device using a dynamic circuit.According to an external clock input 300, a clock generation circuit generates an internal clock P H1. (301) and P
H2 (302) is generated, 303 is an on-chip memory, 304 is a first module L/ that performs data processing,
305 stores data from another module externally or internally into the on-chip memory 303 or the first module 304.
This is the second module that outputs to. The data to be processed in the first module 304 (as supplied by a first bus 306) is
02) is precharged by the precharge circuit 307 during a high potential period. Also, from the first arithmetic module 304 or the second module 305 to the on-chip memory 30
The data to be written in 3 is transferred using the second bus 308, and the second bus 308 is precharged by a precharge circuit 309 while PH1 (301) is at a high potential 7). 310 is a memory safe k in the on-chip memory 303. 311 and 312 are data bit lines B, respectively.
A bit line B for logical inversion of data is precharged by a precharge circuit 313, and a word line WD is precharged by a precharge circuit 313.
Reference numeral 315 denotes a sense amplifier a. In the case of data reading (read enable signal RE31), the enable signal LE318 of the latch circuit 317 becomes valid, and the data is held in the latch circuit 317. This output data is controlled by the tri-state buffer 319. However, in the case of data writing, the write enable signal WE320 becomes valid and memory cell data is written.This data is transferred from the second bus 308 via the PH2 synchronous and PH1 synchronous latch circuits 321 and 322. The on-chip memory 303% is the output of the first module 304 and the second module 305 (which is output to the first bus 30a and the second bus 308 at a predetermined timing) and the precharge circuit 307, 309.
313 is composed of a p-type MOS transistor. The operation timing of the semiconductor integrated circuit using the conventional dynamic circuit shown in FIG. 3 will be explained with reference to FIG. 4.In accordance with the potential of the clock input 300 (400), internal clocks PHI and PH2 are generated (401. 402)-
. The bit line B511SB312 is precharged while PH1 is at a high potential (403a), and in the case of data reading, the word line WD 314 and the read enable signal RE316 are enabled (404'), and the potential of the bit line is determined. (403b or 403c). The read data is held in the latch circuit 317 (405)
. The first bus 306 is precharged while PH2 is at a high potential (406a), and the potential is determined according to the output of the on-chip memory 303 or the output of the second module 305 (406b or 406c). Also the second bus 3
08 is precharged during the period when PH1 is at high potential (40
7a), the potential is determined according to the output of the first module 304 or the output of the second module 305 (407
b or 407c).

The data on the second bus 308 is held in latches 321, 322 (408). In the case of data writing, word line WD314 and write enable signal W E 320
becomes valid (409), and the potential of the bit line is determined (
403b or 403c).

Problems to be Solved by the Invention In a CMO5 type semiconductor integrated circuit (i.e., no current flows except during switching operations), no steady large power supply leakage current occurs.1+~ If the power supply leakage current is large, There is a high probability of failure of 1%. In other words, by evaluating the power supply leakage current, it is possible to check the quality of the transistors in the CMO5 semiconductor integrated circuit device, as well as possible wiring shorts and gate oxide film abnormalities due to variations in manufacturing process conditions. It is possible to know the existence of a failure, and therefore it has important significance in the evaluation and failure analysis of semiconductor integrated circuit devices.Measurement of power supply leakage current has an important meaning in the evaluation and failure analysis of semiconductor integrated circuit devices. In integrated circuit devices, a large through-current may flow when the device is stationary, and there is a problem that power supply leakage current cannot be measured accurately.
In the example of FIG. 3, when the clock input 300 is at a low potential and no data is output to the second bus 308, the internal clock P H1 (301) is at a low potential and the second bus 308 is precharged. The charge accumulated in the gate capacitance and wiring capacitance of the gate connected to the bus is discharged by leakage over time, and the potential of the bus becomes an intermediate potential. However, when the clock input is at a low potential and there is no data writing, the bit lines B 311 and B 312 become high potential and high impedance ζ because the bit lines B 311 and B 312 are disconnected, so they become high impedance ζ. Similar to the bus 308, the voltage becomes intermediate for discharging, and a through current occurs at the gate on the side of the receiver.These through currents can be avoided by setting the clock input bus to a high potential. In this case, P H2 (302
) occurs in the first bus 306 and the second bus 308, and a phenomenon similar to that in Major Phenomenon 7 occurs, resulting in a large through current. As mentioned above, as the circuit scale of a semiconductor integrated circuit device becomes large and its functions become complex, a through current may occur at some point in the circuit configuration, and this current may enter the manufacturing process. The problem is that it is not possible to accurately estimate the power supply leakage current caused by the process.Also, since this through current is caused by a discharge phenomenon, it takes several seconds to several tens of seconds for the measured value to stabilize. Furthermore, the time required for stabilization varies greatly depending on the measurement ambient temperature and light irradiation.There is also the problem that it is difficult to unify the measurement conditions. This can be avoided to some extent by changing the settings.If the circuit scale becomes large or the number of logic stages from the signal input section to the corresponding signal line is deep (above), it becomes difficult to create test vectors.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit device in which power supply leakage current can be easily evaluated by adding a small amount of hardware. In order to solve the above-mentioned problems, the present invention includes means for setting a plurality of signal lines to be precharged to a ground potential or a power supply potential. A semiconductor integrated circuit that sets the plurality of signal lines to a ground potential when the signal is invalid, or sets the plurality of signal lines to a power supply potential when the test signal is valid or the precharge signal is valid. Even if the signal line to be precharged in a circuit device is connected to a means for setting it to ground potential or power supply potential, the signal line C
i Force set to ground potential when the test signal is valid and the precharge signal is invalid; or set to power supply potential when the test signal is valid or the precharge signal is valid. Therefore, the signal line to be precharged will not enter a high impedance state at any timing, and a through current will not occur at the gate on the receiving side when it is stationary (~ This setting is made for each signal line. This can be achieved with a single p-type MO3) transistor or n-type MOS transistor.There is no need to add large hardware or to generate test vectors for large-scale internal state settings.The manufacturing process is a factor. Embodiments of the present invention will be described below using drawings (Example 1).
) FIG. 1 is a block diagram of a semiconductor integrated circuit device which is an embodiment of the present invention. Components that are the same as those in Figure 3 are indicated by the same numbers as in Figure 3 above. In FIG. 1, 101 is a discharge section 102 that sets the first bus 306 to ground potential when P H2 (302) is a low voltage and the test signal T S T 104 is valid.
1 is a discharge circuit that sets the second bus 308 to the ground potential when the test signal T S T 104 is at a low potential and the test signal T S T 104 is valid. 103 is the bit line B5 when PH1 is at a low potential and the test signal T S T 104 is valid.
11 and B 312 to ground potential. The test signal T S T 104 is valid when set to a low potential, and the word line W D 314 . Read enable RE31a, write enable WE
320 may be disabled. On-chip memory 30a
, first module 304. All control signals for the tri-state output of the second module jo5 are also disabled and no data is output. Resistance discharge circuit 101.10
Although the discharging transistor 2° 103 is composed of an n-type MOS transistor, in the embodiment shown in FIG. 1, the test signal T S T 104 is set to a low potential when evaluating the power supply leakage current. The signal line whose precharge was cut off due to the setting of clock power 300 (friend test signal TST10
4 is valid and the precharge signal is invalid, it is set to the ground potential by the collection and discharge circuits 101, 10 and 103. Also, the signal line during precharging is set to a high potential. Therefore, the signal line will not enter a high impedance state at any timing, and no through current will occur at the gate on the side of the receiver. Add an AND circuit (realized by an NDR circuit in Figure 1) that generates a logical product of test signals, and one n-type MOS transistor for each signal line. All you have to do is control it.

Therefore, there is no need to generate test vectors for internal settings by simply adding hardware, and power supply leakage current caused by the manufacturing process can be easily evaluated.

(Embodiment 2) Figure 2 (above) is a block diagram of a semiconductor integrated circuit device which is a second embodiment of the present invention. In Figure 2, 201 indicates a case where PH2 is at a high potential or the test signal TST104 is valid. The precharge section 202 precharges the first bus 306 when PH1 is at a high potential or when the test signal T
Second bus 308 if S T 104 is enabled
The precharge circuit 203 precharges the bit line B511. when PH1 is at a high potential or the test signal TST 104 is valid. This is a precharge circuit that precharges B512. In a second embodiment, when test signal T S T 104 is valid, word line W D 314 . Read enable RE316
゜Write enable W E 320 is disabled.

Also, on-chip memory 303. first module 304
．． All the control signals for the tri-state output of the second module 305 are also invalidated, and no data is output (also, the precharge transistors of the precharge circuits 201, 202, and 203 are composed of p-type MOS transistors. In the embodiment shown in FIG. 2, the test signal T S T 104 is set to a low potential when the power is turned on and a small current is evaluated. Therefore, the signal line whose precharge is cut off due to the setting of the clock input 300 is set to the test signal T S T 1
Since 04 is valid, it will continue to be precharged.
Set to high potential. Therefore, if the signal line does not enter a high impedance state at any timing, a through current will occur at the gate on the side of the receiver.
This setting (above) can be achieved by simply adding an OR circuit that generates the logical sum of the precharge signal and the test signal during normal operation, and controlling the p-type MOS transistor of the precharge circuit with its output. Therefore, it is simple] 1 - By simply adding software, there is no need to generate test vectors for internal settings, and it is possible to easily evaluate the power supply current, which is caused by the manufacturing process.

Effects of the Invention According to the present invention, by realizing means for setting the precharged signal line to the ground potential or the power supply potential by adding some hardware, (1) the signal line can be easily used even in a circuit that performs dynamic operation. (2) There is no need for test vectors for internal settings, and it is possible to easily and accurately measure power supply leakage current even in large-scale circuits with deep logic stages. Current can be measured.

(3) It is not necessary to generate test vectors for internal settings, which reduces the time required to generate test vectors. (4) It is easier to measure power supply leakage current, which makes evaluation more efficient and failure analysis easier. It is extremely useful for evaluating large-scale semiconductor integrated circuit devices.

[Brief explanation of drawings]

FIG. 1 shows the configuration of a semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 2 shows the configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention. FIG. 3 shows the configuration using a conventional dynamic circuit. Figure 4 is a timing diagram of a semiconductor integrated circuit device using a conventional dynamic circuit. 103...discharge area 104...
...Test signal 201.202. ．． 20 East 307.
30 large 313...Precharge times i 301.
...Internal clock PH1, 302...Internal clock PH2, 303...On-chip memory, 304...
...1st module) I4 305...2nd module, 306...1st buff 5308...
Second input 310...memory cell, 311.31
2... Bit Turtle 316... Sense Ans

Claims (3)

[Claims] (1) A circuit having a plurality of signal lines precharged by a precharge signal, comprising means for setting the plurality of signal lines to a ground potential or a power supply potential, and the test signal is valid and the precharge signal is invalid. The plurality of signal lines are set to a ground potential when the test signal is valid, or the plurality of signal lines are set to a power supply potential when the test signal is valid or the precharge signal is valid. Semiconductor integrated circuit device. (2) The means for setting the plurality of signal lines to be precharged to the ground potential is composed of an n-type MOS transistor, and the n 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device controls a type MOS transistor. (3) The means for setting the plurality of signal lines to be precharged to the power supply potential is composed of p-type MOS transistors, and the p-type MOS A semiconductor integrated circuit device according to claim 1, which controls a transistor.