JPH04129087A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To easily identify the cause of malfunction and to enable an efficient analysis by closing a gate by applying a test signal of test signal generating means to the transfer gate. CONSTITUTION:A low level STEST signal from a test logical control circuit 12 is applied to an AND circuit 13, and a low level TRG signal is outputted and applied to the data transfer gate 52 to close the gate. Therefore, data stored in a port of serial access memory SAM can be read out to the outside without accompanying the data transfer to the SAM port from a port of random access memory RAM. Consequently, when an error exists in the read-out data, the generation of malfunction is identified in the course of reading out the data of SAM port, and it can be distinguished from the malfunction generated at the time when the data are transferred to the SAM port from the RAM port, then the cause can promptly be identified. Thus, the place causing the defective operation is promptly identified and the efficient analysis can be performed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a random access memory (RAM) board and a serial access memory (SAM) board. Multi boat・
It's about memory.

(Prior Art) FIG. 6 shows the configuration of the main parts of a conventional multiport memory. A RAM boat cell array 53 in which dynamic memory cells are arranged in a matrix, a SAM boat data register 51 consisting of a serial data register arranged in a column direction and connected to each row line of the RAM boat cell array 53, and data transfer control. A data transfer gate 52 is provided which transfers data between the RAM boat cell array 53 and the SAM port data register 51 in response to a signal TRG.

A multi-port memory with such a RAM port and a SAM port on the same chip enables high-speed data access from the SAM port and access from the CPU to the RAM port that is asynchronous to this access. Therefore, it is expected to have a wide range of applications such as image memory.

On the other hand, since multi-port memory not only has all the functions of general-purpose dynamic memory but also many special functions, product evaluation and failure analysis are extremely complex and wide-ranging, which delays commercialization. This is becoming a major problem.

Of the malfunctions that occur in multiport memories, the most important and complex to analyze are RAM ports and SAs.
This relates to data transfer to and from M boats. In particular, in the read transfer mode that transfers data from the RAM port to the SAM port, the operation mode of the SAM port is switched from the write cycle mode (Sertal In) to the read cycle mode (Serial 0ut), and at the same time, any row of the RAM port is transferred. It is necessary to transfer the data of the memory cell to the data register of the SAM port, and to take in from the RAM port the start address (generally used as a Tap Mill address) when reading this data serially. Since such operations are performed continuously, analysis to determine which operation is defective becomes complicated.

Regarding the operation of the SAM port in conventional equipment, Part 7
This will be explained using figures. SAM port data register 51
Each serial data register is connected to data line pair 5DQn and 5DQn, respectively.
n and 5DQn are connected to a serial manual buffer 62. The serial manual buffer 62 is provided with a serial input/output terminal 5IOn, and further includes a serial input control circuit 61 to which a serial clock SC and a serial enable signal SE are input.
is connected.

Serial enable signal SE is connected to serial input control circuit 6
1, the serial manual buffer 62 becomes operational, and serial data is input from the serial input/output terminal 5IOn or output to the outside based on the timing of the serial clock SC.

Here, when reading data from the SAM port to the outside, the operation mode of the SAM port must first be switched from write cycle mode to read cycle mode. However, this switching involves data transfer from the RAM port to the SAM port, and this operation completes the switching. Therefore, the data stored in the SAM port cannot be read externally at the current stage before the operation mode is switched, and the data stored in the data register 51 before the mode switch is It will be destroyed by. Therefore, the data stored in the RAM port cell array 53 is temporarily transferred to the SAM port data register 51, and this transferred data is read out. Even if there is an error in the read data, the data It is extremely difficult to separate and analyze whether there was a problem with the transfer of the data or whether there was a problem when reading the transferred data to the outside.

(Problems to be Solved by the Invention) As described above, with conventional multi-port memories, it is difficult to analyze malfunctions in read transfer mode, and it takes time to identify the defective location, or the defective location may be overlooked, resulting in product failure. Turnaround time for glue fines (T
AT) was significantly worsened.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device in which the cause of malfunction can be quickly identified and efficiently analyzed.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a random access memory port in which memory cells are arranged in a matrix, and a serial access memory port in which serial data registers are arranged in the column direction of the random access memory port. A semiconductor storage device that is equipped with a memory port on the same semiconductor chip, and when reading data stored in the serial access memory port to the outside. further comprising a test signal generating means for applying a test signal to a data transfer gate provided in the serial access memory port to close the gate; The feature is that the stored data can be read externally.

The invention further includes an electrode provided on the semiconductor chip and connected to the test signal generating means, and a lead connected to the electrode, and when a predetermined potential is supplied to the lead from the outside,
The test signal generating means may generate a test signal.

Furthermore, the timing at which the test signal generation means generates the test signal is determined by a combination of levels of a plurality of signals that define the operating mode of the semiconductor storage device, other than the combination that defines the normal operating mode. It may be something that

(Function) When reading data stored in the serial access memory port to the outside, a test signal is applied to the transfer gate by the test signal generating means, the gate is closed, and the serial access memory is read out from the random access memory port. No data is transferred to the port. As a result, if there is an error in the data read externally, it is identified that the malfunction occurred when reading data from the serial access memory port, and the serial access memory is transferred from the random access memory port to the serial access memory port. This can be distinguished from a malfunction in data transfer to a port.

Here, the timing at which the test signal generating means generates the test signal may be determined by supplying a predetermined potential to the lead from the outside and applying a signal to the test signal generating means from the electrode connected to this lead. Alternatively, the normal operation mode may be defined using a combination of levels of a plurality of signals that define the operation mode.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device according to this embodiment. As data transfer control signals, row address strobe (RAS) signal, column address strobe (CAS) signal, write enable (W
E) signal and data transfer (DT) signal are each input to the data transfer control circuit 11. In the conventional device, the data transfer control signal TRG was output from the direct data transfer control circuit 11 when these signals were in a predetermined combination.

In contrast, in this embodiment, the test logic control circuit 12 and A
An ND circuit 13 is further provided.

This test logic control circuit 12 is externally inputted with a TE multiplied signal that becomes high level during a test, and an inverted test signal (S
TEST) signal is output. This STEST signal and
A data transfer control (TRG-) signal output from the data transfer control circuit 11 is input to the AND circuit 13. A data transfer control (TRG) signal is output from this AND circuit 13 and input to the data transfer gate 52 shown in FIG.

A specific example of the circuit configuration of this test logic control circuit 12 is shown in FIG. The TE multiplied signal is input to the operation threshold adjusting means 21 in which P-channel transistors are connected in two stages, and 1) its output is applied to the input terminal N1 of an inverter composed of a P-channel transistor T2 and an N-channel transistor T3. An N-channel transistor T is connected to the input terminal N1.
The drain of No. 1 is connected, and during the test, a low level signal is applied to the gate and the gate is turned off.

Furthermore, a P-channel transistor T4 is connected as a resistor between the source of the P-channel transistor T2 and the power supply terminal.

The output terminal N2 of the inverter is connected to an amplifier 22 in which inverters are connected in two stages.
A TEST signal is output. The test logic control circuit 12 having such a configuration inverts the high level TE signal and outputs the low level 5TEST signal.

This low level 5TEST signal is applied to the AND circuit 13, and a low level TRG signal is outputted and applied to the data transfer gate 52 to close the gate. Thereby, data stored in the SAM port can be read to the outside without data transfer from the RAM port to the SAM port. Therefore, if there is an error in the read data, it means that a malfunction occurred during the process of reading data from the SAM port, and it can be distinguished from malfunctions that occur when transferring data from the RAM port to the SAM port, and the cause can be determined. This enables rapid identification.

Here, the TE multiplied signal is inputted from outside the device via a path as shown in FIG. Electrodes 33 prepared for testing are formed inside the semiconductor chip 30, and the semiconductor chip 30
package 311; leads 32 held on the outside of the package 311;
is provided. This lead 32 is a non-connection wire that is not connected to other electrodes.
n Pin), and the bonding wire 3 is connected to the electrode 33.
Connected by 4. When performing the test, use lead 3.
By supplying a voltage higher than the power supply voltage Vcc to 2, a high level T1 signal is input to the test logic control circuit 12 via the electrode 33.

In this embodiment, a 5TEST signal indicating that a test is in progress is generated by receiving a TE multiplied signal from outside the device. However, even if such signals are not supplied from the outside, conventionally used operation signals may be newly combined and defined. FIG. 4 shows a truth table of operating signals internationally defined by the Electronic Device Engineering Council (JEDEC). In the diagram, it is also possible to select (1) or (2), which is a combination other than the already defined combinations, and to specify that the test is to be performed when this combination is established.

Furthermore, since the means of this embodiment is used at the stage of inspecting malfunctions, it is necessary to prevent the 5TEST signal from going to a high level at the stage of shipping as a product. In this embodiment, the power supply voltage Vcc is applied to the gate of the N-channel transistor T1 in the test logic control circuit shown in FIG. 2, and the low level of the 5TEST signal is guaranteed by turning it on.

Further, the present invention can be applied, and a semiconductor memory device according to another embodiment will be explained using FIG. In this device, the RAM boat cell array 73 or cell array 73a
and 73b. Similarly, the SAM port data register 71 is set to data registers 71a and 71b.
It is divided into Data transfer between cell array 73a and data register 71a is controlled by data transfer gate 72a, and data transfer between cell array 73b and data register 71a is controlled by data transfer gate 72a.
1b is controlled by a data transfer gate 72b. In this way, the RAM port and the SAM port are divided into two, making split transfer possible.

A TRGa signal and a TRGb signal are input as data transfer control signals to the data transfer gates 72a and 72b, respectively. The TRGa signal and TRGb signal are in an independent relationship.

That is, it has two sets of circuits shown in FIG. 1, two types of TEa signal and TEb signal are inputted from the outside to each, and a TRGa signal and a TRGb signal are independently generated.

As a result, when reading data stored in one data register 71a to the outside, for example, only the data transfer gate 72g is closed to prevent data from being transferred from the cell array 73a to the data register 71a, thereby eliminating the cause of malfunction. can be quickly determined.

〔Effect of the invention〕

As explained above, according to the present invention, the RAM boat and the S
When testing malfunctions between AM boats, a test signal is applied to the transfer gate by the test signal generating means, the gate is closed, and data is stored in the SAM port without data transfer from the RAM boat to the SAM port. Since the stored data can be read out to the outside, the cause of malfunction can be easily identified and analyzed efficiently, and it is possible to improve TAT and reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a test logic control circuit in the same device, and FIG. 3 is a circuit diagram showing the configuration of a test logic control circuit in the same device.
A circuit diagram showing the route input from the outside of the E-multiplier signal device,
FIG. 4 is an explanatory diagram showing combinations of operational truth values defined by JEDEC, FIG. 5 is a circuit diagram showing the configuration of a semiconductor memory device according to another embodiment of the present invention, and FIG. 6 is an explanatory diagram showing the combination of operation truth values defined by JEDEC. FIG. 7 is a block diagram showing a schematic configuration of a multi-port memory to which a semiconductor storage device according to an embodiment can be applied; FIG. 7 is a block diagram showing components on the SAM port side of a conventional multi-port memory; It is. DESCRIPTION OF SYMBOLS 11... Data transfer control circuit, 12... Test logic control circuit, 13... AND circuit, 21... Operation threshold adjustment means, 22... Inverter, 3o... Semiconductor chip, 31...・Package, 32...Lead, 33・
...electrode, 34...bonding wire, 51.71
...SAM boat data register, 52.72...
Data transfer gate, 53.73...RAM boat cell array, TI, T3...N channel transistor, T
2゜T4...P channel transistor.

Claims (1)

[Claims] 1) A random access memory port in which memory cells are arranged in a matrix is the same as a serial access memory port in which serial data registers are arranged in the column direction of the random access memory port. In a semiconductor memory device provided on a semiconductor chip, when reading data stored in the serial access memory port to the outside, the random access
further comprising test signal generating means for applying a test signal to a data transfer gate provided between a memory port and the serial access memory port to close the gate, and transferring the data from the random access memory port to the serial access memory port. A semiconductor memory device characterized in that the data stored in the memory port can be read out to the outside without data transfer to the memory port. 2) Further comprising an electrode provided on the semiconductor chip and connected to the test signal generating means, and a lead connected to the electrode, and when a predetermined potential is supplied to the lead from the outside, the test signal is generated. 2. A semiconductor memory device according to claim 1, wherein said generating means generates said test signal. 3) The timing at which the test signal generation means generates the test signal is a combination of levels of a plurality of signals that define the operation mode of the semiconductor memory device, other than the one that defines the normal operation mode. 2. The semiconductor memory device according to claim 1, wherein: