JPH03109660A - Memory access control system for dual bus system - Google Patents

Abstract

PURPOSE:To enable two bus masters to simultaneously have accesses to a common memory by controlling a gate circuit and securing the connection between a memory area including an address received an access and a shared bus to which an access is given only when the memory area is not used presently. CONSTITUTION:It is supposed that a bus master 6-1 outputs an address included in a memory area 5-1 to a shared bus 2-1 and has an access to a common memory 1. Thus a memory access control circuit 3 controls a gate circuit 4-1 and secures the connection between the area 5-1 and the bus 2-1 as long as the area 5-1 is kept unused. Furthermore the circuit 3 gives the permission to the master 6-1 serving an access starter for use of the memory 1 and also changes the contents of a memory use permission table 31 corresponding to the area 5-1 into a busy mode. The master 6-1 outputs the read and write signals, etc., to the bus 2-1 with permission secured for use of the memory 1. As a result, two bus masters can have the simultaneous accesses to the memory 1.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a dual bus system in which buses are duplicated, and in particular, to memory access in a dual bus system that controls access to a common memory in the dual bus system. Regarding control method.

[Conventional technology]

Dual bus systems have been proposed in the past, in which buses are duplicated and a plurality of bus masters such as microprocessors, a common memory, input/output devices, etc. are connected to each of the duplicated buses. By duplicating the buses in this way, when one of the multiple bus masters uses one bus to access, for example, common memory, the other bus masters use the other bus to access input/output devices. It becomes possible to access other resources such as Also, as mentioned above,
In such a conventional dual bus system, when a bus master attempts to access a common memory, the access is permitted on the condition that no other bus master is accessing the common memory.

[Problem to be solved by the invention]

In the conventional example described above, if a bus master tries to access the common memory, if another bus master is accessing the common memory, the common memory cannot be accessed, and even though the bus is duplicated, , there was a problem in that only one bus master could access the common memory.

An object of the present invention is to enable two bus masters to access a common memory at the same time.

[Means to solve the problem]

In order to achieve the above object, the present invention includes two shared buses, a common memory connected to each of the two shared buses, and a plurality of memory devices that can access the common memory via each of the two shared buses. In a dual bus system including a bus master, the gate circuit divides the memory space of the common memory into a plurality of memory areas and controls the connection between each of the memory areas and the two shared buses, and the gate circuit a memory access control circuit that controls the common memory via the shared bus, and a memory use permission table that stores information indicating whether each of the memory areas is in use. When accessed, the memory area including the accessed address is controlled by referring to the memory usage permission table and determining that the memory area including the accessed address is unused. connecting the accessed shared bus to the accessed shared bus, further granting memory usage permission to the accessing bus master, and changing the contents of the memory usage permission table corresponding to the memory area including the accessed address while in use; Upon completion of the access, the gate circuit is controlled to separate the memory area containing the accessed address from the accessed shared bus, and further the memory area containing the accessed address in the memory use permission table is controlled. The content of the correspondence is marked as unused.

[For production]

The memory space of the common memory is divided into a plurality of memory areas, and the connection between each memory area and the two shared buses is controlled by a gate circuit. When the common memory is accessed via the shared bus, the memory access control circuit determines whether or not the memory area including the accessed address is in use by referring to the memory use permission table. If it is determined that the memory area is not in use, it controls the gate circuit to connect the memory area containing the accessed address to the accessed shared bus of the two shared buses, and connects the accessed bus master. At the same time, the content of the memory use permission table corresponding to the area including the accessed address is changed to be in use, and the memory area is prevented from being accessed via another shared bus. Furthermore, when the access to the common memory is completed, the memory access control circuit controls the gate circuit to separate the memory area containing the accessed address from the accessed shared bus, and further controls the access to the memory usage permission table. The contents of the memory area including the completed address are changed to unused, and the memory area is made accessible.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention, showing two shared buses 2-1.2-2 and a respective shared bus 2-1.2-2.
2, and a common memory 1 connected to each of the shared buses 2-1 and 2-2. The common memory 1 is provided with M memory areas 5-1 to 5-M obtained by dividing the memory space into M, and is provided corresponding to each memory area 5-1 to 5-M. It includes gate circuits 4-1 to 4-M that control the connection between M and the shared bus 2-1.2-2, and a memory access control circuit 3 that controls the gate circuits 4-1 to 4-M. . Further, the memory access control circuit 3 includes a memory use permission table 31 in which information indicating whether each memory area 5-1 to 5-M is in use is stored.

For example, assume that the bus master 6-1 accesses the common memory 1 by outputting an address in the memory area 5-i to the shared bus 2-1. Note that the bus master 6-1 is connected to the shared bus 2.
When accessing the common memory 1 via the bus 2-1, the address is output after confirming that the shared bus 2-1 is not in use.

When the common memory 1 is accessed from the bus master 6-1 via the shared bus 2-1, the memory access control circuit 3 in the common memory 1 accesses the memory area 5-1 based on the address output to the shared bus 2-1. It is determined which one of 1 to 5-M has been accessed. In this example, it is determined that memory area 5-i has been accessed. Thereafter, the memory access control circuit 3 refers to the memory use permission table 31 and determines whether the memory area 5-1 is in use.

If it is determined that the memory area 5-i is unused, the memory access control circuit 3 controls the gate circuit 4-i to connect the memory area 5-1 and the shared bus 2-1. Furthermore, the access source bus master 6-1 is granted memory usage permission, and the memory usage permission table 31 is
The contents corresponding to memory area 5-i are changed during use. When the bus master 6-1 is given permission to use the memory by the memory access control circuit 3, it outputs read signals, write signals, data, etc. to the shared bus 2-1. After performing the above processing, when the memory access control circuit 3 detects the end of the access, it controls the gate circuit 4-i to disconnect the memory area 5-i from the shared bus 2-1, and also updates the memory use permission table. 3. Change the contents corresponding to memory area 5-i in 1 to unused.

In addition, if it is determined that the memory area 5-i is in use, that is, the memory area 5-i is
is being accessed, the memory access control circuit 3 waits until the access via the shared bus 2-2 is completed, that is, the memory area 5-i of the memory use permission table 31 is accessed.
Wait until the corresponding content becomes unused, and perform the same process as described above.

Further, as described above, while the bus master 6-1 is accessing the memory area 5-1 via the shared bus 2-1, the bus master 6-N is accessing the memory area 5-1 via the shared bus 2-2. If the memory area 5-j is accessed in the memory use permission table 31, if the contents corresponding to the memory area 5-j are unused, the shared bus 2-2 is accessed in the same manner as described above.
and memory area 5-j are connected via gate circuit 4-3, and memory area 5-j is accessed via shared bus 2-2 by bus master 6-N.

〔Effect of the invention〕

As explained above, the present invention divides the memory space of a common memory into a plurality of memory areas, provides a gate circuit for controlling the connection between each memory area and the shared bus, and provides a memory area including an accessed address. The gate circuit is controlled to connect the memory area containing the accessed address to the accessed shared bus only when the bus master is not in use, so two bus masters can connect the common memory at the same time. There are effects that can be accessed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention. In the figure, 1... common memory, 2-1.2-2...
・Shared bus, 3...Memory access control circuit, 4-1
~4-M...Gate circuit, 5-1~5-M...Memory area, 6-1~6-N...Bus master, 31...
Memory usage grant table.

Claims (1)

[Scope of Claims] Two shared buses; a common memory connected to each of the two shared buses; and a plurality of bus masters that can access the common memory via each of the two shared buses. In a dual bus system, the gate circuit divides the memory space of the common memory into a plurality of memory areas and controls the connection between each memory area and the two shared buses, and the memory controls the gate circuit. The memory access control circuit includes an access control circuit and a memory use permission table that stores information indicating whether each of the memory areas is in use, and the memory access control circuit controls when the common memory is accessed via the shared bus. , refers to the memory use permission table and determines that the memory area including the accessed address is unused, thereby controlling the gate circuit to determine the memory area including the accessed address and the access. Furthermore, the access source bus master is granted permission to use the memory, and the contents of the memory area corresponding to the accessed address in the memory use permission table are changed to in use, and the access is completed. By controlling the gate circuit, the memory area including the accessed address is separated from the accessed shared bus, and the contents of the memory use permission table corresponding to the memory area including the accessed address are read. A memory access control method in a dual bus system that is characterized by being unused.