JPH03108767A - Display device - Google Patents

Display device

Info

Publication number
JPH03108767A
JPH03108767A JP2212020A JP21202090A JPH03108767A JP H03108767 A JPH03108767 A JP H03108767A JP 2212020 A JP2212020 A JP 2212020A JP 21202090 A JP21202090 A JP 21202090A JP H03108767 A JPH03108767 A JP H03108767A
Authority
JP
Japan
Prior art keywords
electrode
electrodes
melting point
transistors
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2212020A
Other languages
Japanese (ja)
Inventor
Yutaka Senoo
妹尾 豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2212020A priority Critical patent/JPH03108767A/en
Publication of JPH03108767A publication Critical patent/JPH03108767A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent disconnection of a drain electrode, a source electrode itself, improper contact of the source electrode with a segment electrode made of light transmission conductive oxide by forming the source electrode and the drain electrode of a TFT of a 2-layer structure having a base layer of high melting point metal such as titanium, etc. CONSTITUTION:In an active matrix type display device in which thin film transistors are disposed correspondingly in a matrix on segment electrodes 11 made of a plurality of light transmission conductive oxide films disposed in a matrix, and source electrodes 17 of the transistors are partly superposed to be connected to the electrodes 11 corresponding to the transistors, the electrodes 17 and the drain electrodes 16 of the transistors are formed of 2-layer structure having a base layer 16, made of high melting point metal such as titanium, etc., the superposing part of the electrodes 17, 11 is formed in a laminate of light transmission conductive oxide, the metal and electrode main metal, and the connecting part of a semiconductor layer 14, the electrodes 17, 16 of the transistor is formed in a laminate of semiconductor, high concentration impurity semiconductor 14', the high melting point metal and the electrode main metal.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はマトリックス状の表示セグメントを有する液晶
表示装置の如き表示装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a display device such as a liquid crystal display device having a matrix of display segments.

(ロ)従来の技術 マトリックス状の表示セグメントを有する表示装置とし
ては、日経エレクトロニクス1984年1月2日号の記
事「文書と画像表示をねらうフラット・パネル・デイス
プレィ」に開示されている様に液晶表示器を用いたもの
、エレクトロ・ルミネッセンス表示器を用いたもの、等
各種の表示装置が存在するが、現在は低消費電力大容量
化が可能である点で液晶表示器の将来性が高く評価され
ている。
(b) Conventional technology As a display device having a matrix-like display segment, there is a liquid crystal display as disclosed in the article "Flat panel display aimed at displaying documents and images" in the January 2, 1984 issue of Nikkei Electronics. There are various display devices, such as those using displays and those using electroluminescence displays, but liquid crystal displays are currently highly regarded for their future potential due to their low power consumption and large capacity. has been done.

斯様な液晶表示装置の一般的構成の要部平面図を第3図
(a)に示し、同図(b)にそのX−X線断面図を示す
。これ等の図に於いて、(10)は第1のガラス基板、
(11)・・・は第1のガラス基板(10)上に窒化シ
リコンからなる層間絶縁膜(12)を介して行列配置(
約250X 600)された透明なITOからなるセグ
メント電極である。(13)・・・は上記セグメント電
極(11)(11)・・・間隙の層間絶縁膜(12)l
に縦方向に複数本並列配置したアモルファスシリコン膜
ラインであり、各セグメント電極(11)(]、1.)
  の左下方のスペースに突設した半導体動作領域(1
4)(1’l)・・・が設けられている。(15)・・
・は各アモルファスシリコン膜ライン(13)・・・」
二に配置されたアルミニウム膜からなるドレインライン
であり、上記各半導体動作領域(14)(14)の左側
辺上に重畳したドレイン電極(16)(16)が突設さ
れている。(17)(17)・・は各半導体動作領域(
14)(M)・・の右側辺」−に一部重畳したアルミニ
ウム膜からなるソース電極であり、その右側辺は層間絶
縁膜(1,2)lで対応する各セグメント電極(11)
(]1)・・・の左下端部と接続されている。(]8)
・・・は」二記セグメンl−1j極(11)(]])・
間隙位置を横方向に複数本並列配置されて」二記第1の
ガラス基板(10)と絶縁膜(12)との層間に形成さ
れた金とクロムの2層膜からなるゲートラインであり、
該ライン(18)・・・には上記各ソース電極(17)
・・・とドレイン電極(16)・・・どの間隙位置の半
導体動作領域(14)下のゲート電極(19)・・・が
一体に突設されている。即ち、図中りで示すドレイン電
極(16)・・・と、Sで示すソース電極(17)・と
、Gで示すゲート電極(19)・・・と、これ等電極り
、S、Gに結合しているアモルファスシリコン膜からな
る半導体動作領域(14)・・・箇所とに依って薄膜ト
ランジスタ(TPT)が行列配置されており、各セグメ
ン) (11,)(11)・・・は夫々に対応したこの
TPTを介してドレインライン(15)・に接続される
のである。
FIG. 3(a) shows a plan view of essential parts of the general configuration of such a liquid crystal display device, and FIG. 3(b) shows a cross-sectional view taken along the line X--X. In these figures, (10) is the first glass substrate,
(11)... are arranged in rows and columns (
It is a segment electrode made of transparent ITO with a size of about 250×600. (13)... is the segment electrode (11) (11)... interlayer insulating film (12) l in the gap
A plurality of amorphous silicon film lines are arranged in parallel in the vertical direction, and each segment electrode (11) (], 1.)
The semiconductor operating area (1
4) (1'l)... is provided. (15)...
・ indicates each amorphous silicon film line (13)...''
This is a drain line made of an aluminum film arranged on the second side, and overlapping drain electrodes (16) (16) are provided protrudingly on the left side of each of the semiconductor operating regions (14) (14). (17) (17)... is each semiconductor operating region (
14) A source electrode made of an aluminum film partially superimposed on the right side of (M).
It is connected to the lower left end of (]1).... (]8)
...is'' 2 segment l-1j pole (11) (]])・
A gate line consisting of a two-layer film of gold and chromium formed between the first glass substrate (10) and the insulating film (12), with a plurality of gate lines arranged in parallel in the horizontal direction at the gap position,
Each of the above source electrodes (17) is connected to the line (18)...
. . . and a drain electrode (16) . . . and a gate electrode (19) under the semiconductor operating region (14) at which gap position are integrally provided in a protruding manner. That is, the drain electrode (16) shown in the figure, the source electrode (17) shown by S, the gate electrode (19) shown by G, and these electrodes, S and G. Semiconductor operating region (14) consisting of bonded amorphous silicon films... Thin film transistors (TPT) are arranged in rows and columns depending on the location, and each segment (11,) (11)... It is connected to the drain line (15) through the corresponding TPT.

(1,00)は」二記各セグメント電極(11,)(1
1)・・・上記ドレインライン(]5)・・及び上記T
PT箇所を一面に被覆した配向膜である。
(1,00) is 2. Each segment electrode (11,) (1
1)...The above drain line (]5)...and the above T
This is an alignment film that completely covers the PT area.

一方、(20)は第2のガラス基板であり、その下面、
即ち第1のガラス基板(10)と対向する面には一面に
共通電極(21)、配向膜(200)が順次形成されて
いる。
On the other hand, (20) is the second glass substrate, the lower surface of which
That is, a common electrode (21) and an alignment film (200) are sequentially formed on the surface facing the first glass substrate (10).

(30)は」二記両基板(10)、(20)間即ち両配
向膜(100)、(200)間に封入された液晶物質で
あり、各マトリクスセグメント 事に依って表示信号、即ち液晶励起電圧が印加される第
1のガラス基板〔〕0)のセグメント電極(11)箇所
の液晶物質(30)が電気光学効果を引き起こす事とな
る。
(30) is a liquid crystal substance sealed between the two substrates (10) and (20), that is, between the alignment films (100) and (200). The liquid crystal material (30) at the segment electrode (11) of the first glass substrate []0) to which the excitation voltage is applied causes an electro-optic effect.

(ハ)発明が解決しようとする課題 上述の如き従来の表示装置に於いては、そのTPTは、
第2図の要部断面図に示す如く、そのソース電極(17
)のアルミニウムがセグメント電極(11)のITOJ
二に直接コンタクトされているので、ソース電極形成の
際、アルミニウムのパターンニング用の燐酸系エッチャ
ントがITOとアルミニウムとの間で電気化学的反応を
引き起こす事となる。この結果、ITOとアルミニウム
とのコンタクト部が侵され、ソース電極(17)とセグ
メント電極(11)とのコンタクト不良を招く欠点があ
った。
(c) Problems to be Solved by the Invention In the conventional display device as described above, the TPT is
As shown in the cross-sectional view of the main part in Fig. 2, the source electrode (17
) is the segment electrode (11) of ITOJ.
Since the ITO and aluminum are in direct contact with each other, when forming the source electrode, a phosphoric acid-based etchant for patterning aluminum causes an electrochemical reaction between the ITO and aluminum. As a result, the contact portion between the ITO and aluminum is corroded, resulting in poor contact between the source electrode (17) and the segment electrode (11).

さらには、ソース電極(17)並びにドレイン電極(1
6)のアルミニウムがアモルファスシリコンの半導体動
作領域(14)lに、これ等のオーミックコンタクトを
図る為のn+型アモルファスシリコン膜(14’)を介
してコンタクトされているので、この後の配向膜(10
0)の例えばポリイミドの硬化処理(200℃、1時間
)によって、アルミニウムがn4型アモルファスシリコ
ン膜(14’)中に拡散導入される事となる。この結果
このn+型アモルファスシリコン膜(14 ’ )のn
+の濃度が低下してしまい、この膜(14’)のオート
ミックコンタクトの働きを阻害してしまう欠点があった
Furthermore, a source electrode (17) and a drain electrode (1
Since the aluminum of 6) is contacted to the amorphous silicon semiconductor operating region (14)l via the n+ type amorphous silicon film (14') for making ohmic contact with these, the following alignment film ( 10
For example, by the polyimide curing treatment (200° C., 1 hour) in step 0), aluminum is diffused and introduced into the n4 type amorphous silicon film (14'). As a result, the n of this n+ type amorphous silicon film (14')
There was a drawback that the concentration of + decreased and the automic contact function of this film (14') was inhibited.

(二)課題を解決するための手段 本発明は、TPTのソース電極、並びにドレイン電極を
チタン等の高融点金属を下地層に有する2層構成とし、
この電極主体金属と透光性導電酸化物との間並びにこの
電極主体金属と非晶質半導体層の表面部の高不純物非晶
質半導体層との間に高融点金属を共存させた表示装置を
提供するものである。
(2) Means for Solving the Problems The present invention has a TPT source electrode and drain electrode having a two-layer structure having a high melting point metal such as titanium as an underlying layer,
A display device in which a high melting point metal coexists between the electrode main metal and the transparent conductive oxide and between the electrode main metal and the high impurity amorphous semiconductor layer on the surface of the amorphous semiconductor layer. This is what we provide.

(ホ)作用 本発明の表示装置によれば、ソース電極とセグメント電
極との重畳箇所で、中間の高融点金属が例えばチタンが
アルミニウムとITOとの間に介存するので、現像液や
リン酸系エラチャンl−m1月こ於いてもアルミニウム
/チタン、チタン/ITOの両コンタクトのいずれでも
電気化学反応は生じない。
(E) Function According to the display device of the present invention, since an intermediate high melting point metal such as titanium is present between aluminum and ITO at the overlapped portions of the source electrode and the segment electrode, developer solution or phosphoric acid-based Even at this time, no electrochemical reaction occurred in either the aluminum/titanium or titanium/ITO contacts.

さらには、このチタンの如き高融点金属の存在により、
ソース電極並びにドレイン電極と高濃度不純物非晶質半
導体層との接続箇所で、これ等電極のアルミニウムのよ
うな金属材料がこの半導体層内に拡散されるのを防止で
きる。
Furthermore, due to the presence of high melting point metals such as titanium,
At the connection points between the source electrode and the drain electrode and the highly doped amorphous semiconductor layer, it is possible to prevent the metal material such as aluminum of these electrodes from being diffused into the semiconductor layer.

又、表示装置内の配線を兼ねるドレイン電極が高融点金
属の下地層を備えているので、このトレイン電極の配線
が断線する事故を解決し得る。
Furthermore, since the drain electrode, which also serves as the wiring within the display device, is provided with a base layer of a high-melting point metal, it is possible to solve the problem of disconnection of the wiring of the train electrode.

(へ)実施例 第1図に本発明の表示装置の要部の断面図を示す。同図
の装置はガラス基板(I O)−J二に金とクロムの2
層膜からなるゲート電極(19)、窒化シリコンからな
る絶縁膜(12)、真性のアモルファスシリコン膜から
なる半導体動作領域(14)が順次形成され、さらに該
領域(14)J二のドレイン、ソース各箇所に燐ドープ
された1〕1型アモルファスシリコン11A (14’
 )(14’ )カ連続形成され、さらに、ITOから
なるセグメント電極(11)がこれに近接して形成され
ている。以上は第2図の従来装置と同様に形成される。
(F) Embodiment FIG. 1 shows a sectional view of the main parts of the display device of the present invention. The device shown in the figure is a glass substrate (IO)-J with two layers of gold and chromium.
A gate electrode (19) made of a layered film, an insulating film (12) made of silicon nitride, and a semiconductor operating region (14) made of an intrinsic amorphous silicon film are successively formed, and the drain and source of the region (14) J2 are formed in sequence. 1] Type 1 amorphous silicon 11A (14'
) (14') are formed continuously, and further, a segment electrode (11) made of ITO is formed adjacent to this. The above is formed in the same manner as the conventional device shown in FIG.

本発明の表示装置が第2図の従来装置と異なる所は、上
記n 4型アモルファスシリコン膜(14’)(14′
)と、セグメント電極(11)のITO上に形成される
ドレイン電極(16)並びにソース電極(17)の夫々
に高融点金属であるチタンの下地層(16’)(17′
)を形成した点にある。尚、この下地層(16’)はド
レイン電極(16)に連なる第3図のドレインライン(
15)下にも共通して延在している。
The difference between the display device of the present invention and the conventional device shown in FIG.
), a drain electrode (16) and a source electrode (17) formed on the ITO of the segment electrode (11), respectively, with base layers (16') and (17') of titanium, which is a high melting point metal.
). Note that this base layer (16') is connected to the drain line (16') shown in FIG.
15) Commonly extends downward as well.

従って、トレインライン(15)に連なるドレイン電極
(]6)、並びにソース電極(17)となるアルミニウ
ムをパターンニングする為に燐酸系エッチャントを使用
したとしても、このアルミニウムとITOとの間にはチ
タンが介在しているので、アルミニウム/チタン、チタ
ン/ITOの両コンタクトで電気化学反応は生じない。
Therefore, even if a phosphoric acid-based etchant is used to pattern the aluminum that will become the drain electrode (6) and the source electrode (17) connected to the train line (15), there is no titanium between this aluminum and the ITO. is present, so no electrochemical reaction occurs at both the aluminum/titanium and titanium/ITO contacts.

よって、ITOのセグメント電極(11)、チタンの下
地層(17’)、ソースミ極(エフ)の三層間のオーミ
ックコンタクトが確保されている。
Therefore, ohmic contact between the three layers of the ITO segment electrode (11), the titanium base layer (17'), and the source electrode (F) is ensured.

一方、」二連の如きセグメント電極(]1)及びTPT
」二に第3図と同様のポリイミドからなる配向膜(1,
00)を形成する際に、硬化処理(200℃、1時間)
を施したとしても、トレイン電極(I6)並びにソース
電極(17)のアルミニウムは、下地層(16’)(]
7′)のチタンの存在によって、その下層のn+型アモ
ルファスシリコン膜(]4’)(14’)に拡散導入す
るのを防止する事となる。
On the other hand, segment electrodes (]1) such as ``double series'' and TPT
” Second, an alignment film (1,
00), hardening treatment (200°C, 1 hour)
Even if the aluminum of the train electrode (I6) and the source electrode (17) is applied, the base layer (16') (]
The presence of titanium in 7') prevents titanium from being diffused into the underlying n+ type amorphous silicon film (]4') (14').

又、ドレインライン(15)のアルミニウム膜下にも下
地層が存在するので、これ等上下両層のいずれに断線が
生じたとしても互いにこれを補償し合って電気的な接続
を維持し得る事となる。
Furthermore, since there is a base layer under the aluminum film of the drain line (15), even if a disconnection occurs in either of these layers, they can compensate for each other and maintain electrical connection. becomes.

上述の実施例に於いては、TPTの半導体層としてアモ
ルファスシリコン膜 る事なくセレン等の多結晶物質等、−船釣な非単結晶質
半導体層が用いられ、又、セグメント電極(11)とし
てはITO以外にも透光性導電酸化物の使用が可能であ
る。さらに、下地層(16’)(17’)としてはチタ
ンの他にもモリブデン、タングステン、タンタルの如き
高融点金属が使用でき、ドレイン電極(16)、ソース
電極(17)はアルミニウム以外にもクロム等の金属が
用いられる。
In the above embodiment, a non-single crystal semiconductor layer such as a polycrystalline material such as selenium is used as the semiconductor layer of the TPT instead of an amorphous silicon film, and as the segment electrode (11) Transparent conductive oxides other than ITO can also be used. Furthermore, as the base layer (16') (17'), other than titanium, high-melting point metals such as molybdenum, tungsten, and tantalum can be used. Metals such as

(ト)発明の効果 本発明の表示装置は、以上の説明から明らかな如く、T
PTのソース電極並びにドレイン電極に高融点金属から
なる下地層を形成して二層構成とするだけで、ドレイン
電極やソース電極自体の断線を防止し得るばかりか、ソ
ース電極と透光性導電酸化物からなるセグメントを極と
の間の接触不良を防止し得ると共に、ドレイン電極並び
にソース電極から半導体層」二の高不純物半導体への電
極材料の拡散導入を阻止する事ができる。
(G) Effects of the Invention As is clear from the above description, the display device of the present invention has T.
By simply forming a base layer made of a refractory metal on the source and drain electrodes of PT to create a two-layer structure, not only can disconnection of the drain and source electrodes themselves be prevented, but also the source electrode and the transparent conductive oxide It is possible to prevent poor contact between the segment made of the material and the electrode, and also to prevent the electrode material from diffusing into the highly impurity semiconductor of the semiconductor layer from the drain electrode and the source electrode.

従って、TPTの半導体と各電極、及びソース電極とセ
グメント電極のオーミックコンタクトを維持でき、この
種アクティブマトリックス型の表示装置の信頼性の大幅
な向」二が図れる。
Therefore, ohmic contact can be maintained between the TPT semiconductor and each electrode, and between the source electrode and the segment electrode, and the reliability of this type of active matrix display device can be greatly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の表示装置の要部断面図、第2図は従来
装置の要部断面図、第3図(a)(+))は従来装置の
平面図、及びそのX−X線断面図である。 (]、0)(20)・・・基板、(1])・・セグメン
ト電極、(12)・・・層間絶縁膜、(13)・・アモ
ルファスシリコン膜ライン、(14)・・・半導体動作
領域、(14’)・・I〕“型アモルファスシリコン膜
、(15)・・・ドレインライン、(16)・・・ドレ
イン電極、(16’)・・・下地層、(17)・・・ソ
ース電極、(17’)・・下地層、(18)・・・ゲー
トライン、(]9)・・・ゲート電極、(21)・・共
通電極、(30)・・液晶物質。
Fig. 1 is a sectional view of the main part of the display device of the present invention, Fig. 2 is a sectional view of the main part of the conventional device, and Fig. 3 (a) (+)) is a plan view of the conventional device and its X-X line. FIG. (], 0) (20)...Substrate, (1])...Segment electrode, (12)...Interlayer insulating film, (13)...Amorphous silicon film line, (14)...Semiconductor operation Region, (14')...I] "type amorphous silicon film, (15)...Drain line, (16)...Drain electrode, (16')...Underlayer, (17)... Source electrode, (17')...base layer, (18)...gate line, (]9)...gate electrode, (21)...common electrode, (30)...liquid crystal material.

Claims (1)

【特許請求の範囲】[Claims] (1)行列配置された複数の透光性導電酸化物膜からな
るセグメント電極の夫々に半導体層を有する薄膜トラン
ジスタを対応させて行列配置してなり、薄膜トランジス
タのソース電極を該トランジスタに対応するセグメント
電極に一部重畳接続すると共に、所定数の薄膜トランジ
スタのドレイン電極を一体的に延在接続してなるアクテ
ィブマトリックス型の表示装置に於いて、 上記トランジスタのソース電極並びにドレイン電極はチ
タン等の高融点金属からなる下地層を有する2層構成と
し、ソース電極と上記セグメント電極との重畳箇所では
透光性導電酸化物と高融点金属と電極主体金属との積層
体とし、上記半導体層とトランジスタのソース電極並び
にドレイン電極との接続箇所では半導体と高濃度不純物
半導体と高融点金属と電極主体金属との積層体となした
事を特徴とする表示装置。
(1) Thin film transistors each having a semiconductor layer are arranged in rows and columns, each of which is made up of a plurality of transparent conductive oxide films arranged in rows and columns, and the source electrodes of the thin film transistors are connected to the segment electrodes corresponding to the transistors. In an active matrix type display device in which drain electrodes of a predetermined number of thin film transistors are connected in an integral manner and partially overlapped with each other, the source and drain electrodes of the transistors are made of a high melting point metal such as titanium. It has a two-layer structure with a base layer consisting of the semiconductor layer and the source electrode of the transistor, and a laminate of a transparent conductive oxide, a high melting point metal, and an electrode main metal is used at the overlapped portion of the source electrode and the segment electrode, and the semiconductor layer and the source electrode of the transistor Furthermore, a display device characterized in that a laminate of a semiconductor, a high-concentration impurity semiconductor, a high melting point metal, and an electrode main metal is formed at a connection point with a drain electrode.
JP2212020A 1990-08-09 1990-08-09 Display device Pending JPH03108767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2212020A JPH03108767A (en) 1990-08-09 1990-08-09 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2212020A JPH03108767A (en) 1990-08-09 1990-08-09 Display device

Publications (1)

Publication Number Publication Date
JPH03108767A true JPH03108767A (en) 1991-05-08

Family

ID=16615548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2212020A Pending JPH03108767A (en) 1990-08-09 1990-08-09 Display device

Country Status (1)

Country Link
JP (1) JPH03108767A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448612B1 (en) 1992-12-09 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor
US6853083B1 (en) 1995-03-24 2005-02-08 Semiconductor Energy Laboratory Co., Ltd. Thin film transfer, organic electroluminescence display device and manufacturing method of the same
JP2009501347A (en) * 2005-06-30 2009-01-15 セントレ・ナショナル・デ・ラ・レシェルシェ・サイエンティフィーク Flat display active plate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS615577A (en) * 1984-06-20 1986-01-11 Hitachi Ltd Thin film semiconductor device
JPS61193485A (en) * 1985-02-22 1986-08-27 Matsushita Electric Ind Co Ltd Manufacture of thin film transistor array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS615577A (en) * 1984-06-20 1986-01-11 Hitachi Ltd Thin film semiconductor device
JPS61193485A (en) * 1985-02-22 1986-08-27 Matsushita Electric Ind Co Ltd Manufacture of thin film transistor array

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448612B1 (en) 1992-12-09 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor
US6608353B2 (en) 1992-12-09 2003-08-19 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having pixel electrode connected to a laminate structure
US7045399B2 (en) 1992-12-09 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7061016B2 (en) 1992-12-09 2006-06-13 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7105898B2 (en) 1992-12-09 2006-09-12 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7547916B2 (en) 1992-12-09 2009-06-16 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US7897972B2 (en) 1992-12-09 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit
US8294152B2 (en) 1992-12-09 2012-10-23 Semiconductor Energy Laboratory Co., Ltd. Electronic circuit including pixel electrode comprising conductive film
US6853083B1 (en) 1995-03-24 2005-02-08 Semiconductor Energy Laboratory Co., Ltd. Thin film transfer, organic electroluminescence display device and manufacturing method of the same
US6992435B2 (en) 1995-03-24 2006-01-31 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, organic electroluminescence display device and manufacturing method of the same
US7476900B2 (en) 1995-03-24 2009-01-13 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, organic electroluminescence display device and manufacturing method of the same
JP2009501347A (en) * 2005-06-30 2009-01-15 セントレ・ナショナル・デ・ラ・レシェルシェ・サイエンティフィーク Flat display active plate

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