JPH03108378A - Variable capacity diode device - Google Patents
Variable capacity diode deviceInfo
- Publication number
- JPH03108378A JPH03108378A JP1246156A JP24615689A JPH03108378A JP H03108378 A JPH03108378 A JP H03108378A JP 1246156 A JP1246156 A JP 1246156A JP 24615689 A JP24615689 A JP 24615689A JP H03108378 A JPH03108378 A JP H03108378A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- layer
- diffusion
- variable capacitance
- diode device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 77
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 11
- 239000000377 silicon dioxide Substances 0.000 abstract description 11
- 239000004020 conductor Substances 0.000 abstract description 10
- 230000001681 protective effect Effects 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 239000000126 substance Substances 0.000 abstract 1
- 230000002500 effect on skin Effects 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05555—Shape in top view being circular or elliptic
-
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
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- H01—ELECTRIC ELEMENTS
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の産業上の利用分野〕
本発明は、高周波用に好適な同調用素子として用いられ
る可変容量ダイオード装置に関し、性能指数Qが高く、
容量可変比が大きな可変容量ダイオード装置に係るもの
である。[Detailed Description of the Invention] [Industrial Application Field of the Invention] The present invention relates to a variable capacitance diode device used as a tuning element suitable for high frequencies, and has a high figure of merit Q,
This relates to a variable capacitance diode device with a large variable capacitance ratio.
第5図a、bは、従来の可変容量ダイオード装置の平面
図と断面図を示している。FIGS. 5a and 5b show a plan view and a sectional view of a conventional variable capacitance diode device.
第5図a、bに於いて、半導体基体がN導電型であって
高不純物濃度の半導体基板(N”)10と、半導体基板
10にN導電型であって低不純物濃度のエピタキシャル
層(N−)20からなる半導体層とで構成されている。In FIGS. 5a and 5b, a semiconductor substrate (N") 10 whose semiconductor body is of N conductivity type and has a high impurity concentration, and an epitaxial layer (N") whose semiconductor substrate is of N conductivity type and has a low impurity concentration are formed on the semiconductor substrate 10. -) 20 semiconductor layers.
半導体基体の主表面からエピタキシャル層20にNi電
型であり高不純物濃度の拡散層(N” )30が半導体
基板IOに到達するように拡散形成されている。拡散層
30を覆うようにP導電型であって高不純物濃度の拡散
層(P”)40を拡散して接合J1を形成する。拡散工
程で半導体基体主表面に形成された二酸化シリコン膜は
、素子中央部においては除去され、主表面に露呈するP
N接合J、を覆う二酸化シリコン膜50は接合の保護膜
として残す。主表面露呈部には、アルミニューム等の導
電体膜60を被着形成して電極を形成する。この導電体
膜60に金線70をワイヤーボンディングして可変容量
ダイオード装置が形成される。A diffusion layer (N'') 30 of Ni conductivity type and high impurity concentration is diffused into the epitaxial layer 20 from the main surface of the semiconductor substrate so as to reach the semiconductor substrate IO. A junction J1 is formed by diffusing the diffusion layer (P'') 40 which is a type and has a high impurity concentration. The silicon dioxide film formed on the main surface of the semiconductor substrate in the diffusion process is removed in the center of the device, and the P exposed on the main surface is removed.
The silicon dioxide film 50 covering the N junction J is left as a protective film for the junction. A conductor film 60 made of aluminum or the like is deposited on the exposed portion of the main surface to form an electrode. A gold wire 70 is wire-bonded to this conductor film 60 to form a variable capacitance diode device.
高周波用の可変容量ダイオード装置では、最大容量値C
waxを数pF以下に設定しなければならない。即ち、
接合面積を極めて小さく設定する必要がある。例えばF
Mラジオ受信機用の可変容量ダイオード装置の為に調整
された製造工程で、最大容量値Cmaxが数pFのもの
を得ようとすると、第5図の従来例によれば、接合面積
S0の直径は、約80μmまで小さくする必要がある。In variable capacitance diode devices for high frequencies, the maximum capacitance value C
Wax must be set to several pF or less. That is,
It is necessary to set the bonding area extremely small. For example, F
When attempting to obtain a maximum capacitance value Cmax of several pF in a manufacturing process adjusted for a variable capacitance diode device for M radio receivers, according to the conventional example shown in Fig. 5, the diameter of the junction area S0 needs to be reduced to about 80 μm.
ところが接合面積に対してワイヤーボンデングの為の導
電体膜60の面積を、極めて広く形成する必要が生じる
。通常、金線70の金ボール71のサイズは、金線の面
形の3〜5倍程度の大きさとなり、金線の直径が25μ
mの場合、金ボールの直径が75〜125μmにもなり
、これに対応して導電体膜60の面積を設定しているの
が通例である。However, it becomes necessary to form the conductor film 60 for wire bonding in an extremely large area relative to the bonding area. Usually, the size of the gold ball 71 of the gold wire 70 is about 3 to 5 times the surface shape of the gold wire, and the diameter of the gold wire is 25 μm.
In the case of m, the diameter of the gold ball is 75 to 125 μm, and the area of the conductor film 60 is usually set correspondingly.
従来の可変容量ダイオード装置では、拡散層40の面積
がワイヤーボンディング時の金線が引き出されるキャピ
ラリの先端の面積より小さなものとなり、金線の熱圧着
時にその拡散層40にストレスが掛かることになる。又
、性能指数Qを劣化させることなく、容量可変比を可能
な限り大き′くとる為には、拡散層40の接合深さを浅
くする必要があり、通常、約0.1μm以下の浅い拡散
層となっている。In the conventional variable capacitance diode device, the area of the diffusion layer 40 is smaller than the area of the tip of the capillary from which the gold wire is drawn out during wire bonding, and stress is applied to the diffusion layer 40 during thermocompression bonding of the gold wire. . In addition, in order to make the capacitance variable ratio as large as possible without deteriorating the figure of merit Q, it is necessary to make the junction depth of the diffusion layer 40 shallow. It is layered.
近年、高周波用の可変容量ダイオード装置にあっては、
高い性能指数Qが要求されると共に、その容量値は、ま
すます小さいものが必要とされている。例えば、AMラ
ジオ等に使用されている可変容量ダイオード装置では最
大容量値C□8が、350〜650pF程度であるが、
UHFTV帯等のように使用周波数帯域が高くなるにつ
れて、可変容量ダイオード装置の最大容量値CmaNが
0.1〜15pF程度の特性のものが要求され、接合面
積は極めて小さなくなっている。第5図a、bの実施例
によれば、必要な最大容量値C1axを得る為の円柱状
に拡散された拡散層30の外周壁の面積は、極めて小さ
なものとなる。高周波の表皮効果から明らかなように拡
散層30の外周面積が小さい為に高周波抵抗が大きくな
り性能指数Qの低下をもたらす欠点がある。In recent years, in variable capacitance diode devices for high frequencies,
A high figure of merit Q is required, and the capacitance value is also required to be smaller and smaller. For example, in a variable capacitance diode device used in AM radio, etc., the maximum capacitance value C□8 is about 350 to 650 pF.
As the frequency band used becomes higher, such as the UHFTV band, a variable capacitance diode device is required to have a maximum capacitance value CmaN of about 0.1 to 15 pF, and the junction area becomes extremely small. According to the embodiments shown in FIGS. 5a and 5b, the area of the outer peripheral wall of the cylindrical diffused diffusion layer 30 to obtain the required maximum capacitance value C1ax becomes extremely small. As is clear from the skin effect of high frequencies, since the outer circumferential area of the diffusion layer 30 is small, the high frequency resistance increases, resulting in a decrease in the figure of merit Q.
又、ワイヤーボンディング時に、金ボールが導電体膜6
0からはみ出さないようにする必要があり、導電体膜の
面積は、接合面積に対して不必要な程極めて大きなもの
となる。従って、接合部から鍔状に延在している導電体
膜60とエピタキシャル層20との間に不要な浮遊容量
等が発生する場合があり、高周波特性に悪影響を与える
欠点がある。Also, during wire bonding, the gold ball is attached to the conductor film 6.
It is necessary to prevent the conductor film from protruding from 0, and the area of the conductor film becomes unnecessarily large compared to the bonding area. Therefore, unnecessary stray capacitance may occur between the epitaxial layer 20 and the conductive film 60 extending in the shape of a brim from the joint, which has the drawback of adversely affecting high frequency characteristics.
更に、高周波に対応すべく接合面積を小さく設定し、大
きな容量可変比を得る為に拡散層40の拡散深さを0.
1μm以下の掻めて浅いものとする為に、ワイヤーボン
ディング時、金線70を引き出すキャピラリをチップに
降下させて導電体膜60に金vA70を熱圧着させる際
に、キャピラリの先端部が接合面より大きいこともあっ
て、金線70の熱圧着時のストレスによって拡散層40
を破損するおそれがあり、ボンディング時にかなり多く
の不良を発生させる要因となっている。Furthermore, the junction area is set to be small to accommodate high frequencies, and the diffusion depth of the diffusion layer 40 is set to 0.0 to obtain a large variable capacitance ratio.
In order to make it shallower than 1 μm, during wire bonding, when lowering the capillary that pulls out the gold wire 70 onto the chip and thermocompression bonding the gold vA70 to the conductor film 60, the tip of the capillary is placed on the bonding surface. Because the gold wire 70 is larger in size, the stress during thermocompression bonding of the gold wire 70 causes the diffusion layer 40 to
There is a risk of damage to the bonding process, and this is the cause of a considerable number of defects during bonding.
本発明は、上述の如き欠点を改善する為になされたもの
で、その主な目的は、高周波特性が良好で容量可変比の
大きい可変容量ダイオード装置を提供することにある。The present invention has been made to improve the above-mentioned drawbacks, and its main purpose is to provide a variable capacitance diode device with good high frequency characteristics and a large variable capacitance ratio.
本発明の他の目的は、性能指数Qを向上させることので
きる可変容量ダイオード装置を提供することにある。Another object of the present invention is to provide a variable capacitance diode device that can improve the figure of merit Q.
本発明の他の目的は、ワイヤーボンディング時のストレ
スによって素子が破壊することのない構造を有する可変
容量ダイオード装置を提供することにある。Another object of the present invention is to provide a variable capacitance diode device having a structure in which the element is not destroyed by stress during wire bonding.
本発明の可変容量ダイオード装置は、上述の如き課題を
解消しようとするものであって、第1導電型の半導体基
板に形成された高比抵抗で第1導電型のエピタキシャル
層に、中空円柱状の第1導電型の第1の拡散層を形成し
、この第1導電型の第1の拡散層を覆うように浅く環状
に第2導電型の第2の拡散層を形成して接合を形成し、
該第2の拡散層の内側に位置する接合部を覆う第1の絶
縁膜層と、該第2の拡散層の外周部分の接合部を覆う第
2の絶縁膜層と、該第2の拡散層の主表面露呈部と該第
1の絶縁膜層を覆う導電体膜とを含むものである。The variable capacitance diode device of the present invention is intended to solve the above-mentioned problems, and has a hollow cylindrical shape formed in a high resistivity epitaxial layer of a first conductivity type formed on a semiconductor substrate of a first conductivity type. A first diffusion layer of a first conductivity type is formed, and a second diffusion layer of a second conductivity type is formed in a shallow annular shape so as to cover the first diffusion layer of a first conductivity type to form a junction. death,
a first insulating film layer covering a junction located inside the second diffusion layer; a second insulating film layer covering a junction at an outer peripheral portion of the second diffusion layer; It includes a main surface exposed portion of the layer and a conductive film covering the first insulating film layer.
本発明の可変容量ダイオード装置は、高比抵抗のエピタ
キシャル層に同一導電型の不純物元素を高濃度に拡散形
成した第1の拡散層の外周壁の面積を拡大するように中
空円柱状又は中空四角柱状とすることで、表皮効果に基
づく高周波抵抗の低下を妨げて性能指数Qを向上させ、
且つワイヤーボンディング時にキャピラリが半導体基体
の主表面を押圧する部分には、第1と第2の拡散層が形
成されない形状とすることにより、容量可変比を大きく
とるべく第2の拡散層を薄く形成したとしてもキャピラ
リの押圧によるストレスによって浅く形成された拡散層
を破壊することがない。The variable capacitance diode device of the present invention has a first diffusion layer formed by diffusing an impurity element of the same conductivity type in a high concentration into an epitaxial layer having a high specific resistance. By making it columnar, it prevents the drop in high frequency resistance based on the skin effect and improves the figure of merit Q.
In addition, the first and second diffusion layers are not formed in the portion where the capillary presses the main surface of the semiconductor substrate during wire bonding, so that the second diffusion layer is formed thin in order to increase the variable capacitance ratio. Even if this happens, the shallowly formed diffusion layer will not be destroyed by the stress caused by the pressure of the capillary.
第1図a、bは、本発明の可変容量ダイオード装置の一
実施例を示す図であり、第1図aが可変容量ダイオード
装置の平面図であって、第1図すがその断面図である。FIGS. 1a and 1b are views showing one embodiment of a variable capacitance diode device of the present invention, FIG. 1a is a plan view of the variable capacitance diode device, and FIG. 1 is a sectional view thereof. be.
第1図に於いて、半導体基体がN導電型であって高不純
物濃度の半導体基板(N”)1に、N導電型であって高
比抵抗のエピタキシャル層(N−)2が気相成長されて
形成されている。In Figure 1, an epitaxial layer (N-) 2 of N conductivity type and high resistivity is grown in vapor phase on a semiconductor substrate (N'') 1 of which the semiconductor substrate is of N conductivity type and has a high impurity concentration. has been formed.
そのエピタキシャル層2の半導体基体主表面からN4電
型であって高不純物濃度の環状或いは中空円柱状の拡散
層(N” )3を半導体基板1に到達する如く拡散形成
する。この拡散層3を覆うようにP導電型であって高不
純物濃度の拡散層(P”)4を環状に拡散形成して拡散
層3とエピタキシャル層2とによりPN接合J2を形成
する。拡散工程で形成された素子中央部を覆う二酸化シ
リコン膜であり、エピタキシャル層2と環状の拡散層4
とによって形成された中空円柱の内周に形成されるPN
接合の素子主表面露呈部と素子中央部を覆う二酸化シリ
コン膜5Iと、その中空円柱の外周に形成されるPN接
合が素子主表面に露呈する部分を覆う二酸化シリコン膜
5を保護膜として残す。二酸化シリコン膜が除去された
環状の拡散層4の露呈部と素子中央部の二酸化シリコン
膜5.の上にアルミニューム等の導電体膜6を被着して
電極を形成する。この導電体膜6にキャピラリから引き
出される金線7を熱圧着して接続し、金線7を外部リー
ド等に接続して可変容量ダイオード装置が形成される。From the main surface of the semiconductor substrate of the epitaxial layer 2, an annular or hollow cylindrical diffusion layer (N'') 3 of N4 type and high impurity concentration is diffused so as to reach the semiconductor substrate 1. A diffusion layer (P'') 4 of P conductivity type and high impurity concentration is formed in an annular shape so as to cover it, and a PN junction J2 is formed between the diffusion layer 3 and the epitaxial layer 2. This is a silicon dioxide film that covers the center of the device formed in a diffusion process, and includes an epitaxial layer 2 and an annular diffusion layer 4.
PN formed on the inner periphery of the hollow cylinder formed by
A silicon dioxide film 5I that covers the exposed part of the element main surface of the junction and the central part of the element, and a silicon dioxide film 5I that covers the part where the PN junction formed on the outer periphery of the hollow cylinder is exposed to the element main surface are left as protective films. The exposed portion of the annular diffusion layer 4 from which the silicon dioxide film has been removed and the silicon dioxide film 5 at the center of the element. A conductive film 6 made of aluminum or the like is deposited thereon to form an electrode. A gold wire 7 drawn out from the capillary is connected to this conductor film 6 by thermocompression bonding, and the gold wire 7 is connected to an external lead or the like to form a variable capacitance diode device.
一般に、可変容量ダイオード装置の最大容量値Cma*
は、接合面積Sと接合面の不純物濃度係数αの積で決定
される為に最大容量値Cmaxを小さくするには、接合
面積S又は不純物濃度係数αを小さくすればよい。最大
容量値Cmaxは、接合面積Sと接合面の不純物濃度係
数αの積とは、次のような関係にあり、
Cmax ocS cx −−−−−−−−−−=−
(1)この(1)式の関係より最大容量値Cmaxを小
さく、容量変化比を大きくとりたい場合は、P導電型の
拡散層4の接合深さを浅くすることと、接合面積S或い
は不純物濃度係数αを小さくする必要がある。しかし、
不純物濃度係数αを小さくすることは、半導体基板の不
純物濃度から限界がある。即ち、最小容量値Cm1nを
決める半導体基板の不純物濃度を低く調整して、半導体
基板のシート抵抗を大きくしようとすると性能指数Qの
低下を招く為に、半導体基板の不純物濃度を低く設定す
ることには限界がある。このような観点から、一般に最
大容量値Cmaxを小さくする為には、接合面積Sを小
さくすることが有効な手段となる。又、容量可変比を大
きくする為には、不純物濃度の制御には限界があるので
、接合の深さを浅く形成することで、表面と半導体基板
面の不純物濃度変化を大きくして容量可変比を大きくと
っている。Generally, the maximum capacitance value Cma* of a variable capacitance diode device
is determined by the product of the junction area S and the impurity concentration coefficient α of the junction surface. Therefore, in order to reduce the maximum capacitance value Cmax, the junction area S or the impurity concentration coefficient α can be decreased. The maximum capacitance value Cmax is the product of the junction area S and the impurity concentration coefficient α of the junction surface, and has the following relationship: Cmax ocS cx −−−−−−−−−−=−
(1) From the relationship in equation (1), if you want to reduce the maximum capacitance value Cmax and increase the capacitance change ratio, make the junction depth of the P conductivity type diffusion layer 4 shallow, and reduce the junction area S or impurity It is necessary to reduce the concentration coefficient α. but,
There is a limit to reducing the impurity concentration coefficient α due to the impurity concentration of the semiconductor substrate. That is, if an attempt is made to increase the sheet resistance of the semiconductor substrate by adjusting the impurity concentration of the semiconductor substrate, which determines the minimum capacitance value Cm1n, to a low value, the figure of merit Q will decrease, so it is decided to set the impurity concentration of the semiconductor substrate low. has its limits. From this point of view, reducing the junction area S is generally an effective means for reducing the maximum capacitance value Cmax. In addition, in order to increase the variable capacitance ratio, there is a limit to controlling the impurity concentration, so by forming a shallow junction, the change in the impurity concentration between the surface and the semiconductor substrate surface can be increased, and the variable capacitance ratio can be increased. It has a large value.
第1図の実施例では、エビタキャル層2を比較的高比抵
抗とし、そのエピタキシャル層2に表皮効果を考慮して
中空円柱状の拡散層3を形成する。最大容量値Ctma
xは、従来のものと等しく調整する場合、第1図の実施
例で第5図の従来例のものと同じ面積の接合面S、を形
成すればよ(、以下のように設定すればよい。第1図の
可変容量ダイオード装置の拡散層3の接合面積S、は、
次のように表される。In the embodiment shown in FIG. 1, the epitaxial layer 2 has a relatively high resistivity, and a hollow cylindrical diffusion layer 3 is formed in the epitaxial layer 2 in consideration of the skin effect. Maximum capacitance value Ctma
If x is adjusted to be equal to that of the conventional example, it is only necessary to form a joint surface S, which has the same area in the embodiment shown in FIG. 1 as that of the conventional example shown in FIG. The junction area S of the diffusion layer 3 of the variable capacitance diode device shown in FIG.
It is expressed as follows.
St =π(r、 t r −) 、−−−−−−・
−・−・(2)(但し、r、は外周円の半径、r2は内
周円の半径であり、キャピラリの寸法を考慮して設定す
る。)
因に、第5図の従来の可変容量ダイオード装置は、拡散
層30の表面の半径をr、とすれば、接合面積S0は、
次式のように表される。St = π(r, tr −) , −−−−−・
-・-・(2) (However, r is the radius of the outer circumferential circle, and r2 is the radius of the inner circumferential circle, which are set taking into consideration the dimensions of the capillary.) Incidentally, the conventional variable capacitance shown in Fig. 5 In the diode device, if the radius of the surface of the diffusion layer 30 is r, the junction area S0 is
It is expressed as the following formula.
S、=πr、2 ・・−・・・−・・−・−一−−−
−−・−−−−−−−・(3)従って、(2)式と(3
)式から、以下の関係式が得られる。S, = πr, 2 ・・−・−・・−・−1−−−
−−・−−−−−−−・(3) Therefore, equation (2) and (3
), the following relational expression is obtained.
πr32=π (r、! −r22)r3 =r I
−r z” −−−−−−−−−−(4)(4)式
のような関係に設定することで最大容量値Cmaxが第
5図のものと同じものが容易に形成できる。而も、中空
円柱状の拡散層3の外周縁の表面積が極めて拡大され、
表皮効果により高周波抵抗は小さくなり、性能指数Qを
劣化させることがない。むしろ高周波抵抗をより小さく
することで、性能指数Qをより向上させることが可能で
ある。πr32=π (r,!-r22)r3=r I
−r z” −−−−−−−−−−(4) By setting the relationship as shown in equation (4), it is possible to easily form a device with the same maximum capacitance value Cmax as that shown in FIG. 5. Also, the surface area of the outer periphery of the hollow cylindrical diffusion layer 3 is greatly expanded,
High frequency resistance becomes small due to the skin effect, and the figure of merit Q does not deteriorate. Rather, it is possible to further improve the figure of merit Q by making the high frequency resistance smaller.
更に、ワイヤーボンディング時にキャピラリで押圧され
る部分が、直径rtの円周内であるので、この部分を除
く外周に拡散層3,4が形成されるようになされており
、従って、ギヤピラリの押圧による接合の破壊が生じな
い。Furthermore, since the part pressed by the capillary during wire bonding is within the circumference of the diameter rt, the diffusion layers 3 and 4 are formed on the outer periphery excluding this part. No breakdown of the bond occurs.
第2図は、本発明の可変容量ダイオード装置の他の実施
例を示す平面図であり、第1図の実施例で拡散層3が一
重であるのに対して、二重にNi電型の拡散領域3I、
3□が形成されており、その拡散領域3I、3□を覆う
ようにP導電型の拡散N4が形成されている。尚、図示
されていないが二重以上に拡散層3を形成してもよい。FIG. 2 is a plan view showing another embodiment of the variable capacitance diode device of the present invention, in which the diffusion layer 3 is double in the embodiment of FIG. diffusion region 3I,
3□ is formed, and a P conductivity type diffusion N4 is formed to cover the diffusion regions 3I and 3□. Although not shown, the diffusion layer 3 may be formed in double or more layers.
このように拡散領域38,3□を形成することで表皮効
果に基づき一層高周波抵抗を低減でき、性能指数Qを向
上できると共に、ワイヤーボンディング時の金線の熱圧
着によって素子が破壊されることもない。By forming the diffusion regions 38, 3□ in this way, it is possible to further reduce the high frequency resistance based on the skin effect, improve the figure of merit Q, and prevent the element from being destroyed by thermocompression of the gold wire during wire bonding. do not have.
熱論、第3図に示すように第1図に示した拡散N3を、
平面図で四角形の拡散層33としても良いことは明らか
である。又、第2図の実施例のように四角形の拡散領域
33を二重に形成してもよいことは、明らかである。Thermal theory, as shown in Figure 3, the diffusion N3 shown in Figure 1 is
It is clear that the diffusion layer 33 may be rectangular in plan view. It is also obvious that the square diffusion regions 33 may be formed in duplicate as in the embodiment shown in FIG.
更に、第4図は、第1図に示した拡散N3を平面から見
て円周上に略円形の拡散領域を点在させるように拡散層
34を形成し、その拡散層3、を覆うようにP導電型の
拡散層4が形成された実施例である。Furthermore, FIG. 4 shows that the diffusion layer 34 is formed so that substantially circular diffusion regions are scattered on the circumference when the diffusion N3 shown in FIG. 1 is viewed from above, and that the diffusion layer 3 is covered. This is an example in which a P conductivity type diffusion layer 4 is formed.
本発明の可変容量ダイオード装置は、容量可変比を略決
定する拡散層が従来のように円柱状ではなく、ワイヤー
ボンディング時のストレスによる素子の破壊を防止すべ
く、環状又は中空円柱状であって外周壁面積を拡大する
ことが可能であるので、高周波抵抗が低減できると共に
性能指数Qを向上させることが可能である。而も、拡散
層を環状に形成することで、素子中央部には拡散層が形
成されていない為に、極めて浅(拡散層を形成すること
が可能であり、容量可変比を太き(することが可能であ
る。In the variable capacitance diode device of the present invention, the diffusion layer that approximately determines the variable capacitance ratio is not cylindrical as in the conventional case, but is annular or hollow cylindrical in order to prevent the element from breaking due to stress during wire bonding. Since it is possible to expand the area of the outer peripheral wall, it is possible to reduce high frequency resistance and improve the figure of merit Q. However, by forming the diffusion layer in an annular shape, since no diffusion layer is formed in the center of the element, it is possible to form an extremely shallow (diffusion layer), and the variable capacitance ratio can be made thick ( Is possible.
第1図aは、本発明の可変容量ダイオード装置の実施例
の平面図、第1図すは、本発明の可変容量ダイオード装
置の実施例の断面図、第2図乃至第4図は、第1図実施
例に示した拡散層の他の実施例を示す拡散層の平面図、
第5図aは、従来の可変容量ダイオード装置の例を示す
平面図、第5図すは、従来の可変容量ダイオード装置の
例を示す断面図である。
に半導体基板、 2:エピタキシャル層。
3.4:拡散層、5,5.:二酸化シリコン膜。
6:導電体膜、 7:金線FIG. 1a is a plan view of an embodiment of the variable capacitance diode device of the present invention, FIG. 1 is a sectional view of the embodiment of the variable capacitance diode device of the present invention, and FIGS. 1 is a plan view of a diffusion layer showing another embodiment of the diffusion layer shown in the embodiment;
FIG. 5a is a plan view showing an example of a conventional variable capacitance diode device, and FIG. 5 is a sectional view showing an example of a conventional variable capacitance diode device. 2: an epitaxial layer; 3.4: Diffusion layer, 5,5. : Silicon dioxide film. 6: Conductive film, 7: Gold wire
Claims (4)
形成された高比抵抗の第1導電型の半導体層と、該第1
導電型の半導体層より不純物元素が高濃度に拡散され、
該半導体層に中空円柱状を呈している第1導電型の第1
の拡散層と、中空円柱状の該第1の拡散層を覆うように
形成された浅い環状の第2導電型の第2の拡散層と、該
第2の拡散層に囲まれた半導体主表面と該半導体層と該
第2の拡散層とによって形成された半導体主表面に露呈
する内側の接合を覆う比較的厚い第1の絶縁膜と、半導
体主表面に露呈する該第2の半導体層と該第2の拡散層
とによって形成された接合と該接合の外周面を覆う第2
の絶縁膜とを含むことを特徴とする可変容量ダイオード
装置。(1) In a variable capacitance diode device, a high resistivity semiconductor layer of a first conductivity type formed on a semiconductor substrate;
Impurity elements are diffused at a high concentration from the conductive type semiconductor layer,
A first semiconductor layer of a first conductivity type having a hollow cylindrical shape is provided in the semiconductor layer.
a shallow annular second conductivity type second diffusion layer formed to cover the hollow columnar first diffusion layer, and a semiconductor main surface surrounded by the second diffusion layer. a relatively thick first insulating film covering an inner junction exposed at the semiconductor main surface formed by the semiconductor layer and the second diffusion layer; and the second semiconductor layer exposed at the semiconductor main surface. a bond formed by the second diffusion layer and a second diffusion layer covering the outer circumferential surface of the bond;
A variable capacitance diode device comprising an insulating film.
、前記第2の拡散層が該第1の拡散層を覆う環状の拡散
層であることを特徴とする可変容量ダイオード装置。(2) A variable capacitance diode device, wherein the first diffusion layer is formed in the shape of a plurality of hollow cylinders, and the second diffusion layer is an annular diffusion layer covering the first diffusion layer.
の拡散層が該第1の拡散層を覆う中空四角状を呈する拡
散層であることを特徴とする可変容量ダイオード装置。(3) the first diffusion layer has a hollow rectangular shape;
A variable capacitance diode device characterized in that the diffusion layer is a hollow rectangular diffusion layer that covers the first diffusion layer.
状に分布し、前記第2の拡散層が該第1の拡散層を覆う
ように環状を呈する拡散層であることを特徴とする可変
容量ダイオード装置。(4) The first diffusion layer is a diffusion layer in which columnar diffusion layers are distributed dotted around the circumference, and the second diffusion layer has an annular shape so as to cover the first diffusion layer. A variable capacitance diode device characterized by:
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1246156A JPH0644635B2 (en) | 1989-09-21 | 1989-09-21 | Variable capacitance diode device |
US08/076,024 US5338966A (en) | 1989-09-21 | 1993-05-27 | Variable capacitance diode device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1246156A JPH0644635B2 (en) | 1989-09-21 | 1989-09-21 | Variable capacitance diode device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03108378A true JPH03108378A (en) | 1991-05-08 |
JPH0644635B2 JPH0644635B2 (en) | 1994-06-08 |
Family
ID=17144330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1246156A Expired - Fee Related JPH0644635B2 (en) | 1989-09-21 | 1989-09-21 | Variable capacitance diode device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0644635B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100435189B1 (en) * | 2002-01-24 | 2004-06-09 | 정광석 | Custody case of fish hook |
-
1989
- 1989-09-21 JP JP1246156A patent/JPH0644635B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100435189B1 (en) * | 2002-01-24 | 2004-06-09 | 정광석 | Custody case of fish hook |
Also Published As
Publication number | Publication date |
---|---|
JPH0644635B2 (en) | 1994-06-08 |
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