JPH03106043A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03106043A
JPH03106043A JP1245527A JP24552789A JPH03106043A JP H03106043 A JPH03106043 A JP H03106043A JP 1245527 A JP1245527 A JP 1245527A JP 24552789 A JP24552789 A JP 24552789A JP H03106043 A JPH03106043 A JP H03106043A
Authority
JP
Japan
Prior art keywords
input
output circuit
circuit area
connection conductors
bonding pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1245527A
Other languages
Japanese (ja)
Inventor
Yoshitomo Numaguchi
沼口　喜伴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1245527A priority Critical patent/JPH03106043A/en
Publication of JPH03106043A publication Critical patent/JPH03106043A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered

Abstract

PURPOSE:To make it possible to uniformize the wiring length of the connection conductors between input/output circuits and bonding pads and to make it possible to widen easily the wiring width as well of the connection conductors by a method wherein the pads are arranged not only on the outer sides of input/output circuit regions but between an internal circuit region and the input/ output circuit regions. CONSTITUTION:An internal circuit region 2 is formed on the inner side of a semiconductor chip 1 and input/output circuit regions 3 are formed in such a way as to encircle the region 2. Bonding pads 4 are alternately arranged on the outer sides and the inner sides of the regions 3 and are connected with input/output circuits by pad connection conductors 5. Thereby, the wiring length of the connection conductors between the pads 4 and the input/output circuits can be uniformized and the wiring width of the connection conductors can be also easily widened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高集積化，多ビン化に有効な半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that is effective for high integration and multi-bin storage.

〔従来の技術〕゛ 従来、この種の半導体装置は第３図に示す様に入出力回
路領域の外側に千鳥にボンディングパッドを配していた
。[Prior Art] Conventionally, in this type of semiconductor device, bonding pads have been arranged in a staggered manner outside the input/output circuit area, as shown in FIG.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置は、ボンディングパッドが千
鳥に配される為、外側のボンディングバッドと入出力回
路間の配線は内側のボンディングバッドと入出力回路間
の配線に比べ距離が離れる上、内側のボンディングパッ
ド間を通さなければならない為、配線巾を太くしにくい
という欠点がある。In the conventional semiconductor device described above, the bonding pads are arranged in a staggered manner, so the wiring between the outer bonding pad and the input/output circuit is longer than the wiring between the inner bonding pad and the input/output circuit, and the wiring between the inner bonding pad and the input/output circuit is longer. The disadvantage is that it is difficult to increase the wiring width because it must pass between bonding pads.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、半導体チップの外周に形或され
る入出力回路領域と入出力回路領域の外側に形或される
ボンディングパッドと半導体チップの中央に形或される
内部回路領域、及び入出力回路領域と内部回路領域との
間に形戊されるボンディングパッドを有している。The semiconductor device of the present invention includes an input/output circuit area formed on the outer periphery of a semiconductor chip, a bonding pad formed outside the input/output circuit area, an internal circuit area formed in the center of the semiconductor chip, and an input/output circuit area formed on the outside of the input/output circuit area. A bonding pad is formed between the output circuit area and the internal circuit area.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明す゜る。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の第ｌの実施例である。FIG. 1 shows a first embodiment of the present invention.

半導体チップ１の内側に内部回路領域２が形戊され、そ
の内部回路領域２を取り巻くように人出力回路領域３が
形成される。ボンディングパッド４は前述入出力回路領
域３の外側と内側に交互に配置されパッド接続線５によ
って入出力回路と結線される。An internal circuit area 2 is formed inside the semiconductor chip 1, and a human output circuit area 3 is formed surrounding the internal circuit area 2. The bonding pads 4 are arranged alternately on the outside and inside of the input/output circuit area 3 and are connected to the input/output circuit by pad connection lines 5.

第２図は、本発明の第２の実施例である。木例ではポン
ディングバッド４は入出力回路領域３の外側と内側に２
：１の比で配置されている。FIG. 2 shows a second embodiment of the invention. In the tree example, there are two bonding pads 4 on the outside and inside of the input/output circuit area 3.
:1 ratio.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ボンディングパッドを入
出力回路領域の外側だけでなく内部回路領域と入出力回
路領域の間にも配することにより、入出力回路とボンデ
ィングパッド間の接続線の配線長を均一にでき、配線巾
も容易に広くできる効果がある。As explained above, the present invention enables wiring of connection lines between the input/output circuit and the bonding pad by arranging bonding pads not only outside the input/output circuit area but also between the internal circuit area and the input/output circuit area. This has the effect of making the length uniform and easily increasing the wiring width.

又、入出力回路領域の内側にもボンディングパッドがあ
るので内部回路と入出力回路の分離電源供給が容易にで
き、入出力回路領域がより外周部に形戒されるので配置
できる入出力回路数を増すことができる効果もある。In addition, since there are bonding pads inside the input/output circuit area, it is easy to separate the power supply between the internal circuit and the input/output circuit, and the input/output circuit area is more closely spaced on the outer periphery, reducing the number of input/output circuits that can be placed. It also has the effect of increasing the

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例の平面図、第２図は第２
の実施例の平面図、第３図は従来例の平面図である。 １・・・・半導体チッフ、２・・・・・・内部回路領域
、３・・・・入出力回路領域、４・　・・ボンディング
パッド、５・・・・・・パッド接続線。FIG. 1 is a plan view of a first embodiment of the present invention, and FIG. 2 is a plan view of a second embodiment of the present invention.
FIG. 3 is a plan view of the conventional example. 1... Semiconductor chip, 2... Internal circuit area, 3... Input/output circuit area, 4... Bonding pad, 5... Pad connection line.

Claims (1)

【特許請求の範囲】[Claims] 半導体チップ外周部に入出力回路領域を配した半導体装
置において、ボンディングパッドを入出力回路領域の外
側だけでなく、内側の内部回路領域と外側の入出力回路
領域の間にも配することを特徴とする半導体装置。In a semiconductor device in which an input/output circuit area is arranged on the outer periphery of a semiconductor chip, bonding pads are arranged not only outside the input/output circuit area but also between the inner internal circuit area and the outer input/output circuit area. semiconductor device.
JP1245527A 1989-09-20 1989-09-20 Semiconductor device Pending JPH03106043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1245527A JPH03106043A (en) 1989-09-20 1989-09-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1245527A JPH03106043A (en) 1989-09-20 1989-09-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03106043A true JPH03106043A (en) 1991-05-02

Family

ID=17135015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1245527A Pending JPH03106043A (en) 1989-09-20 1989-09-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03106043A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130484A (en) * 1997-07-17 2000-10-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
WO2001050526A1 (en) * 1999-12-30 2001-07-12 Intel Corporation Optimized driver layout for integrated circuits with staggered bond pads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130484A (en) * 1997-07-17 2000-10-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
WO2001050526A1 (en) * 1999-12-30 2001-07-12 Intel Corporation Optimized driver layout for integrated circuits with staggered bond pads

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