JPH03105967A - Input/output protective circuit of semiconductor device - Google Patents

Abstract

PURPOSE:To arrange that a MOS transistor of an input/output protective circuit is easy to punch through and that an input/output protective circuit and an internal circuit are hard to destroy by a method wherein a gate length of a MOS transistor used for an input/output protective circuit is formed to be shorter than a gate length of a MOS transistor used for an internal circuit. CONSTITUTION:An enhancement-type N-channel MOS transistor TrNa is formed on a P-type silicon substrate 1; an enhancement-type P-channel MOS transistor TrPa is formed on an N-well 8 formed on a P-type silicon substrate 1; P<+> diffusion layers 6 and N<+> diffusion layers 7 are formed on the substrate 1 and N- wells 8; a field oxide film 2 is formed as an insulating isolation film of the diffusion layers 6, the diffusion layers 7, the TrPa and the TrNa. The TrPa and the TrNa have gate electrodes 9 whose gate lengths LPa, LNa are shorter than a gate length of an internal circuit; aluminum interconnections 4 are connected to the diffusion layers 6, the diffusion layers 7 and the gate electrodes 9 at prescribed parts via contact holes 5 formed in an interlayer insulating film 3.

Description

[Detailed description of the invention] r Industrial application field] The present invention relates to an input/output protection circuit for a semiconductor device.

[Prior Art] An input/output protection circuit conventionally used in a MOS type semiconductor device will be described below with reference to FIGS. 5 and 6.

FIG. 5(a) is a plan view of a conventional input/output protection circuit,
FIG. 5(b) is an equivalent circuit diagram. Also, Figure 5 (C)
, FIG. 5(d) is a cross-sectional view taken along line A-A' in FIG. 5(a), and B
-B' line sectional view.

A P-type silicon substrate 1 is provided with an enhancement I type N-channel MOS transistor Tr. A P-channel MOS transistor Trρ is formed in the N well 8 formed in the P-type silicon substrate l.
A P+ diffusion layer 6 and an N+ diffusion layer 7 are formed on the substrate 1, N-) layer 8, and a field oxide film 2 is formed as an insulating separation film for the diffusion layer 6, the diffusion layer 7, and TrP and TrN. It has been pierced. Trp and TrN have gate electrodes 9 of the same length as the internal circuit, LP and LN, and the aluminum wiring 4 connects contacts 1 to holes 5 provided in the interlayer insulating film 3.
It is connected to the diffusion layer 6, the diffusion layer 7, and the gate electrode 9 at predetermined locations via.

The power supply 10 is connected to the N1 diffusion layer 7 formed in the N well 8 (so-called well contact), and is connected to the P+ diffusion layer 6 of T r p forming the diffused resistor R3, and through this diffused resistor R3. It is connected to the gate electrode 9 of.

The ground (GND) 12 is connected to the P diffusion layer 6 formed on the substrate 1 (so-called sub-contact I-), and connected to the N+ diffusion layer 7 of T r N forming the diffusion resistor R4.
Tr. It is connected to the gate I electrode 9 of.

The board member 11- is a diffusion resistor R1. , R2 through the diffusion layers 6 and 7 of Trp , Tr, ,
Connected to internal circuit.

When excessive voltage is applied to boarding pad 11#
．． By flowing current to T r p and T r N, the influence on the internal circuit is reduced. Furthermore, the diffused resistors R 1 , R 2 , R 3 , and Ra protect T r p and T l-N from momentarily applied excessive voltages.

FIGS. 6(a) and 6(b) are circuit diagrams in which a conventional input/output protection circuit is connected to a gate and a diffusion layer of an internal circuit.

For example, in FIG. 6 (a>.(b), for the power supply 10, the bonding pad 11 is
Vtpl) (where ■TP is the threshold voltage of Trp) or more is applied, Trp becomes conductive and protects the internal circuit. Furthermore, [power supply voltage l BVo
sp I ) (However, for BVDSP, even if a voltage below the drain-source breakdown voltage of T r p is applied), T
rp becomes conductive to protect the internal circuit.

Also, for GND 1 2, bonding pad 11
A voltage higher than BVDSN (BVDSN is the drain-source breakdown voltage of T r N) or (GND
When a voltage lower than the voltage -VTN) (where VTN is the threshold voltage of TrN) is applied, Tr+y becomes conductive to protect the internal circuit.

Here, the gate lengths and threshold voltages of P-channel MOS transistors T r pH and T r P2 in the internal circuit are the same values LP and VTR as Trp in the human output protection circuit, and Transistor T rNl. T r N2 game 1 to long, Shikiichi,
The voltage is also Trl. of the input/output protection circuit. The same value T-N.l. V
It is TN.

[Problem to be solved by the invention]

The gate length and threshold voltage of the MOS type I transistor used in the input/output protection circuit of the conventional MOS type semiconductor device described above are the gate length and threshold voltage of the MOS type transistor used in the internal circuit. The 1-rain-source breakdown voltage of these MOS transistors is the breakdown voltage due to electric field concentration generated in the channel portion near the drain. In other words, if the train voltage is greatly changed, punch-through will not occur between the drain and source due to the depletion layer extending from the train.

This is to prevent malfunction of the internal circuit due to 1. transistor leakage current and to reduce power consumption.

Breaker width voltage depends on gate oxide film thickness, channel area,
Depending on the impurity profile of the drain diffusion layer, typically
It is more than ten volts.

As shown in Figure 6(b), the human output protection circuit? When connected to the diffusion layer of the internal circuit, when a positive voltage of less than BVoslv of the TrN is applied to the bonding pad 1l with respect to the ground] 2, since the TrN is in the OFF state,
Depending on the operating state of T r p2 and T r N2 (determined by gate voltage levels X and Y), the diffusion resistance R,...
A current flows to the power supply 10 or ground 12 through R2 and T r p or T r N2.

As a result, current concentration occurs in the P+ diffusion layer 6 shown in FIG. 5(c) and the N+ diffusion layer 7 shown in FIG. 5(d).
A disadvantage is that thermal destruction of the diffusion layer occurs.

[Means to solve the problem]

In the input/output protection circuit of a semiconductor device of the present invention, the gate length of the MOS transistor used in the input/output protection circuit is made shorter than the gate length of the MOS transistor used in the internal circuit.

1. Example] Next, the present invention will be explained with reference to the drawings, as shown in Fig. 1 (
a) is a plan view of the first embodiment of the present invention, FIG. 1(b) is an equivalent circuit diagram of the first embodiment, FIG. 1(C), FIG.
) are a sectional view taken along line AA' and sectional view taken along line BB' of FIG. 1 (a).

An enhancement type N-channel MOS type 1 to a transistor Tr'Na is formed on the P-type silicon substrate 1, and an N-well 8 formed on the P-type silicon substrate 1 is formed with a
Hensionment type P-channel MOS transistor T
rp, and a P+ diffusion layer 6 in the substrate 1N well 8.
and N+ diffusion layer 7 are formed, and diffusion layer 6, diffusion layer 7 and T r Pa +TrN. A field oxide film 2 is formed as an insulating isolation film. T r Ps.
T r Na is the gate length L p , L N of the internal circuit
It has a gate 1 and an electrode 9 with a shorter gate length LPa+LNa, and the aluminum wiring 4 is connected to the diffusion layer 6, the diffusion layer 7, and the gate 1 to the electrode through the contact 1 and hole 5 provided in the interlayer insulating film 3. Connected at designated points.

The power supply 10 is connected to the N+ diffusion layer 7 formed in the N well 8 (so-called well contact), and is connected to the P'' diffusion layer 6 of Trpa forming the diffusion resistance R3.
3 via Trp. It is connected to the gate I electrode 9 of.

The ground (GND) 12 is connected to the P+ diffusion layer 6 formed on the substrate 1 (so-called sub-contact 1~), and is connected to the TrNa N diffusion layer 7 forming the spreading resistance R4. via TrN. It is connected to the gate electrode 9 of.

The bonding pad 11 has a Trp. , T rN. Through the diffusion layer 6.7 of
Connected to internal circuit.

In this embodiment, the gate length 1-p, , LNs of T rPa, T rNa is the gate length L p of the internal circuit,
By making it shorter than L N, T r . p@, T
r Drain-source breakdown voltage of Ni1 I B V os
p-l, B V osl. I. is the train-source breakdown voltage I BVospl . of the internal circuit. BVos
It becomes lower than u, making punch-through more likely to occur. Third
The figure shows an example of the relationship between gate length and BVD5. As is clear from this figure, in the P-channel MOS type L transistor, the gate I length is LP<1. ．． In the case of an N-channel MOS transistor, LN<1.15 μm, and the drain-source breakdown voltage is determined by punch-through.

Figure 2(a). (b) is a circuit diagram when the input/output conservation circuit of this embodiment is connected to the gate 1 and gate 2 diffusion layers of the internal circuit. T r PI, T r p2. T r Nl
．． and the gate length of TrN2 is 1.5 μm, LPa
And when LNa is 1.1 μm and 1.0 μm,
In the internal circuit, l BVosp l. BVDSN≧1
2 volts, input/output protection circuit, l B V osp.
l, BVosN-Sait becomes 7 volts. At this time, even in the case of the circuit connection shown in Fig. 2(b), the conventional R
、． Current concentration in the diffusion layer constituting R2 does not occur.

In addition, at this time, l B V ospSl , B V
The value of DSN- is the absolute value of the power supply voltage (for example, 5 volts)
If it is larger, under normal conditions T r Pa + T r
Punch-through of Na does not occur, and in this case, power consumption does not increase.

A second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view of an N-channel MOS type transistor.

? In Example 1, the gate length of the MOS transistor was directly changed, but in this example, the N of the input/output protection circuit was changed directly.
By changing the N+ diffusion R7 of the channel MOS type transistor to the N+ diffusion layer 7a depending on the ion implantation conditions and heat treatment conditions, and changing the diffusion layer depth x and ■ to XJN2, the effective gate length LNe4fl can be obtained without changing the gate length LN.
is changed to LNerr2 to make it easier to cause bunch-through.

This also applies to the P+ diffusion layer 6 of the P channel MOS type transistor of the input/output protection circuit.

〔Effect of the invention〕

As explained above, the present invention makes the gate length of the MOS transistor used in the input/output protection circuit shorter than that of the MOS transistor used in the internal circuit. It is possible to make bunch-through easier and to make it less likely that the input/output protection circuit and internal circuit will be destroyed.

[Brief explanation of drawings]

Fig. 1(a) is a plan view of an embodiment of the present invention, Fig. 1(b) is an equivalent circuit diagram, Fig. 1(c) and (d) are sectional views, and Fig. 2(a). (b) is a circuit diagram in which the first embodiment is connected to the internal circuit, FIG. 3 is a characteristic diagram of the gate length and drain-source breakdown voltage of the MOS transistor of the first embodiment, and FIG.
The figure is a sectional view of the second embodiment of the present invention, FIG. 5(a) is a plan view of the prior art, FIG.
c). (d) is a cross-sectional view, and FIG. 6 (a>. (b) is a circuit diagram in which the first embodiment is connected to an internal circuit. ■...P-type silicon substrate, 2... Field oxide film , 3... Interlayer insulating film, 4... Aluminum wiring, 5...
Contact hole, 6...P+ diffusion layer, 7.7a...
・N+ diffusion layer, 8... N well, 9... gate electrode, 10... power supply, 11... bonding path,
12...Ground (GND). Trp, Trp■, Trp2・-P channel M O
S type I transistor. T r N , T r Nl. '1" r N2-
N-channel MOS transistor. Rl, R2, R3 + R4... Diffused resistance. XJNI. XjN2...Diffusion layer depth of N+ diffusion layer. Lp, Lp1... Gate length of P channel MOS type transistor, LN, LN1... Gate length of N channel MOS type transistor. L Nerfl T L Netrz ・” Effective gate length of N-channel MOS type transistor. X, Y... Gate voltage level of T rP2, T rv2.

Claims (1)

[Claims] An input/output protection circuit for a semiconductor device, wherein a gate length of a MOS transistor used in the input/output protection circuit is formed shorter than a gate length of a MOS transistor used in an internal circuit of the semiconductor device. input/output protection circuit.