JPH03105929A - Manufacture of schottky barrier junction gate type field-effect transistor - Google Patents
Manufacture of schottky barrier junction gate type field-effect transistorInfo
- Publication number
- JPH03105929A JPH03105929A JP24418989A JP24418989A JPH03105929A JP H03105929 A JPH03105929 A JP H03105929A JP 24418989 A JP24418989 A JP 24418989A JP 24418989 A JP24418989 A JP 24418989A JP H03105929 A JPH03105929 A JP H03105929A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode
- gate
- gate electrode
- photo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004888 barrier function Effects 0.000 title claims description 6
- 230000005669 field effect Effects 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000001039 wet etching Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- 238000012356 Product development Methods 0.000 description 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- UUWCBFKLGFQDME-UHFFFAOYSA-N platinum titanium Chemical compound [Ti].[Pt] UUWCBFKLGFQDME-UHFFFAOYSA-N 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
し産業上の利用分野〕
本発明は高出力用のガリウム砒素ショットキー障壁ゲー
ト型電界効果トランジスタの装道方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for mounting a high-output gallium arsenide Schottky barrier gate type field effect transistor.
１従来の技術〕
ガリウム砒素ショットキー障壁ゲート型電界効東トラン
ジスタ（ Ｇ ａ Ａ ｓ−Ｍ Ｅ Ｓ Ｆ Ｅ Ｔ
）は、高周波特性に優れているので、高周波増幅素子を
始めとして、製品開発が進められている。1. Prior art] Gallium arsenide Schottky barrier gate field effect transistor (GaAs-MESFET)
) has excellent high-frequency characteristics, so product development is progressing, including high-frequency amplification elements.
従来技術によるＧａＡｓ−ＭＥＳＦＥＴについて、第３
図を参照して説明する。About GaAs-MESFET according to the conventional technology, Part 3
This will be explained with reference to the figures.
半絶縁性ガリウム砒素基板１の表面に、キャリア濃度Ｉ
Ｘ １ ０ ”ｃ ｍ−’、厚さ２０００人のＮ型チ
ャネル層２を挟んでキャリア濃度３Ｘ１０”ｃｍ−’、
厚さ３０００人のＮ型低抵抗層８が形戒され、Ｎ型チャ
ネル層２とショットキー接合をなす厚さ６０００人の高
融点金属、たとえばタングステンシリサイド（ＷＳｉ＞
からなるゲート電極３と、Ｎ型低抵抗層８とオーミック
接合をなすソース電極１１、ドレイン電極１２とが形成
されている。On the surface of the semi-insulating gallium arsenide substrate 1, there is a carrier concentration I
X 10 "cm-', carrier concentration 3X10"cm-' across the N-type channel layer 2 with a thickness of 2000 people,
An N-type low resistance layer 8 with a thickness of 3000 nm is formed, and a high melting point metal such as tungsten silicide (WSi>
A source electrode 11 and a drain electrode 12 forming an ohmic contact with the N-type low resistance layer 8 are formed.
一般にＧ ａ Ａ ｓ Ｍ Ｅ Ｓ Ｆ Ｅ Ｔは、
ソース電極１１を接地し、ドレイン電極１２を正電位に
し、ゲーＩ−電極３を負電位にバイアスして使用される
。In general, G a As M E S F E T is
The source electrode 11 is grounded, the drain electrode 12 is set to a positive potential, and the gate I-electrode 3 is biased to a negative potential.
このときゲート電ｆＪｉ３とドレイン電極１２との間に
臨界電圧以上の電圧が印加されると、ドレイ〉・電極１
２からゲート電極３に電流が流れてしまうため、ドレイ
ン電極１２に印加できる電圧は臨界電圧による制限を受
ける。At this time, if a voltage higher than the critical voltage is applied between the gate voltage fJi3 and the drain electrode 12, the drain>・electrode 1
Since current flows from the drain electrode 2 to the gate electrode 3, the voltage that can be applied to the drain electrode 12 is limited by the critical voltage.
この臨界電圧はゲート耐圧と称されており、特に高出力
用のＧ ａ Ａ ｓ − Ｍ Ｅ Ｓ Ｆ Ｅ Ｔにと
っては、このゲート耐圧の向上が出力電力限界および信
頼度の向上などの性能向上のために重要である。This critical voltage is called the gate withstand voltage, and especially for high-output GaAs-MESFETs, improving the gate withstand voltage improves performance such as improving the output power limit and reliability. It is important for
しかしながら従来技術によるＧａＡｓ−ＭＥＳＦＥＴで
は、キャリア濃度が３Ｘ１０ｌ７ｃｍ−’と高いＮ型低
抵抗層８がゲー１ヘ電極３に接して設けられている。However, in the GaAs-MESFET according to the prior art, an N-type low resistance layer 8 having a high carrier concentration of 3.times.1017 cm.sup.-' is provided in contact with the gate electrode 3.
そのためゲート耐圧が８■という小さいものしか得られ
ず、高出力用ＧａＡｓ−ＭＥＳＦＥＴとして機能させる
には不十分であった。Therefore, the gate breakdown voltage was only as low as 8 .mu., which was insufficient to function as a high-output GaAs-MESFET.
本発明の目的はゲート耐圧を高くして、出力電力限界お
よび信頼度を向上させるとともに、ソース抵抗、ゲート
抵抗を低減して、遮断周波数、電力付加効率などの向七
を実現するものである。An object of the present invention is to increase the gate breakdown voltage to improve the output power limit and reliability, and to reduce the source resistance and gate resistance to achieve improvements in cutoff frequency, power addition efficiency, etc.
本発明のショットキー障壁接合ゲート型電界効果トラン
ジスタの製造方法は、トレイン側のゲート電ｉｕ面に第
１の絶縁膜を形成する工程と、前記ゲー１〜電極と第１
の絶縁膜とをマスクとして、Ｎ型不純物をイオン注入す
る工程と、ソース側のゲート電極側面とドレイン側の第
１の絶縁膜の側面とに第２の絶縁膜を形成する工程と、
前記ゲート電極、第１の絶縁膜と第２の絶縁膜とをマス
クとして、Ｎ型不純物をイオン注入する工程と、イオン
注入された不純物を活性化するためのアニール工程と、
ソース−ドレイン電極を形成する工程とから構成されて
いる。The method for manufacturing a Schottky barrier junction gate field effect transistor of the present invention includes the steps of forming a first insulating film on the gate electrode iu surface on the train side,
using the insulating film as a mask, ion-implanting N-type impurities; forming a second insulating film on the side surface of the gate electrode on the source side and the side surface of the first insulating film on the drain side;
A step of ion-implanting N-type impurities using the gate electrode, the first insulating film, and the second insulating film as masks, and an annealing step for activating the ion-implanted impurities.
The process consists of a step of forming source-drain electrodes.
Ｌ実施例〕
本発明の第１の実施例について、第１図（ａ）〜（ｉ＞
を参照して説明する。L Example] Regarding the first example of the present invention, FIGS. 1(a) to (i>
Explain with reference to.
はじめに第１図（ａ）に示すように、半絶縁性Ｇ ａＡ
ｓ基板１の表面にキャリア濃度Ｉ Ｘ １ ０ ”ｃ
ｍ−３、深さ０．２ｕｍのＮ一型チャネルＭ２を形成し
、これとショットキー接合をなす、たとえば厚さ６ ０
０ ０人のタングステンシリサイドからなるゲー１〜
電極３を形成し、全面に厚さ４ ０ ０ ０人の第１の
絶縁膜（例えばＣ Ｖ Ｄ Ｓ ｉ Ｏ ２膜）４を
堆積したのち、第１のフォトレジスト５を形吠する。First, as shown in Figure 1(a), semi-insulating GaA
The carrier concentration I
m-3, a depth of 0.2 um N-type channel M2 is formed, and a Schottky junction is formed with this, for example, a thickness of 60 um.
Game 1 consisting of 0 0 tungsten silicides
After forming an electrode 3 and depositing a first insulating film (for example, a C V D Si O 2 film) 4 to a thickness of 4000 on the entire surface, a first photoresist 5 is formed.
つぎに第１図（ｂ）に示すように５第１のフォトレジス
ト５をマスクとして、ＲＩＥ法により第１の絶縁膜４を
エッチングしたのち、第１のフォトレジスト５を除去し
て、ソース側のゲー１・電極３の側壁に第１の絶縁膜４
ａを残す。Next, as shown in FIG. 1(b), the first insulating film 4 is etched by RIE using the first photoresist 5 as a mask, and then the first photoresist 5 is removed and the source side A first insulating film 4 is formed on the side wall of the gate 1 and electrode 3.
Leave a.
つぎに第１図（Ｃ）に示すように、第２のフォトレジス
ト６を形成する。Next, as shown in FIG. 1(C), a second photoresist 6 is formed.
つぎに第１図（ｄ）に示すように、第２のフォトレジス
ト６をマスクとして、ＲＩＥ法により第■の絶縁膜４を
エッチングしたのち、第２のフォトレジスト６を除去し
て、トレイン測のゲー１〜電極側壁に第１の絶縁膜４ｂ
を残す。Next, as shown in FIG. 1(d), the second insulating film 4 is etched by RIE using the second photoresist 6 as a mask, and then the second photoresist 6 is removed and the train measurement is performed. A first insulating film 4b is formed on the sidewalls of the electrodes 1 to 1.
leave.
つぎに第１図（ｅ）に示すように、Ｎ型低抵抗層８を形
成するために、ゲーＩ−電極３および第１の絶縁膜４を
マスクとして、Ｎ型不純物（例えばシリコン）を加速エ
ネルギー５０ｋｅＶ、注入量（ドース） Ｉ Ｘ １
０ｌ２／ｃｍ２イオン注入する。Next, as shown in FIG. 1(e), in order to form an N-type low resistance layer 8, an N-type impurity (for example, silicon) is accelerated using the gate I-electrode 3 and the first insulating film 4 as a mask. Energy 50 keV, implantation amount (dose) I x 1
0l2/cm2 ion implantation.
つぎに第１図（ｆ＞に示すように、全面に厚さ３０００
人の第２の絶縁膜（例えばＣＶＤ−ＳｉＯ２膜）７を堆
積する。Next, as shown in Figure 1 (f>), a thickness of 3000 was applied to the entire surface.
A second insulating film (eg, CVD-SiO2 film) 7 is deposited.
つぎに第１図（ｇ＞に示すように、ＲＩＥ法により第２
の絶縁膜７を工・ソチングして、第２の絶縁膜７からな
る側壁７ａを残す。Next, as shown in Figure 1 (g>), a second
The insulating film 7 is etched and sown, leaving side walls 7a made of the second insulating film 7.
つぎに第１図（ｈ）に示すように、Ｎ＋型オーミック層
９を形成するために、ゲート電ｆｉ３および第１、第２
の絶縁膜４ｂ，７ａをマスクとしてて、Ｎ型不純物（例
えばシリコン〉を加速エネルギー１ ５０ｋｅＶ、注入
量（ドース）ＩＸＩＯＩＳ・’ｃｍ２イオン注入ずる。Next, as shown in FIG. 1(h), in order to form the N+ type ohmic layer 9, the gate voltage fi3 and the first and second
Using the insulating films 4b and 7a as masks, N-type impurity (for example, silicon) ions are implanted at an acceleration energy of 150 keV and a dose of IXIOIS.cm2.
このあとイオン注入された不純物を活性化する六二めに
、例えばアノレシン（Ａｓｌ−１３）ガス中でアニール
を行なう。Thereafter, to activate the ion-implanted impurities, annealing is performed in, for example, anolescine (Asl-13) gas.
つぎに第１図（ｉ）に示すように、ゲーｌ・電極３の上
にチタンー白金一金（Ｔｉ−Ｐｔ−Ａｕ＞からなる金属
配線１０を設けたのち、ソース電極１１およびドレイン
電極１２を形成して、Ｇ ａ Ａｓ−Ｍ Ｅ Ｓ Ｆ
Ｅ Ｔが完戊する。Next, as shown in FIG. 1(i), a metal wiring 10 made of titanium-platinum (Ti-Pt-Au) is provided on the gate electrode 3, and then a source electrode 11 and a drain electrode 12 are formed. to form GaAs-MESF
ET is completed.
つぎに本発明の第２の実施例について、第２図（ａ）〜
（ｅ）を参照して説明する。Next, regarding the second embodiment of the present invention, FIGS.
This will be explained with reference to (e).
はじめに第２図＜ａ＞に示すように、半絶縁性Ｇ ａＡ
ｓ基板１の表面にＮ一型チャネルＮ２を形成し、ゲー
ト電極３を形成し、全面に第１の絶縁１漠４を堆積した
のち、第１のフォトレジスト５を形成する。First, as shown in Figure 2<a>, semi-insulating GaA
An N1 type channel N2 is formed on the surface of the s-substrate 1, a gate electrode 3 is formed, a first insulating film 4 is deposited on the entire surface, and a first photoresist 5 is formed.
つぎに第２図（ｂ）に示すように、ＲＩＥ法により第１
の絶縁膜４をエッチングしてゲート電極の側壁４ａ．４
ｂを残す。Next, as shown in Figure 2(b), the first
The insulating film 4 of the gate electrode is etched to form side walls 4a. 4
Leave b.
つぎに第２図（ｃ）に示すように、ドレイン側を覆う第
２のフォトレジストｌ２を形成する。Next, as shown in FIG. 2(c), a second photoresist 12 covering the drain side is formed.
つぎに第２図（ｄ）に示すように、第２のフォトレジス
ト６をマスクとして、ウェットエッチングにより第１の
絶縁膜４をエッチングして、トレイン側のゲート電極側
壁４ｂを残してから、フォトレジスト１２を除去する
つぎに第２図（ｅ）に示すように、Ｎ型低抵抗層８とＮ
＋型オーミック層９とを形戒したのち、ゲー１〜電極３
の上に金属配線１０を形成し、ソース電極１１およびド
レ，イン電極１２を形戒して、Ｇａ Ａ ｓ 一Ｍ Ｂ
Ｓ Ｆ Ｅ Ｔが完成する。Next, as shown in FIG. 2(d), the first insulating film 4 is etched by wet etching using the second photoresist 6 as a mask, leaving the gate electrode sidewall 4b on the train side, and then photoresist 6 is used as a mask. After removing the resist 12, as shown in FIG. 2(e), the N-type low resistance layer 8 and the N-type
After forming the + type ohmic layer 9, the electrodes 1 to 3
A metal wiring 10 is formed on the metal wiring 10, a source electrode 11 and drain and inlet electrodes 12 are formed, and Ga
SFET is completed.
本発明のＧａＡｓ−ＭＥＳＦＥＴの製造方法は、キャリ
ア濃度の高いドレイン側のＮ型低抵抗層をゲート電極端
から離すことができるため、ゲート耐圧が高く（例えば
第１の実施例では１５Ｖ）、シかもソース抵抗は小さい
（例えば０．８Ω・ｍｍ）ＧａＡｓ−ＭＥＳＦＥＴを得
ることができた９
特に第２の実施例においては、半絶縁性Ｇ ａ ＡＳ基
板１の表面が、ほとんどＲＩＥ法によるエッチングのプ
ラズマ雰囲気にさらされないため、表面損傷の影響が少
ないという特徴がある。In the GaAs-MESFET manufacturing method of the present invention, the N-type low resistance layer on the drain side with high carrier concentration can be separated from the end of the gate electrode, so the gate breakdown voltage is high (for example, 15V in the first embodiment) and the silicon In addition, we were able to obtain a GaAs-MESFET with a low source resistance (for example, 0.8 Ω·mm).9 Especially in the second embodiment, the surface of the semi-insulating Ga AS substrate 1 was almost completely etched by the RIE method. Since it is not exposed to a plasma atmosphere, it has the characteristic of being less susceptible to surface damage.
第１図＜ａ）〜（ｉ）は本発明の第１の実施例を工程順
に示す断面図、第２図（ａ）〜（ｅ）は本発明の第２の
実施例を工程順に示す断面図、第３図は従来技術による
Ｇ ａ Ａ ｓ Ｍ Ｅ Ｓ Ｆ Ｅ Ｔを示す断面
図。
１・・・半絶縁性ＧａＡｓ基板、２・・Ｎ型チャネル層
、３・・・ゲーｌ〜電極、４・・・第１の絶縁膜、４ａ
，４ｂ・・・側壁、５・・・第１のフォトレジスト、６
・・・第２のフォトレジス？−、７・・・第２の絶縁膜
、７ａ・・＋１１Ｊ壁、８・・・Ｎ型低抵抗層、９・・
・Ｎ＋型オーミック層、１０・・・金属配線、１１・・
ソース電極、１２・・・ドレイン電極。Figures 1(a) to (i) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and Figures 2(a) to (e) are cross-sectional views showing the second embodiment of the present invention in the order of steps. FIG. 3 is a cross-sectional view showing a G as M E S F E T according to the prior art. DESCRIPTION OF SYMBOLS 1... Semi-insulating GaAs substrate, 2... N-type channel layer, 3... Gael~electrode, 4... First insulating film, 4a
, 4b... side wall, 5... first photoresist, 6
...Second Photoregis? -, 7...Second insulating film, 7a...+11J wall, 8...N-type low resistance layer, 9...
・N+ type ohmic layer, 10...metal wiring, 11...
Source electrode, 12... drain electrode.
Claims (1)
ー障壁ゲート型電界効果トランジスタの製造方法におい
て、ドレイン側のゲート電極側面に第１の絶縁膜を形成
する工程と、前記ゲート電極と第１の絶縁膜とをマスク
として、Ｎ型不純物をイオン注入する工程と、ソース側
のゲート電極側面とドレイン側の第１の絶縁膜の側面と
に第２の絶縁膜を形成する工程と、前記ゲート電極、第
１の絶縁膜と第２の絶縁膜とをマスクとして、Ｎ型不純
物をイオン注入する工程と、イオン注入された不純物を
活性化するためのアニール工程と、ソース−ドレイン電
極を形成する工程を含むことを特徴とするショットキー
障壁ゲート型電界効果トランジスタの製造方法。In a method of manufacturing a Schottky barrier gate field effect transistor formed on a surface of a semi-insulating gallium arsenide substrate, a step of forming a first insulating film on a side surface of a gate electrode on a drain side, and forming a first insulating film between the gate electrode and the first insulating film are provided. a step of ion-implanting N-type impurities using the film as a mask; a step of forming a second insulating film on a side surface of the gate electrode on the source side and a side surface of the first insulating film on the drain side; A step of ion-implanting N-type impurities using the first insulating film and the second insulating film as masks, an annealing step to activate the ion-implanted impurities, and a step of forming source-drain electrodes. A method of manufacturing a Schottky barrier gate field effect transistor, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24418989A JPH03105929A (en) | 1989-09-19 | 1989-09-19 | Manufacture of schottky barrier junction gate type field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24418989A JPH03105929A (en) | 1989-09-19 | 1989-09-19 | Manufacture of schottky barrier junction gate type field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03105929A true JPH03105929A (en) | 1991-05-02 |
Family
ID=17115097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24418989A Pending JPH03105929A (en) | 1989-09-19 | 1989-09-19 | Manufacture of schottky barrier junction gate type field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03105929A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768147B2 (en) * | 2002-03-28 | 2004-07-27 | Fujitsu Quantum Devices Limited | Semiconductor device and method of fabricating the same |
-
1989
- 1989-09-19 JP JP24418989A patent/JPH03105929A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768147B2 (en) * | 2002-03-28 | 2004-07-27 | Fujitsu Quantum Devices Limited | Semiconductor device and method of fabricating the same |
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