JPH03105398A - Reverberation device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a digital signal processing part by allowing a write address in a memory for delaying a signal to coincide with a read address from the memory by a digital signal processing means. CONSTITUTION:The digital signal processing means (DSP) 2 loads a write/read address Add 5 at the time of accessing the memory. The address can be used for both writing and reading, and after initially reading out data from the external memory 3, the data are written by the same address. The address is successively subtracted in each access, and when the address reaches the minimum value, the address is automatically set up to the maximum value. Thereby, the memory 3 is used like a ring, the delay value up to writing/reading operation is the time required for restoring the Add 5 to the original value after one circulation and the delay value can be optionally changed by changing only the minimum value or maximum value. Thereby, the signal processing algorithm of the DSP 2 can be simplified and the generation of noise due to the change of the delay time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reverberation I$ device in a digital audio device.

BACKGROUND OF THE INVENTION In recent years, due to advances in semiconductor technology, digital signal processing technology for reverberation devices, which used to be a technology for professional equipment, has come to be announced in large numbers for consumer equipment.

A conventional example will be described below with reference to the drawings. Fig. 4 and enlarged Fig. 5 are diagrams of a conventional reverberation device.
6 is an output bus, 6 is an address bus that controls external memory, and 6 is a data bus/14'.

A reverberation device obtains the @reverberation effect by adding a delayed signal to the input digital signal, but it uses a digital signal processing LSI such as a DSP to add the delayed signal. An external memory is connected to an address bus in a digital signal processing LSI such as an LSI. connected by a data bus.

The reverberation device constructed as described above will be explained with reference to FIG. The numbers of structural elements in FIG. 6 are the same as those in FIG. 4. However, to explain the operation, each structural element is changed as follows.

2...nsp-digital signal processing section 3...
...External memory delay 7...Signal write address 8...Signal read address Digital signal input from 1 in Figure 5 (hereinafter referred to as signal) Digital signal processing of P2 After the necessary processing is performed in the section, the data is written to the delay section 3 of the external memory due to a delay. At this time, the signal is managed by write address 7. Further, the signal read out after a certain delay is managed by the read address 8. The signal delay time is determined by these write addresses and read addresses, and when using a DSP to add reverberation and manage the delay time, that is, to perform digital signal processing, the difference between these addresses must always be kept constant.

Two addresses, a write address and a read address, were given to the delay means, and the difference between the addresses corresponded to the delay time.

The delayed signal read out through the read address 8 is subjected to necessary processing in the digital signal processing section 2 and reaches the output 4.

Problems to be Solved by the Invention However, in the above-mentioned method, writing for memory management is required in the digital signal processing section. It was necessary to manage two addresses, read and write, which complicated the internal structure or algorithm.

FIG. 6 shows an example of address management in a conventional DSP. Now, the address space of the delay part in the memory space is Min-
Let's use Maxi. FIG. 6 shows only the memory access part of the signal processing flow of the DSP. According to FIG. 6, the write address is first loaded into the CC (accumulator) in order to perform a memory write to delay the write cycle. and A.C.C.
That is, the write address is subtracted by 1, and if the result is smaller than Min, the MILx value is loaded into ice, otherwise it is set to 11, and the memory for writing is accessed later using the path of the person CC as the address. At the same time, the access address is stored in the internal memory for the next access.

Next, a memory read cycle is entered. The rest is the same procedure as the write cycle, so the explanation will be omitted here.

As mentioned above, in the past, two addresses were managed, one for writing and one for reading, and the calculation required extra cycles, complicating the hardware or algorithm.

In view of the above problems, the present invention simplifies the internal configuration or algorithm of the digital signal processing section.
The present invention provides a reverberation device that integrates address management for delay.

Means for Solving the Problems In order to solve the above problem, the reverberation device of the present invention uses the same address for writing and reading from the memory of the digital signal processing section.

The invention of the action tree can simplify the structure (hardware or algorithm) of the digital signal processing section by the above structure.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram of an embodiment of the wooden invention. 1 is a signal input, 2 is a digital signal processor (DSP),
3 is an external memory, 4 is an output, 5 is an address bus to the memory, and 6 is a data bus connecting the DSP and the memory. The explanation of the external structure of the hardware is the same as that of the conventional example, and will therefore be omitted.

Next, the operation of the embodiment will be explained with reference to FIG. FIG. 2 is a diagram explaining the operation of the embodiment, where 1 is an input;
2 is a DSP, 3 is an external memory, 4 is an output, and 6' is a write/read address (data). Description of parts whose operation is the same as that of the conventional example will be omitted. In this embodiment, the memory address for delay is Min-MIL:Ic. The write/read address is set to ▲dd, and the relationship Min≦person dd≦Maw is maintained. Furthermore, when accessing memory, the DSP loads the memory address and subtracts -1 as shown in Figure 3, and uses the result to set Max or one of its residues as the access address. After reading at that address, writing is performed at the same address. Here, each time the person dd is accessed, the value is sequentially subtracted, and the value is Mini, and then the value of Max is obtained by further subtraction.

By doing this, the memory is used in a ring shape, and the amount of delay from writing to reading 1 is ▲1 after one round of dd.
Returns to original value! In the end, I decided to use Min-Maxi.
This corresponds to the entire delay allocation area in . To change the amount of delay, it is sufficient to simply change the Min or Max address, and since the access address is not directly changed, noise can be reduced. In this anoregorism of FIG. 3, the write/read addresses can be the same.

As described above, according to this embodiment, the digital signal processing section using the DSP and the memory for delaying signals are provided, and the DSP
By making the signal write address and read address to the memory for managing delay the same, it is possible to simplify the signal processing algorithm of the DSP and reduce noise when changing the delay time.

Effects of the Invention As described above, the present invention includes a digital signal processing means and a memory for delaying the signal, and in the digital signal processing means, by setting the signal write address and the read address to the memory to the same address, the digital signal can be processed. This facilitates the simplification of the processing section (hardware or algorithm).

is a block diagram explaining the operation in Fig. 1, and in Fig. 3, the first and fourth
FIG. 6 is a block diagram for explaining the operation of the figure, and FIG. 6 is a flowchart of the address calculation algorithm of the DSP of FIG. 4.

1...Input, 2...Digital signal processing means (or DSP), 3...Memory,
4...Reverberation output, 5...Address bus, 6...Data bus, 5'...Write/
Read address, 7...Write address, 8...Read address.

Claims (1)

[Claims] It is characterized by comprising a digital signal processing means for processing a digitized acoustic signal and a memory for delaying the signal, and in the digital signal processing means, the write address and the read address of the digital signal to the memory are the same address. reverberation device.