JPH0310519A - High gain d/a conversion output circuit - Google Patents

Abstract

PURPOSE:To supply high gain output with a low drift, a low offset and a high accuracy by applying n-times of shift of a high-order bit signal from the low- order to the high-order. CONSTITUTION:A ROM 19 has low-order addresses A0-A3 storing a parallel binary signal T as low-order bits and has high-order addresses A4, A5 storing the high-order bit with respect to the low-order bits. The logical arithmetic function of the ROM 19 is utilized and the bit string of the inputted parallel binary signal T is shifted by the high-order addresses A4, A5 by the combination of high and low level operations of switches 20, 21. Thus, the parallel binary signal from a zero adjustment circuit 6 is amplified digitally and amplified analogically by span offset circuits 10, 11 to obtain high gain outputs 16, 17 with a low drift, low offset and high accuracy.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to synchro electric machines, and in particular, digitizes the output of synchro electric machines used in instrumentation control equipment, and furthermore digitizes the output after zero adjustment with high precision and high precision. The present invention relates to a D/A high gain output circuit using digital signal processing to obtain gain.

[Conventional technology]

Conventionally, synchronous operation of cranes and dam gate hoisting machines,
Synchronous electric machines are used for the synchronized operation of belt conveyors and various sensors, and internationally standardized instrumentation signals are used. Synchro electric machines have the same structure as wire-wound induction motors, and have excellent resistance to wind (temperature, humidity), vibration, and shock.

FIG. 3 is a block diagram showing an output signal processing circuit when the output of such a synchro electric machine is used as a control signal for an instrumentation control device.

In the figure, an output signal 102 from a synchro electric machine 101
is input manually to an S/D (synchronized digital) converter 104 (synverter: trade name 1, manufactured by Nihon Denki Seiki Co., Ltd.) of the signal converter 103, where the output signal is converted into a digital signal 105.

This digital signal 105 is manually inputted to a zero adjustment circuit 106, adjusted to a zero value from a desired value, and becomes a zero adjustment signal 107, which is converted into an analog signal 109 by a D/A (digital-to-analog) converter 108.

This analog signal 109 is branched to a first span offset circuit 110 . Second span offset circuit 111
The span and zero point position are adjusted, and the span and offset adjustment signals 112 and 113 are respectively inputted to the V/I (voltage/current) converter 114 and the buffer yl15. An output current 116 of 4 to 20 mA and an output voltage 117 of 0 to 10 V are sent out from these V/I converter 114 and buffer 115, respectively. Here, the analog signal 109 of the D/A converter 108 has a relationship between the synchronization angle and the output voltage of 0 to 10V10° to 360°.
It is fixed as follows.

[Problem to be solved by the invention]

By the way, the above output current 116 and output voltage 117 may vary depending on the instrumentation control device as a load, depending on the synchro electric machine angle (
For example, as shown in Figure 4, 0° to 320° is 0 to IOV or 4 mA to 20
mA, or 18° to 3
60° may have to correspond to OV to IOV or 4mA to 20mA. For this reason, conventionally, span and zero point positions have been adjusted in an analog manner using span offset circuits 110 and 111 to satisfy the above requirements. However, with this conventional method, D
Since the gain of the analog signal 109 from the /A converter 108 is adjusted using an operational amplifier, for example, O~18° is 0■
When trying to configure a high gain circuit such as ~IOV or 4mA ~ 20mA, there is a drawback that drift and offset become large.

The present invention has been made to solve these conventional drawbacks, and it is possible to reduce drift by processing the digital signal on the input side of the D/A converter.

It is an object of the present invention to provide a D/A high gain output circuit using digital signal processing that can provide a high gain output with low offset and high accuracy.

[Means to solve the problem]

The D/A high gain output circuit based on digital signal processing of the present invention is configured as a combination of a lower address in which manually generated parallel binary signals are stored as lower bits, and a high level or low level signal by switching an accompanying switch circuit. and an upper address for storing the higher-order bit signal, and the configuration of the upper-order bit signal is changed by switching the switch circuit, and the lower-order bit signal is changed according to the weight set in advance by the changed upper-bit signal. This is a high-gain D/A conversion circuit whose main component is a ROM, which is equipped with logical operation means for shifting the bit array of an input parallel binary signal, which is a signal.

[Effect]

The bit arrangement of the upper bit signal is shifted by switching the switch circuit. Along with this switching of the upper bit signal, the bit arrangement of the manually input parallel binary signal, which is the lower bit signal, is also shifted.

As a result, the upper bit signal is shifted from lower to upper n
By performing this process twice, the input parallel binary signal, which is the lower bit, is amplified by 2fi times and output.

〔Example〕

Hereinafter, one embodiment of a high gain D/A conversion output circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a synchro electric machine output signal processing circuit incorporating an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the embodiment of FIG. 1 in detail.

In FIG. 1, the output signal from the synchro electric machine 1 is sent to the S/D converter 4 of the signal converter 3. It passes through the power conditioning circuit 6 and becomes a power conditioning signal 7, which is manually input to the D/A high gain output circuit 18 of this embodiment. Here, the electric tone signal 7 is digitally amplified and converted into an analog signal 9 by a D/A converter 8. This analog signal 9 is branched to the span/offset circuits 10 and 11 as explained in the conventional example in FIG. 3, and subjected to span and offset processing in each.
An output current 16 of 4 to 20 mA and an output voltage 17 of 0 to 10 mA are delivered through a V/I converter 14 or a buffer 15, respectively.

Here, the D/A high gain output circuit 18 of this embodiment will be explained with reference to FIG.

In the figure, a read-only memory (hereinafter referred to as R) is used as a storage means.
It is abbreviated as OM. ) 19 denotes lower addresses A0 to A in which the parallel binary signal T (assumed to be 4 bits here), which is the electric power signal 7 from the electric power controller 6 in FIG. 1, is stored as lower bits, and these lower addresses. It has upper addresses A1, A, which store the upper bits of the bits.

Switches 20 and 21 are connected to upper addresses A1 and A of this ROM 19. These switches 20.21
are both switched connected to either the power supply Vee or OV. For example, when the switches 20, 21 are connected to the power supply Vce side, the potentials of the corresponding addresses A, , AS become high level, and when the switches 20, 21 are connected to the OV side, the potentials of the addresses A4, . Both As levels are low.

Next, by using the logic operation function of the ROM, the upper addresses As, As are determined by the combination of high-level and low-level operations of the switches 20 and 21. Shift as shown. However, in Table 1, H represents high level and L represents low level.

Also, similar symbols will be used in the following description as necessary.

Table 1 For example, if you input 0011(3) manually as a 4-digit bit string T and set switch 20 to H and 21 to L, RO
The output of M becomes 0110(6).

Next, when switch 20 is set to L and switch 21 is set to H, the ROM
(7) Output 1tl l OO(12) I:? , + le.

Immediately, manual data to ROM is transferred to switches 20 and 2.
1 state (high level or low level), it is possible to obtain output data by shifting the input data by pre-memorizing the relationship between the weight of the output and the input in the ROM, and as a result, the D/A high gain circuit 18 gains can be changed.

The parallel binary signal from the power conditioning circuit 6 is amplified digitally by the D/A high gain output circuit 18 of the present embodiment shown above, and then amplified in an analog manner by the span offset circuit 10.11. As a result, it is possible to obtain an output of 16.17 with low drift, low offset, high precision, and high gain. For example, as shown in Figure 4, if you want to obtain an output of IOV or 20 mA at a synchro angle of 18 degrees, you can amplify it 16 times on the digital side and multiply it by 20/16 = 1.25 on the analog side. .

[Effects of the Invention] As explained above, a memory means provided with addresses for respectively storing manually input parallel binary signals and higher-order bit signals that are a combination of high-level or low-level signals by switching a switch circuit; The input parallel binary signal can be changed by a simple circuit comprising a ROM and a switch. 2″
It has the effect of providing high precision, high gain, low drift, and low offset output that can be amplified twice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a synchro electric machine output signal processing circuit incorporating an embodiment of the D/A high gain output circuit according to the present invention, and FIG. 2 is an explanatory diagram showing the embodiment of FIG. 1 in detail.
FIG. 3 is a block diagram showing the output signal processing circuit of a conventional synchro electric machine, and FIG. 4 is a graph showing the relationship between the synchro angle and the synchro electric machine output. 1... Synchro electric machine, 3... Signal converter, 4... S/D converter, 6... Electrical control circuit, 8... A/D converter, 10... First span・Offset circuit, 11...Second span offset circuit, 14...V/I converter, 15...Buffer, 18...D/A high gain output circuit, 19...Memory for continuous use (ROM)20.21...
·switch.

Claims (1)

[Claims] 1. Storage of a lower address for storing an input parallel binary signal as a lower bit signal and a higher bit signal configured as a combination of a high level or low level signal by switching an accompanying switch circuit. an input parallel binary signal, which is a lower bit signal, by changing the configuration of the upper bit signal by switching the switch circuit; A high gain D/A conversion circuit comprising: logical operation means for shifting the bit array of;