JPH0310513A - Overflow detection method at transfer to register - Google Patents

Abstract

PURPOSE:To make the processing between registers efficient by providing a circuit detecting an overflow caused by the transfer in order to monitor whether or not the transfer between registers with a different word length is correctly implemented. CONSTITUTION:A detection circuit 3 in an overflow detection circuit 7 connected to a register 6 from a data bus 1 via a buffer 2 detects whether or not there is an overflow bit in data of a code bit S from a data bus 1, sends an alarm signal when an overflow bit exists and sends a detection signal to a decision circuit 4 and the signal is converted and inputted into a selection circuit 5. The selection circuit 5 uses a control signal from the decision circuit 4 to select whether the data from the buffer 2 is passed through as it is, a lower limit data is passed through or an upper limit data is passed through and the resulting signal is sent to the register 6.

Description

[Detailed Description of the Invention] [Summary] Regarding an overflow detection method when transferring data to a register in a digital signal processing LSI, an overflow is detected when a data value is transferred to a register whose word length is shorter than the width of the internal data bus. In a circuit connected from a data bus to a register via a buffer for the purpose of detecting and stabilizing processing, there is a detection circuit that detects overflow bits of input data, and an overflow detection bit B from the detection circuit. and the sign bit S of the input data (control pin) So, 5
1, and a selector that selects input data via the buffer, an upper limit value, and a lower limit value under the control of the control bits So, St and overflow bit B. The configuration is such that when an overflow is not detected, the data is sent to the register, and when an overflow is detected, the upper limit value or lower limit value of the data is sent to the register.

[Industrial Application Field] The present invention relates to an overflow detection method during data transfer to a register in a digital signal processing LSI.

Digital signal processing (DSP) LSI is a communication device, NC
It has come to be used in various fields such as devices and image processing. Furthermore, with the expansion of the scope of application, ASIC-DSP
DSPs optimized for each application have been developed. Such an optimized DSP internally includes registers of various types of word lengths. In such a case,
It is possible that a larger number of data than each register can represent may be transferred to the registers, in which case subsequent calculations by the registers will not be performed correctly.

Normally, when performing numerical calculations, countermeasures against overflows and the like that occur during calculations are taken using software. However, since the transfer of the result of the calculation is not taken into consideration, or all registers have the same bit precision, there is no need to take measures against overflows.

However, as DSPs become ASICs, custom-made ICs for specific applications such as filters and echo cancellers are required, and the bit length of registers becomes the minimum necessary size, which increases the possibility of overflow occurring during transfer. It's coming out.

[Prior Art] FIG. 5 shows a block configuration diagram of the -M SP-LSI. In the figure, 20 is a DSP/LSI, 21 is an arithmetic block, 22 is an address arithmetic block, 23 is a program sequence control block, and 24 is a special register/LSI.
A counter block 25 indicates an input/output interface block, and each block is interconnected by a data bus 26.

Arithmetic block 21, input/output interface block 2
5 and the like each have a register and are connected to the data bus 26 via a buffer. The data bus 26 is 3
It is composed of 2-bit buses x 2 trees, and each register receives data from these data buses.

[Problem to be solved by the invention]

However, since all of these conventional registers have the same bit precision, no measures have been taken to prevent overflows that occur during calculations. Therefore, as a countermeasure against overflows and the like that occur during calculation, software is used to examine the range of data and check whether the data is within the range before being transferred.

The present invention aims to improve the efficiency of processing between registers by providing a circuit for detecting overflow caused by transfer in order to monitor whether transfer between registers having different word lengths is being performed correctly. .

[Means for Solving the Problems] FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 1 is a data bus, 2 is a buffer, 3 is a detection circuit, 4 is a determination circuit, 5 is a selection circuit, 6 is a register, and 7 is an overflow detection circuit.

In the overflow detection circuit 7 connected from the data bus 1 to the register 6 via the buffer 2, the detection circuit 3
detects whether there is an overflow bit in the code bit S data from the data bus 1, and if an overflow bit is present, it sends out an alarm signal and also sends the detection signal to the judgment circuit 4 to convert it into a control signal. and input it to the selection circuit 5. The selection circuit 5 selects whether to pass the data from the buffer 2 as is, pass the data of the lower limit value, or pass the data of the upper limit value according to the control signal from the determination circuit 4, and sends the selected data to the register 6.

[Operation] Figure 2 shows the word length formants of the data bus and registers. In the figure, the width of a 10-word data bus is 13 bits including the sign bit S, the bit width of register 6 is 10 bits including the sign bit S, and the bit width of data bus l is 3 bits larger than the bit width of the register. shall be.

The bits in the shaded part of data bus l indicate overflow bits, and all the bits in other parts are in register 6.
Therefore, if the number of bits in the shaded area that exceeds the number of bits that can be processed is inserted, the detection circuit 3 detects this as an overflow bit and sends a signal to the sequence control circuit to control branch conditions and interrupts. At the same time as being used as a trigger, a control signal is sent from the determination circuit 4 to the selection circuit 5 based on the combination of the detection signal from the detection circuit 3 and the sign bit S, and if there is no overflow in the selection circuit 5, the data is passed through the buffer 2. is sent to the register 6 as is, and if an overflow is detected, the overflow portion is cut off and either the lower limit value data or the upper limit value data is sent to the register 6. Therefore, even if data whose number of bits exceeds the processing capacity of the register is input, the overflow part can be cut off and processed.

〔Example] A circuit configuration diagram of an embodiment of the present invention is shown in FIG.

In the figure, 1 is a data bus, 3 is a detection circuit, 4 is a determination circuit, 5 is a selection circuit, and 6 is a register.

Detection circuit 3 is a detection circuit for three overflow bits of data bus l, including sign bit S and overflow bits Bl, B2 . EXOR circuit 11 with each of B3,
12.13, and a three-man OR circuit 14 for the output of each EXoR circuit, and inputs the sign bit S and the three-man OR output B to the determination circuit 4.

Sign bit S and overflow bit 81. B2. B3
are the same, that is, "Ll, LL" or "o, o, o, o", the detection signal B becomes "0" and it is determined that there is no effect of overflow, but the sign bit S and other overflow bits Bl, 82.8
If even one value differs from 3, that is, "1,0.0.1" or "0,1°0.0", the detection signal B will be "
1”, and an overflow is detected.

The judgment circuit 4 includes AND circuits 15 and 16 and an inverter 17.
It inputs the detection bit B and the sign bit S from the detection circuit 3 and outputs control signals S0 and S1. That is, if detection bit B is “O”, sign bit S is “0”.
However, even if the control pins (SO and St) are “1”, it will always be “0” and it is judged that there is no overflow, but the detection pin (B) is “
1”, it is determined that there is an overflow, and in combination with the sign bit S, the control bits So and SL are set to “0”.
” or “1”. Therefore, if there is no overflow, no control signal is sent out, but if there is an overflow, a control signal is sent out.

The selection circuit 5 includes a selector 18, and when it is determined that there is no overflow based on the control signals S0 and S1 from the determination circuit 4, it sends the data bus signal via the buffer to the register 6. If it is determined that there is an overflow, the lower limit value or upper limit value of the bit/nod data is sent out based on the combination signal of the control bin (So, SL) and the detection bit B. If the sign pi+-S is “1”, the lower limit value is “10”.
．． 00...-00", and when the code bin S is "0", the upper limit value is "01.11---11".

Input sign bit S, detection bit B, control bit So,
The relationship between SL and the output data from the selector, ie, the input data to the register, is as follows.

FIG. 4 shows an example of an output waveform of an analog data or echo canceller using the overflow detection circuit of the present invention. In the figure, the amplitude of input data is shown in bit length,
Showing the relationship between the time axis and the output waveform, the overflow bit portion shown by the dotted line is cut off, and the solid line output waveform surrounded by the upper limit value and the lower limit value is sent out as data.

[Effects of the Invention] As described above, by using the circuit of the present invention, an overflow caused by transfer can be detected before it is manually input to the register, and efficient data processing can be performed.

tab block, 25 is an input/output interface block,
26 indicates a data bus.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is the word length format of the data bus and registers, Fig. 3 is a circuit diagram of the embodiment, Fig. 4 is the analog data output waveform of the embodiment, and Fig. 5 1 shows a block diagram of a conventional DSP-LSI. In the figure, ■ is a data bus, 2 is a buffer, 3 is a detection circuit, 4 is a judgment circuit, 5 is a selection circuit, 6 is a register, and 7
is overflow detection circuit, 11°12, I3 is EX
14 is an OR circuit, 1516 is an AND circuit, 17 is an inverter, and 18 is a selector. Also 2
0 is a DSP/LSI, 21 is an arithmetic programmer data bus. Fig. 1 is a circuit diagram of the embodiment of the present invention. Fig. 3 is a word length format of the data bus and registers. Fig. 2 is the data bus.

Claims (1)

[Claims] A circuit connected from a data bus (1) to a register (6) via a buffer (2) includes a detection circuit (3) for detecting an overflow bit of input data; ) and a buffer (2) that sends out control bits S0 and S1 based on the overflow detection bit B from the input data and the sign bit S of the input data. It is equipped with a selector (5) for selecting the input data via the data bus, upper limit value, and lower limit value, and when an overflow of the input data from the data bus (1) is not detected, the data is sent to the register (6), A method for detecting an overflow during transfer to a register, characterized in that when an overflow is detected, an upper limit value or a lower limit value of the data is sent to a register (6).