JPH0310487A - Decoder - Google Patents

Decoder

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Publication number
JPH0310487A
JPH0310487A JP1144531A JP14453189A JPH0310487A JP H0310487 A JPH0310487 A JP H0310487A JP 1144531 A JP1144531 A JP 1144531A JP 14453189 A JP14453189 A JP 14453189A JP H0310487 A JPH0310487 A JP H0310487A
Authority
JP
Japan
Prior art keywords
value
error
sample
correction
decoded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1144531A
Other languages
Japanese (ja)
Other versions
JP2995750B2 (en
Inventor
Nobuhiro Hoshi
星 伸宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP14453189A priority Critical patent/JP2995750B2/en
Priority to EP90305991A priority patent/EP0402058B1/en
Priority to DE69026143T priority patent/DE69026143T2/en
Publication of JPH0310487A publication Critical patent/JPH0310487A/en
Priority to US08/148,523 priority patent/US5325374A/en
Application granted granted Critical
Publication of JP2995750B2 publication Critical patent/JP2995750B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To reduce the correction error by replacing a data with a just preceding value with highest correlation at correction disable state and applying succeeding decoding with the replaced decoding value. CONSTITUTION:The decoder consists of an input terminal 42 for transmission data, an error detection correction circuit 44, an inverse quantizer 46, an adder 48, a switch 50 switched by a correction disable error code, a D flip-flop 52 acting like a delay device for one sample interval, and an output terminal 54 for the decoded value. Then the decoded value corresponding to the coded code disabled of error correction is replaced with the decoding value at one preceding sample with the highest correlation and the succeeding sample is decoded according to the replaced decoding value. Then the correction error is reduced.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、予測符号化方式における復号化装置に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding device in a predictive coding method.

[従来の技術] 画像情報をディジタル伝送する場合に、1標本当たりの
伝送ビット数を削減する方法として、隣接する標本値が
互いに大きな相関性を具備するという性質を利用して圧
縮する差分符号化法(以下、DPCMと略す。)が知ら
れている。
[Prior Art] When digitally transmitting image information, a method for reducing the number of transmission bits per sample is differential encoding, which compresses adjacent sample values by taking advantage of the property that they have a high correlation with each other. (hereinafter abbreviated as DPCM) is known.

第4図は、最も一般的な前値予測DPCM符号化装置の
構成ブロック図を示す。10は標本値の入力端子、12
は入力の標本値から予測値を減算する減算器、14は量
子化器、16は逆量子化器、18は加算器、20は予測
値を出力するためのDフリップフロップ、22は誤り訂
正符号化回路、24は符号化コードの出力端子である。
FIG. 4 shows a configuration block diagram of the most general prior value predictive DPCM encoding device. 10 is the sample value input terminal, 12
is a subtracter that subtracts the predicted value from the input sample value, 14 is a quantizer, 16 is an inverse quantizer, 18 is an adder, 20 is a D flip-flop for outputting the predicted value, and 22 is an error correction code. 24 is an output terminal of the encoded code.

減算器12は、入力端子10の標本値(8ビツト)から
、Dフリップフロップ20の出力の前値予測値(8ビツ
ト)を減算し、量子化器14は、減算器12の出力の差
分値を量子化し、DPCM符号(4ビツト)を出力する
。誤り訂正符号化回路22は量子化器14の出力に誤り
訂正用パリティを付加して、出力端子24に出力する。
The subtracter 12 subtracts the previous predicted value (8 bits) of the output of the D flip-flop 20 from the sample value (8 bits) of the input terminal 10, and the quantizer 14 subtracts the difference value of the output of the subtracter 12. is quantized and a DPCM code (4 bits) is output. The error correction encoding circuit 22 adds error correction parity to the output of the quantizer 14 and outputs it to the output terminal 24.

また、逆量子化器16は量子化器14の出力のDPCM
符号(4ビツト)を逆量子化し、差分代表値(8ビツト
)を出力する。加算器18は逆量子化器16の出力に前
値予測値を加算し、Dフリップフロップ20はこれを1
標本間隔分遅延し、前値予測値として減算器12及び加
算器18に印加する。
Further, the inverse quantizer 16 converts the output of the quantizer 14 into DPCM.
The code (4 bits) is dequantized and the representative difference value (8 bits) is output. The adder 18 adds the previous predicted value to the output of the inverse quantizer 16, and the D flip-flop 20 adds this to 1
It is delayed by the sampling interval and applied to the subtracter 12 and adder 18 as the previous predicted value.

一般に前値予測値との差分値は非常に小さな値となるの
で、差分値を符号化して伝送することにより、大きな圧
縮が可能になる。
Generally, the difference value from the previous predicted value is a very small value, so by encoding and transmitting the difference value, large compression becomes possible.

第5図は第4図に対応する復号化装置の構成ブロック図
を示す。26は伝送されたDPCM符号の入力端子、2
8は誤り検出訂正回路、30は逆量子化器、32は加算
器、34はDフリップフロップ、36はスイッチ、38
は1ライン遅延器、40は復号値の出力端子である。
FIG. 5 shows a block diagram of the configuration of a decoding device corresponding to FIG. 4. 26 is an input terminal for the transmitted DPCM code; 2
8 is an error detection and correction circuit, 30 is an inverse quantizer, 32 is an adder, 34 is a D flip-flop, 36 is a switch, 38
is a one-line delay device, and 40 is an output terminal for the decoded value.

入力端子26の入力データは誤り検出訂正回路28によ
り、データ伝送中に発生した誤りを検出・訂正される。
The input data at the input terminal 26 is subjected to error detection and correction circuit 28, which detects and corrects errors that occur during data transmission.

誤り検出訂正回路28は、DPCM符号を逆量子化器3
0に印加すると共に、訂正できなかった場合には、スイ
ッチ36を制御するエラー・フラグ(第6図参照)を出
力する。逆量子化器30はDPCM符号を逆量子化して
、差分代表値を出力し、加算器32は逆量子化器30の
出力に前値復号値を加算する。加算器32の出力が復号
値となる。加算器32の出力はDフリップフロップ34
で1標本間隔だけ遅延され、前値復号値として加算器3
2に帰還される。
The error detection and correction circuit 28 converts the DPCM code into the inverse quantizer 3.
0, and if the error cannot be corrected, an error flag (see FIG. 6) that controls the switch 36 is output. The dequantizer 30 dequantizes the DPCM code and outputs a representative difference value, and the adder 32 adds the previous decoded value to the output of the dequantizer 30. The output of adder 32 becomes the decoded value. The output of the adder 32 is a D flip-flop 34.
is delayed by one sample interval and sent to adder 3 as the previous value decoded value.
2 will be returned.

加算器32の出力は直接、スイッチ36の接点aに印加
され、1ライン遅延器38を介してスイッチ36の接点
すに印加される。一般に、DPCM符号化方式では、伝
送路で誤りが発生すると、次に標本値そのものを量子化
したPCM符号の復号値か得られるまで、誤りが後続の
復号値に伝搬することが知られている。そこで、誤り検
出訂正回路28で符号化コードに訂正不能な誤りが検出
された場合には、第6図に示すように、当該訂正不能の
誤り検出以後、エラー・フラグを立てる。
The output of the adder 32 is directly applied to the contact a of the switch 36, and is applied to the contact a of the switch 36 via the one-line delay device 38. Generally, in the DPCM encoding method, when an error occurs in the transmission path, it is known that the error propagates to subsequent decoded values until the next decoded value of the PCM code, which is quantized from the sample value itself, is obtained. . Therefore, when the error detection and correction circuit 28 detects an uncorrectable error in the encoded code, as shown in FIG. 6, an error flag is set after the uncorrectable error is detected.

当該エラー・フラグか立っている間はスイッチ36を接
点す側に切り換えて、前ラインの標本値で代替、即ち修
整する。第6図はこの修整による復号値の、1サンプル
点おきの変化を示す。
While the error flag is set, the switch 36 is switched to the contact side, and the sample value of the previous line is substituted, that is, corrected. FIG. 6 shows changes in decoded values at every other sample point due to this modification.

[発明か解決しようとする課題] しかし上記従来例では、1ライン前の標本値で代替する
ので、1ライン遅延器が必要になり、ハードウェアの増
加を招くという欠点がある。また、訂正不能な符号化コ
ードが検出された後の全ての復号値を代替するので、現
在のラインの標本値とその1ライン前の標本値との間に
相関が無い場合には、大きな画質劣化になるという欠点
がある。
[Problems to be Solved by the Invention] However, in the conventional example described above, since the sample value of one line before is substituted, a one-line delay device is required, resulting in an increase in hardware. In addition, all decoded values after an uncorrectable encoded code is detected are replaced, so if there is no correlation between the sample value of the current line and the sample value of the previous line, the image quality will be improved. It has the disadvantage of deterioration.

このような場合、第6図に示すように、前ラインの標本
値と、伝送路誤りが無い場合の標本値との差が大きくな
っており、画質劣化が顕著になる。
In such a case, as shown in FIG. 6, the difference between the sample value of the previous line and the sample value when there is no transmission path error becomes large, and the image quality deteriorates significantly.

本発明はこのような欠点のない復号化装置を提示するこ
とを目的とする。
The present invention aims to present a decoding device that is free from such drawbacks.

[課題を解決するための手段] 本発明に係る復号化装置は、予測符号化方式における復
号化装置であって、誤り訂正不能な符号化コードに対応
する復号値を1サンプル前の復号値で代替する代替手段
を設け、当該代替手段の出力する復号値に従い次サンプ
ルの復号を行なうことを特徴とする。
[Means for Solving the Problems] A decoding device according to the present invention is a decoding device using a predictive coding method, and is a decoding device that uses a decoded value of one sample before a decoded value corresponding to an encoded code that cannot be error corrected. The present invention is characterized in that an alternative means is provided and the next sample is decoded in accordance with the decoded value output by the alternative means.

[作用] 上記手段により、誤った符号化コードに対応する復号値
に対して、最も相関性の高い直前の復号値で代替するの
で、修整誤差は極めて小さく、且つ、この代替復号値で
次サンプルの復号を行なうので、この修整誤差は時間の
経過によって大きくならない。また、1ライン遅延器を
用いないで済み、回路構成が簡略化し、安価になる。
[Operation] With the above means, the decoded value corresponding to the erroneous encoded code is replaced with the immediately preceding decoded value with the highest correlation, so the modification error is extremely small, and this alternative decoded value is used for the next sample. Since decoding is performed, this correction error does not increase over time. Further, it is not necessary to use a one-line delay device, and the circuit configuration is simplified and the cost becomes low.

[実施例] 以下、図面を参照して本発明の詳細な説明する。[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の構成ブロック図を示す。4
2は伝送データの入力端子、44は誤り検出訂正回路、
46は逆量子化器、48は加算器、50は訂正不能のエ
ラー・コートにより切り換えられるスイッチ、52は1
標本間隔の遅延器として機能するDフリップフロップ、
54は復号値の出力端子である。
FIG. 1 shows a block diagram of an embodiment of the present invention. 4
2 is an input terminal for transmission data; 44 is an error detection and correction circuit;
46 is an inverse quantizer, 48 is an adder, 50 is a switch switched by an uncorrectable error code, and 52 is 1
a D flip-flop that acts as a sample interval delayer;
54 is a decoded value output terminal.

誤り検出訂正回路44は入力端子42の伝送データを受
け、伝送途中の誤りを検出・訂正し、DPCM符号を逆
量子化器30に供給する。誤り検出訂正回路44はまた
、訂正不能の伝送誤りに対しては、第2図に示すように
、スイッチ50を制御するエラー・フラグを1サンプル
期間立てる。
The error detection and correction circuit 44 receives the transmission data at the input terminal 42, detects and corrects errors during transmission, and supplies the DPCM code to the dequantizer 30. Error detection and correction circuit 44 also sets an error flag that controls switch 50 for one sample period, as shown in FIG. 2, for uncorrectable transmission errors.

加算器48は逆量子化器46の出力(差分代表値)にD
フリップフロップ52の出力(前値復号値)を加算する
。加算器48の出力はスイッチ50の接点aに接続し、
スイッチ50の接点すにはDフリップフロップ52の出
力が接続する。スイッチ50で選択された信号は、復号
値として出力端子54に供給されると共に、Dフリップ
フロップ52に印加される。即ち、スイッチ50は、通
常は接点aに接続して加算器48の出力を選択するか、
訂正不能な誤りに対しては誤り検出訂正回路44からの
エラー・フラグに従い1サンプル期間だけ接点すに接続
し、前値復号値を選択する。
The adder 48 adds D to the output (difference representative value) of the inverse quantizer 46.
The output of the flip-flop 52 (previous value decoded value) is added. The output of the adder 48 is connected to contact a of the switch 50,
The output of the D flip-flop 52 is connected to the contact point of the switch 50. The signal selected by switch 50 is supplied as a decoded value to output terminal 54 and is also applied to D flip-flop 52. That is, the switch 50 is normally connected to contact a to select the output of the adder 48, or
For uncorrectable errors, the contact is connected for one sample period according to the error flag from the error detection and correction circuit 44, and the previous decoded value is selected.

第2図は第1図の動作例を示す。第5サンプル時点で訂
正不能な伝送誤りが発生しており、その時点の誤って復
号された標本値を1サンプル前の復号値で置換している
。1サンプル前の標本値は現在の標本値と極めて相関が
高いので、復号値での修整誤差も極めて小さい。以後、
伝送されてきたDPCM符号で復号するので、修整誤差
は一定値内に収まり、大きくならない。特に、1サンプ
ル前の標本値と同じ標本鍍のサンプルで訂正不能の伝送
誤りが発生した場合には、修整誤差はゼロである。
FIG. 2 shows an example of the operation of FIG. An uncorrectable transmission error occurs at the time of the fifth sample, and the erroneously decoded sample value at that time is replaced with the decoded value one sample before. Since the sample value one sample before has an extremely high correlation with the current sample value, the correction error in the decoded value is also extremely small. From then on,
Since decoding is performed using the transmitted DPCM code, the modification error remains within a certain value and does not become large. In particular, if an uncorrectable transmission error occurs in a sample of the same sample size as the sample value one sample before, the modification error is zero.

第1図の、逆量子化器46、加算器48及びスイッチ5
0の部分は、ROMテーブルにより形成できる。第3図
はその構成ブロック図を示す。56がその復号化テーブ
ルとしてのROMである。
Inverse quantizer 46, adder 48 and switch 5 in FIG.
The 0 part can be formed by a ROM table. FIG. 3 shows its configuration block diagram. 56 is a ROM serving as the decoding table.

ROM56は、入力として、DPCM符号に4ビツト、
予測値に8ビツト、誤り検出訂正回路44の出力するエ
ラ・フラグに1ビツトを割り当ててあり、また、8ビツ
ト出力を持つ。ROM56には、エラー・フラグが立っ
ているときには、前値復号値、即ちDフリップフロップ
の出力と同一の符号を出力するように書いておき、エラ
ー・フラグが立っていないときには、4ビツトのDPC
M符号による差分代表値にDフリップフロップからの前
値復号値を加算した値を出力するように書いておけばよ
い。
The ROM 56 receives as input 4 bits of DPCM code,
8 bits are allocated to the predicted value, 1 bit is allocated to the error flag output from the error detection and correction circuit 44, and it has an 8-bit output. The ROM 56 is written so that when the error flag is set, the previous decoded value, that is, the same code as the output of the D flip-flop, is output, and when the error flag is not set, the 4-bit DPC is output.
It may be written to output a value obtained by adding the previous decoded value from the D flip-flop to the representative difference value based on the M code.

上記実施例では前値予測符号化法を例に説明したが、フ
レーム間予り1符号化法やライン間予測符号化法でも同
様に適用できることはいうまでもない。
Although the above embodiments have been described using the previous predictive coding method as an example, it goes without saying that the interframe pre-1 coding method and the interline predictive coding method can be similarly applied.

[発明の効果] 以上の説明から容易に理解できるように、本発明によれ
ば、1ライン遅延器を用いないので、回路構成が簡略化
し、安価になる。また、訂正不能時には、最も相関性の
高い直前値で代替するので、修整誤差は極めて小さく、
且つ、この代替復号値により以後の復号を行なうので、
この修整誤差は時間の経過によって大きくならない。
[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, since no one-line delay device is used, the circuit configuration is simplified and the cost is reduced. In addition, when correction is not possible, the immediately preceding value with the highest correlation is used as a substitute, so the correction error is extremely small.
Moreover, since subsequent decoding is performed using this alternative decoding value,
This modification error does not increase over time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成ブロック図、第2図は
第1図の動作説明図、第3図は第1図の一部をROM化
した構成例、第4図は従来の符号化装置の構成ブロック
図、第5図は従来の復号化装置の構成ブロック図、第6
図は第5図の動作説明図である。 42;入力端子 44:誤り検出訂正回路 46:逆量
子化器 48:加算器 50:スイッチ52:Dフリッ
プフロップ 54:出力端子第1図 23456    フ   8.IjJ(、、′ル2.
。 第2図 第 5 図 第 図 時間(サノブル)
FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1, FIG. 3 is a configuration example in which a part of FIG. Fig. 5 is a block diagram of the configuration of the encoding device, and Fig. 6 is a block diagram of the configuration of the conventional decoding device.
The figure is an explanatory diagram of the operation of FIG. 5. 42; Input terminal 44: Error detection and correction circuit 46: Inverse quantizer 48: Adder 50: Switch 52: D flip-flop 54: Output terminal 23456 F 8. IjJ(,,'le2.
. Figure 2 Figure 5 Figure Time (Sanoble)

Claims (1)

【特許請求の範囲】[Claims] 予測符号化方式における復号化装置であって、誤り訂正
不能な符号化コードに対応する復号値を1サンプル前の
復号値で代替する代替手段を設け、当該代替手段の出力
する復号値に従い次サンプルの復号を行なうことを特徴
とする復号化装置。
A decoding device in a predictive coding system, which has an alternative means for substituting a decoded value corresponding to an uncorrectable encoded code with a decoded value one sample before, and selects the next sample according to the decoded value output by the alternative means. A decoding device characterized by decoding.
JP14453189A 1989-06-07 1989-06-07 Decryption device Expired - Fee Related JP2995750B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP14453189A JP2995750B2 (en) 1989-06-07 1989-06-07 Decryption device
EP90305991A EP0402058B1 (en) 1989-06-07 1990-06-01 Predictive decoding device correcting code errors
DE69026143T DE69026143T2 (en) 1989-06-07 1990-06-01 Prediction decoding device correcting code error
US08/148,523 US5325374A (en) 1989-06-07 1993-11-04 Predictive decoding device for correcting code errors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14453189A JP2995750B2 (en) 1989-06-07 1989-06-07 Decryption device

Publications (2)

Publication Number Publication Date
JPH0310487A true JPH0310487A (en) 1991-01-18
JP2995750B2 JP2995750B2 (en) 1999-12-27

Family

ID=15364486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14453189A Expired - Fee Related JP2995750B2 (en) 1989-06-07 1989-06-07 Decryption device

Country Status (1)

Country Link
JP (1) JP2995750B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799582A (en) * 1993-06-18 1995-04-11 Kawasaki Steel Corp Picture compressor
US5915043A (en) * 1994-07-15 1999-06-22 Nec Corporation Image reproducing apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62241436A (en) * 1986-04-14 1987-10-22 Canon Inc Predictive coding and decoding system for image signal
JPH0198323A (en) * 1987-10-12 1989-04-17 Nec Corp Error correction device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62241436A (en) * 1986-04-14 1987-10-22 Canon Inc Predictive coding and decoding system for image signal
JPH0198323A (en) * 1987-10-12 1989-04-17 Nec Corp Error correction device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799582A (en) * 1993-06-18 1995-04-11 Kawasaki Steel Corp Picture compressor
US5915043A (en) * 1994-07-15 1999-06-22 Nec Corporation Image reproducing apparatus

Also Published As

Publication number Publication date
JP2995750B2 (en) 1999-12-27

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