JP2995750B2 - Decryption device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device that decodes an encoded code subjected to predictive difference encoding.

[Prior Art] When digitally transmitting image information, as a method of reducing the number of transmission bits per sample, differential encoding is performed by using the property that adjacent sample values have a large correlation with each other. The law (hereinafter abbreviated as DPCM) is known.

FIG. 4 is a block diagram showing a configuration of the most general DPCM coding apparatus for predicting a prior value. 10 is a sample value input terminal, 12 is a subtractor for subtracting the predicted value from the input sample value, 14 is a quantizer,
16 is an inverse quantizer, 18 is an adder, 20 is a D flip-flop for outputting a predicted value, 22 is an error correction coding circuit, 24
Is an output terminal of the encoded code.

The subtractor 12 calculates the sample value (8 bits) of the input terminal 10 from
Predicted value of output of D flip-flop 20 (8 bits)
, The quantizer 14 quantizes the difference value of the output of the subtractor 12, and outputs a DPCM code (4 bits). The error correction encoding circuit 22 adds an error correction parity to the output of the quantizer 14 and outputs the result to an output terminal 24. In addition, the inverse quantizer 16
Dequantizes the DPCM code (4 bits) output from the quantizer 14 and outputs a representative difference value (8 bits). The adder 18 adds the previous value prediction value to the output of the inverse quantizer 16, and the D flip-flop 20 delays this by one sample interval and applies the result to the subtracter 12 and the adder 18 as the previous value prediction value.

In general, the difference value from the previous predicted value is a very small value. Therefore, by encoding and transmitting the difference value, large compression is possible.

FIG. 5 is a block diagram showing the configuration of a decoding apparatus corresponding to FIG. 26 is an input terminal of the transmitted DPCM code, 28 is an error detection and correction circuit, 30 is an inverse quantizer, 32 is an adder, and 34 is D
A flip-flop, 36 is a switch, 38 is a one-line delay unit, and 40 is a decoded value output terminal.

The input data at the input terminal 26 is detected and corrected by an error detection and correction circuit 28 during the data transmission.
The error detection and correction circuit 28 applies the DPCM code to the inverse quantizer 30 and outputs an error flag (see FIG. 6) for controlling the switch 36 when the error cannot be corrected. The inverse quantizer 30 inversely quantizes the DPCM code and outputs a representative difference value, and the adder 32 adds the decoded previous value to the output of the inverse quantizer 30. The output of the adder 32 becomes the decoded value. The output of the adder 32 is delayed by one sample interval by the D flip-flop 34,
The value is fed back to the adder 32 as the previous value decoded value.

The output of the adder 32 is directly applied to the contact a of the switch 36, and is applied to the contact b of the switch 36 via the one-line delay unit 38. In general, it is known that in the DPCM encoding method, when an error occurs in a transmission path, the error propagates to subsequent decoded values until a decoded value of a PCM code obtained by quantizing the sample value itself is obtained next. . Therefore, the error detection and correction circuit 28
If an uncorrectable error is detected in the coded code, an error flag is set after the detection of the uncorrectable error, as shown in FIG. While the error flag is set, the switch 36 is switched to the contact b side to substitute, that is, correct, the sample value of the previous line. FIG. 6 shows the change of the decoded value at every other sample point due to this modification.

[Problems to be Solved by the Invention] However, in the above-described conventional example, since the sample value of one line before is substituted, a one-line delay unit is required, and there is a disadvantage that hardware is increased. Also, since all the decoded values after the uncorrectable encoded code is detected are substituted,
If there is no correlation between the sample value of the current line and the sample value one line before, there is a disadvantage that the image quality is greatly deteriorated. In such a case, as shown in FIG. 6, the difference between the sample value of the previous line and the sample value when there is no transmission path error is large, and the image quality is significantly deteriorated.

It is an object of the present invention to provide a decoding device free from such disadvantages.

[Means for Solving the Problems] A decoding apparatus according to the present invention provides a decoding apparatus which calculates a difference value between a sample to be coded and a sample preceding the sample to be coded by a predetermined period regardless of a state of a transmission path. Is a device that decodes an encoded code sequence obtained by encoding a decoded value of a sample preceding a predetermined period to a difference value corresponding to the encoded code to be decoded. Decoding means, and a substitute means for replacing the decoded value corresponding to the error-correctable encoded code with the decoded value of the sample preceding the predetermined period, using the decoded value output from the substitute means, The subsequent sample can be decoded by the decoding means without using the alternative means.

[Operation] By the above means, the decoded value corresponding to the erroneous encoded code is replaced with the immediately preceding decoded value having the highest correlation, so that the retouching error is extremely small, and the replacement decoded value , The correction error does not increase over time. Further, it is not necessary to use a one-line delay device, so that the circuit configuration is simplified and the cost is reduced.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
42 is a transmission data input terminal, 44 is an error detection and correction circuit, 46
Is an inverse quantizer, 48 is an adder, 50 is a switch which can be switched by an uncorrectable error code, 52 is a D flip-flop functioning as a delay unit of one sample interval, and 54 is an output terminal of a decoded value.

The error detection and correction circuit 44 receives the transmission data at the input terminal 42, detects and corrects an error during transmission, and supplies a DPCM code to the inverse quantizer 30. The error detection and correction circuit 44 also sets an error flag controlled by the switch 50 for one sample period for an uncorrectable transmission error, as shown in FIG.

The adder 48 adds the output (previous decoded value) of the D flip-flop 52 to the output of the inverse quantizer 46 (representative difference value). The output of the adder 48 is connected to the contact a of the switch 50.
The output of the D flip-flop 52 is connected to the contact b of 50. The signal selected by the switch 50 is supplied to the output terminal 54 as a decoded value and is also applied to the D flip-flop 52. That is, the switch 50 is normally connected to the contact a to select the output of the adder 48, but for an uncorrectable error, the switch 50 is set to 1 according to the error flag from the error detection and correction circuit 44.
It connects to the contact b only for the sample period and selects the previous decoded value.

FIG. 2 shows an operation example of FIG. An uncorrectable transmission error has occurred at the time of the fifth sample, and the incorrectly decoded sample value at that time is replaced with the decoded value of one sample before. Since the sample value one sample before has a very high correlation with the current sample value, the modification error in the decoded value is also very small. Thereafter, decoding is performed using the transmitted DPCM code, so that the retouching error falls within a certain value and does not increase. In particular, when an uncorrectable transmission error occurs in a sample having the same sample value as the sample value one sample before, the correction error is zero.

The portions of the inverse quantizer 46, the adder 48 and the switch 50 in FIG. 1 can be formed by a ROM table. FIG. 3 shows a block diagram of the configuration. 56 is a ROM as the decoding table. The ROM 56 has, as inputs, 4 bits for the DPCM code, 8 bits for the predicted value, 1 bit for the error flag output from the error detection and correction circuit 44, and has an 8-bit output. The ROM 56 is written so as to output the decoded value of the previous value, that is, the same sign as the output of the D flip-flop when the error flag is set. What is necessary is just to write so as to output a value obtained by adding the previous decoded value from the D flip-flop to the difference representative value by the sign.

In the above embodiment, the preceding value predictive encoding method has been described as an example.
It goes without saying that the present invention can be similarly applied to the inter-frame prediction coding method or the inter-line prediction coding method.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, since a one-line delay device is not used, the circuit configuration is simplified and the cost is reduced. Further, when correction is impossible, the preceding decoded value having a high correlation is substituted, so that the retouching error is extremely small. Further, since the subsequent decoding is performed by using the substitute recoding value, the retouching error does not increase with the passage of time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1, FIG. 3 is a configuration example in which a part of FIG. FIG. 5 is a block diagram showing a configuration of a conventional decoding device, and FIG.
The figure is an operation explanatory view of FIG. 42: input terminal, 44: error detection and correction circuit, 46: inverse quantizer, 4
8: adder, 50: switch, 52: D flip-flop, 54: output terminal

Claims (1)

(57) [Claims] An encoded code sequence obtained by encoding a difference value between a sample to be coded and a sample preceding the sample to be coded for a predetermined period, regardless of the state of the transmission path, is decoded. A decoding means for obtaining a new decoded value by adding a decoded value of a sample preceding the predetermined period to a difference value corresponding to an encoded code to be decoded; and an error-correctable encoded code. Substitute means for substituting the decoded value corresponding to the above with the decoded value of the sample preceding the predetermined period, and using the decoded value output from the substitute means,
A decoding apparatus, wherein a succeeding sample can be decoded by the decoding means without using the alternative means.