JPH03104275A - Gate array - Google Patents

Abstract

PURPOSE:To enable this device to perform suitable wiring and high integration by forming contacts in which each gate electrode of a MOSFET is connected to wiring end making up these contacts at the other side of the adjacent MOSFET so that they are provided in the neighborhood each other. CONSTITUTION:In a gate array (Sea of Gate) where cells are spread all over a chip, standard cells 70ij having the same form get near one another and they are arrayed in a lattice at equal intervals. In the standard cells 70ij, diffusion regions 72 and 74 which are formed into a drain or a source are formed on the surface of a semiconductor substrate 68 and each gate electrode 76 is formed on the above substrate 68 between the diffusion regions 72 and 74 through regions 75. Each contact hole formation region 88 of the standard cells 70ij gets close to each contact hole formation region 84 and each contact hole formation region 78 of an adjacent standard cells 70ij+1 and then, each contact hole formation region 84 of the standard cells 70ij+1 gets close to each contact hole formation region 80 of the adjacent standard cells 70ij. Cells of a P channel and an N channel in the standard cells 70ij are arrayed regularly in such a way that they are adjoining each other in one way or another.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 13 to 15) Problems to be solved by the invention Examples of means and actions for solving the problems First embodiment (1 to 5B) Figure) Second embodiment (Figures 6 and 7) Third embodiment (Figures 8 and 9) Fourth embodiment (Figures 10 and 11) P-channel MOSFET and N-channel MOS
Example of arrangement of FETs (Figures 12A-C) Effects of the invention [IA required] Enables suitable wiring and high integration for gate arrays in which MOSFETs are arranged in a lattice pattern as basic cells on the surface of a semiconductor substrate. With the aim of
On the region between the OsFETs, contacts connecting the gate electrode of the MOSFET and the wiring of the upper wiring layer are formed on both end sides of the gate electrode, and one of the MOSFETs adjacent in one direction of the arrangement of the MOSFETs is formed. The contacts are arranged close to each other.

[Industrial Application Field] The present invention relates to a gate array in which MOSFETs are arranged as basic cells in a lattice pattern on the surface of a semiconductor substrate.

[Conventional technology 1] Today, electronic devices are becoming more highly functional, smaller in quantity, and more diverse, and their life cycles are becoming shorter and shorter. This is required by electronic equipment manufacturers. Gate arrays, which are representative of mask slices, meet these requirements. A gate array is a structure in which a large number of basic cells each connected with 4 to 8 transistors are arranged on the surface of a semiconductor substrate.Semiconductor manufacturers prepare a large number of these cells and arrange the connections between the basic cells based on the user's required specifications. By wiring, a desired logic LSI can be provided at low cost and in a short period of time, and is suitable for small-volume, high-mix production.

FIG. 13 shows a planar pattern of a part of a conventional gate array, and FIG. 14 shows a cross section taken along the line XTV-XIV in FIG. 13. The basic cell lO of this gate array consists of four MO
SFETs are connected and configured as shown in FIG.

The basic cell IO has rectangular diffusion areas l@12, 14 and l6
are arranged in parallel, a gate electrode 18 is formed between the diffusion regions 12 and 14, and a gate electrode 20 is formed between the diffusion regions 14 and 16. Contact hole formation regions 22, 24, and 26 are formed on the diffusion regions 12, 14, and 16, respectively, for connecting these to wiring (not shown) in the upper wiring layer.
4 each are shown. Further, lead portions 28 are provided extending from both ends of the gate electrode 18 . A contact hole formation region 30 is shown on this lead portion 28 for connecting it to an upper wiring layer. Similarly, lead portions 32 extend from both ends of the gate electrode 20 . This lead part 32
At the top, a contact hole shaped region 34 for connection to the upper wiring layer is shown.

The basic cell 10 is composed of a pair of cells having the same configuration as the above structure, and in FIG. 13, the corresponding structure element is numbered by adding 30 to the number of the above structure element. It is attached. In addition, the lead parts 28 and 58 and the leads R32 and 62
are connected to each other and located on a straight line.

In Fig. 13, P and N are each P channel MOS.
This shows a MOS with no SN channel. Further, in FIG. 14, 21 is a gate oxide film. Hereinafter, a contact hole forming region and a contact formed by forming a contact hole in this region and filling it will be indicated by the same reference numerals for convenience.

Such a basic cell 10 can be configured by, for example, connecting the contacts 24 and 54, connecting the contacts 30 and 34, connecting the contacts 22 and 52, and further connecting the contacts 26 and 56 using wiring. An inverter with relatively large driving capacity can be constructed.

[Problems to be Solved by the Invention] However, when constructing a sufficient logic circuit, such as a memory cell, with a small drive capacity, the basic cell 10 itself is relatively large, so the occupied area becomes too large, and it is difficult to achieve high integration. It was hindering me. To solve this problem, even if you simply divide the basic cell IO to make it smaller, when connecting basic cells in parallel, the connection wiring may cross or become too long, making it impossible to make suitable wiring or It was difficult to realize integration.

SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide a gate array that allows suitable wiring and high integration.

[Means for Solving the Problems] The configuration of a gate array according to the present invention will be described with reference to the drawings of the embodiments.

In this gate array, a P-channel MOSFET and an N-channel MOSFET are arranged adjacent to each other as basic cells on the surface of a semiconductor substrate. 1st
, 6, 8, and 10, these MOSFETs 70
,? 0A to 70C are arranged in a grid pattern (the intervals may not be equal). MOSFET70,? 0A~7
Contacts 78, 80, 7 are provided on the source and drain regions of 0C to connect the regions to the wiring in the upper wiring layer.
8A to 78C and 80A to 80C are formed.

On the area between adjacent MOSFETs 70, 70A to 70C, MOSFETTO, ? Contacts 84, 88, 84A-84C, 88A-88 connecting the gate electrodes 76, 76A-76C of 0A-70C and the wiring of the upper wiring layer
Shape C. And MOSFET70? 0A~7
In one direction (vertical direction, horizontal direction, or diagonal direction in Figures 1, 6, 8, and 10) of the 0C arrangement, adjacent MOSFETs 7
0, 70Δ to 70C, one contact 84 and 88 (Fig. 1), 84A and 88A (Fig. 6), 84B and 88B or 84B and 84B (Fig. 8), 88C and 88C (Fig.
Figure) should be placed close to each other.

[Function] The wiring pattern shown in FIG. 3A14A, which composes the circuit of FIGS. 3B and 4B, and the 5A, which constitutes the circuit of FIG. 5B.
As is clear from the wiring patterns shown in Figures 17, 9, and 11, if the gate array according to the present invention is used to construct a logic circuit, each wiring can be distributed at almost uniform density without crossing each other. Since the wiring length between basic cells can be made relatively short, suitable wiring and high integration can be achieved.

[Example] Hereinafter, one embodiment of the present invention will be described based on the drawings.

(1) First Embodiment FIG. 1 shows a planar pattern of a part of the gate array of the first embodiment, and FIG. 2 shows an enlarged cross section taken along the line ■--■ in FIG.

This gate array is a spread type gate array (Sea
of Gate), and a basic cell 701J of the same shape (in FIG. 1, is
J = 1 to 3> are arranged close to each other in a grid pattern at equal intervals. In the basic cell 701, diffusion regions 72 and 74 that serve as drains or sources are formed on the surface of a semiconductor substrate 68, and a gate electrode 76 is formed on the semiconductor substrate 68 via 75 between the diffusion regions 72 and 74. ing. These diffusion regions 72 and 74 and the gate electrode 76
The planar shape of the active region T including the active region T is a rectangle (although it is a square in FIG. 1, it is generally a rectangle). Further, the shape of the gate electrode 76 is point symmetrical with respect to the center point of the active region T, and has a step shape. Diffusion regions 7 are disposed on the diffusion regions 72 and 74, respectively.
Contact hole formation regions 78 and 80 are shown for connecting 2 and 74 with wiring (not shown) in the upper wiring layer, and when connecting to the upper wiring, contact holes are formed in these contact hole forming regions. A contact is formed with Al, for example, to fill this area.These contact hole shaped areas 78 and 80 are symmetrical to each other with respect to the center point of the active region T.A lead portion 82 is formed at one end of the gate electrode 76. It has been extended.

A contact hole-shaped region 84 (shown as a circle in FIG. 1, but generally square) is shown on the tip of the lead portion 82. As shown in FIG. 2, a gate oxide film 77 extends below the lead portion 82, and a field oxide film 85 is provided below it. Similarly, gate electrode 76
A lead portion 86 extends from the other end, and a contact hole formation region 88 is shown on the tip of this lead R86.

Each contact hole forming region 88 of the basic cell 70l is close to the contact hole forming region 84 and the contact hole forming region 78 of the first horizontally adjacent basic cell 70+j++. Further, the contact hole type area 84 of the basic cell 70 1J+1 is located in the horizontally adjacent basic cell 7 in FIG.
It is close to the contact hole forming region 80 of No. 01.

The basic cells 70, . . . have P channel cells and N channel cells regularly arranged next to each other in some form. In the following wiring example, it is assumed that P channels (P) and N channels (N) are alternately arranged in each column in the horizontal direction in FIG.

■Wiring forming the CMOS inverter Figure 3A shows the wiring pattern forming the CMOS inverter, which is formed in the upper layer of the basic cell 701J.
FIG. 3B shows the circuit diagram of FIG. 3A.

This inverter is connected to contact 78 of basic cell 70.1.
and contact 80 of basic cell 7021 are connected by wiring 101, contact 88 of basic cell 70.1 and contact 88 of basic cell 70.1 are connected by wiring 102, and contact 80 of basic cell 7o, 1 is connected to power supply. Supply line VI
IO is connected by a wiring 103, and a contact 78 of the basic cell 702l and a power supply line V55 are connected by a wiring 104. This inverter's human power terminal I
N is a point on the wiring 102, and the output terminal OUT is on the wiring 1
It is a point on 01.

As is clear from FIG. 3A, if an inverter is constructed using the gate array of the first embodiment, the wiring lines are distributed at an almost uniform density without crossing each other, and the wiring length between basic cells is relatively short. Since it is short, suitable wiring and high integration can be realized.

■ Wiring of a two-man powered NAND gate Figure 4A shows the wiring pattern constituting the two-man powered NAND gate, which is formed on the upper layer of the basic cell 701J.
FIG. 4B shows the circuit diagram of FIG. 4A.

In this two-man-powered NAND gate, the contact 78 of the basic cell 7o11, the contact 78 of the basic cell 70I2, and the contact 8o of the basic cell 702l are connected by a wiring 201, and the contact 7? and basic cell 70,
, are connected to the contacts 78 of the basic cell 70.2 by the wiring 202, and the contacts 84 of the basic cell 70.
Contact 88 of , and contact 88 of basic cell 70
are connected by a wiring 204, and a contact 80 of the basic cell 70.1 and a contact 80 of the basic cells 70, 2 are connected by a wiring 205. One input terminal INI of this two-man powered NAND gate is a point on the wiring 203, the other input terminal IN2 is a point on the wiring 204,
The output terminal OUT is a point on the wiring 201. Further, the wiring 205 is a power supply line ■. .

The wiring 204 is connected to the power supply line VSS.

As is clear from FIG. 4A, if a two-man-powered NAND gate is constructed using the gate array of the first embodiment, each wiring will be distributed at an almost uniform density without crossing each other, and the wiring length between basic cells will be shortened. Since it is relatively short, suitable wiring and high integration can be realized.

? Wiring of an inverter with three unit CMOS inverters connected in parallel Figure 5A shows the wiring pattern of an inverter with three unit CMOS inverters connected in parallel, which is formed on the upper layer of the basic cell 701J. , showing the circuit diagram of FIG. 5A.

This inverter has basic cells 70■, 701■, 70I
, and the basic cells 7021, 70, 2,
70,, are connected to each contact 80 of the basic cell 70++-basic cell 70, (i, j=1.
The contacts 84 and 88 of 2) are connected by a wiring 302, and the contacts 80 of the basic cells 70, 70,, 70,, are connected by a wiring 303, and the basic cells 70,, 70
Each contact 78 of 22, 70, . . . is connected by a wiring 304. Input terminal IN of this inverter
is a point on the wiring 302, and the output terminal OUT is on the wiring 30
It is a point on l. Moreover, the wiring 303 is a power supply line V,,
The wiring 304 is connected to the power supply line Vss.

As is clear from FIG. 5A, if this inverter is constructed using the gate array of the first embodiment, each wiring will be distributed at an almost uniform density without crossing each other, and the wiring lengths between basic cells will be comparable. Since the target length is short, suitable wiring and high integration can be realized.

(2) Second Embodiment FIG. 6 shows a plane pattern of a part of the gate array of the second embodiment.

Is this gate array also the same basic cell shape as the one shown in Figure 1? 0AIJ (in Figure 6, i, j = 1 to 3
) are arranged close to each other in a grid pattern.

In FIG. 6, structural elements corresponding to the structural elements in FIG. This basic cell? 0A
In the IJ, the gate electrode 76A is formed along the diagonal line of the square active area TA, and the gate electrode 76A is formed along the diagonal line of the square active area TA. 2A and defeat area 7
The surface shape of 4A is an isosceles right triangle sandwiching gate electrode 76A. Also, regarding the column diagonally upward to the right in Figure 6, is it the basic cell? 0A IJ gate electrode terminal 84A and basic cell 70,. The contact hole forming regions 88A of 1J-1 are located close to each other.

In addition, P channel MOSFET and N channel MOSFET
S FET is arranged in the same way as in the first embodiment,
In the following wiring example, it is assumed that P channels and N channels are arranged alternately in each column in the horizontal direction of FIG. 6 (the same applies to the third and fourth embodiments below).

■Is the wiring diagram of an inverter in which three unit CMOS inverters are connected in parallel shown in Figure 7 a basic cell? 0 A A wiring pattern forming the same circuit as the circuit shown in FIG. 5B, which is formed in the upper layer of the IJ, is shown. Wiring corresponding to the wiring in FIG. 5A is designated by the same reference numeral as in FIG. 5A and is designated by the letter A.

This inverter has a basic cell 70Δ+J(i=1,''=
1 to 3) each contact 78A and basic cell 70A+,+
(i = 2, j = 1 to 3) are connected to each contact 80A by a wiring 301A, and the basic cell 70AH (i = 1, j
=1~3), 70A, each contact 88A of 1 and basic cell? The contacts 84A of OA+J (j=2, j=1 to 3) and 70A, 2 are connected by the wiring 302A, and each contact 80 of the basic cell 70AIJ (i=1.j=1 to 3)
A is connected with wiring 303A, basic cell 7 0AIJ
(i=2, j-1 to 3)} 78A are connected by a wiring 304A.

As is clear from FIG. 7, if this inverter is constructed using the gate array of the second embodiment, the wiring lines will be distributed at an almost uniform density without crossing each other, and the wiring length between basic cells will be relatively short. Since it is short, suitable wiring and high integration can be realized.

(3) Third Embodiment FIG. 8 shows a plane pattern of a part of the gate array of the third embodiment.

Similar to the gate array shown in FIG. 1, this gate array has the same basic cell 70BiJ (i
, j=1 to 4) are arranged close to each other in a grid pattern. In FIG. 8, structural elements corresponding to the structural elements in FIG.

In this gate array, i of basic cell 7 0 B IJ
The column whose sum is an even number is the basic cell 70 l in Figure 6.
A column having the same shape as i and in which the sum of l and j is an odd number has a shape obtained by rotating the basic cell 70l by 90 degrees clockwise or counterclockwise around the center of the active region TB. That is, the basic cells 70BI adjacent in the horizontal or vertical direction in FIG.
The gate electrodes 76B of the cells J are perpendicular to each other, and the gate electrodes 76B of the basic cells 70B1 adjacent to each other in the diagonal direction in FIG.
6B are located parallel to each other or on the same straight line. In other words, it has a symmetrical shape with respect to a line passing through the center between the columns in FIG. 8 of the basic cells 70B IJ. In FIG. 8, these mutually symmetrical structural elements are given the same reference numerals.

In this gate array, between the contact hole-shaped hollow regions 84B and 88B of the adjacent basic cells 70Bl, for the vertical column, horizontal column, diagonally upward-rightward column, and diagonally upward-leftward column of the basic cells 70B0 in FIG. The contact hole forming regions 84B or the contact hole forming regions 88B are located close to each other.

(2) Wiring of an inverter in which three unit CMOS inverters are connected in parallel FIG. 9 shows a wiring pattern forming the same circuit as the circuit shown in FIG. 5B, which is formed in the upper layer of the basic cell 70BIJ. Wiring corresponding to the wiring in FIG. 5A is designated by the same reference numeral as in FIG. 5A and is designated by B.

This inverter connects each contact 78B of the basic cell 70BIJ (i-l1J2l-3) and the basic cell 70B+4 (
i=2,''=1 to 3) are connected to each contact 80 to 13 by a wiring 301B, and the basic cell 70B. (i=1.2
, j=1 to 3) are connected by a wiring 302B, and the basic cell 70BIJ (i=1,
Each contact }80B of j=1 to 3) is connected by a wiring 303B, and each contact 78B of a basic cell 70BIj (summer=2, j=1 to 3) is connected by a wiring 304B.

As is clear from FIG. 9, if this inverter is constructed using the gate array of the third embodiment, each wiring will be distributed at an almost uniform density without crossing each other, and the wiring lengths between basic cells will be comparable. Since the target length is short, suitable wiring and high integration can be realized.

(4) Fourth Embodiment FIG. 10 shows a plane pattern of a part of the gate array of the fourth embodiment.

This gate array also has basic cells 70CIJ (11 to 3, j
= 1 to 4) are arranged close to each other in a grid pattern. In FIG. 10, structural elements corresponding to the structural elements in FIG.

In this gate array, the surface area ratio of the diffusion regions '72C and 74C is approximately 1:2, and the gate electrode 76C is parallel to one side of the square active region TC. Also, the basic cell 70 C I in the vertical column of FIG.
J all have the same shape, and the basic cell 70CIJ in the horizontal row is the basic cell 70CIJ rotated by 180, and has the same shape as the basic cell 70CIJ+1 next to it.

Therefore, for the horizontal row of basic cells 70CIJ in FIG. 10, the gate electrode terminals 84C of the adjacent basic cells 70C,
and contacts} 88C are located close to each other.

(2) Wiring of an inverter in which three unit CMOS inverters are connected in parallel FIG. 11 shows a wiring pattern forming the same circuit as the circuit shown in FIG. 5B, which is formed in the upper layer of the basic cell 70C14. The wiring corresponding to the wiring in Figure 5A includes
The same reference numerals as in the figure and C are attached.

This inverter has a basic cell 'roclJ (i=t,j
=1, 3: i=2, j=2) and the basic cell 70CIJ (i=tSj=2: i=2, j=
1.3) are connected to each contact 80C by a wiring 301C, and the basic cell 70C+J (i=1.2, "=1 to 3>
Each contact 84C and 88C of basic cell 70C. contact 7
8C is connected with wiring 303C, basic cell 70CIJ
Each contact 78C (1=2, j=1.3) and the contact 80C of the basic cell 70C22 are connected by a wiring 304C.

As is clear from FIG. 11, if this inverter is constructed using the gate array of the third embodiment, each wiring will be distributed at an almost uniform density without crossing each other, and the wiring lengths between basic cells will be comparable. Since the target length is short, suitable wiring and high integration can be realized.

(5) P-channel MOSFET and N-channel MOS
FET arrangement example basic cell 70l' is sufficient as long as P-channel MOSFET and N-channel MOSFET are regularly arranged next to each other in some way, and the arrangement example is shown in 12A.
- Shown in Figure 12C. In the figure, Pch Tr,, N-ch
Tr. represent P-channel MOSFET%N-channel MOSFET, respectively. Each rectangular region represents a diffusion region, and gate electrodes and the like are not shown.

12A and 12B show a case in which P-channel MOSFETs and N-channel MOSFETs are alternately arranged in one row in one direction. Figure 12C is a P-channel MOSFE
T and N channel MOSFE T alternately in one direction.
This shows the case where each column is arranged.

[Effects of the Invention] As explained above, if a logic circuit is constructed using the gate array according to the present invention, each wiring can be distributed at a substantially uniform density without crossing each other, and the wiring length between basic cells can be made relatively short. Therefore, it is possible to realize an excellent effect of realizing suitable wiring and high integration.

[Brief explanation of drawings]

1 to 5B show the first gate array of the present invention.
Regarding the embodiment, FIG. 1 is a planar pattern diagram of a part of the gate array, FIG. 2 is an enlarged cross-sectional view taken along line 1 in FIG. Figure 3B is the circuit diagram of Figure 3A, Figure 48 is a wiring pattern diagram configuring a two-man powered NAND gate, Figure 4B is the circuit diagram of Figure 4A, and Figure 5A is a circuit diagram of three unit CMOS inverters connected in parallel. 5B is a circuit diagram of FIG. 5A. 6 and 7 relate to the second embodiment of the present invention, FIG. 6 is a plan pattern diagram of a part of the gate array, and FIG.
3 is a wiring pattern diagram configuring the same circuit as the circuit in FIG. B. FIG. 8 and 9 relate to the third embodiment of the present invention, FIG. 8 is a plan pattern diagram of a part of the gate array, and FIG. 9 is a plan view of a part of the gate array.
3 is a wiring pattern diagram configuring the same circuit as the circuit in FIG. B. FIG. 10 and 11 relate to the fourth embodiment of the present invention, FIG. 10 is a plane pattern diagram of a part of the gate array, and FIG. 11 is a wiring pattern constituting the same circuit as the circuit in FIG. 5B. It is a diagram. 12A to 12C are diagrams showing examples of arrangement of P-channel MOSFETs and N-channel MOSFETs. 13 to 15 relate to the conventional example, FIG. 13 is a plane pattern diagram of a part of the gate array, FIG. 14 is a cross-sectional view taken along the xm-xm line of FIG. 2 is a circuit diagram of a basic cell 10 shown in FIG. In the figure, 10, 70,? 0A to 70C are basic cells l2, l4, l
6, 72,? 2A-72C, 74, 74A-74C are diffusion regions 18, 20, 58, 62, 76, 76A-76C are gate electrodes 22, 24, 26, 78, 78A-18C, 80, 80
A to 80C are lead parts 28, 32, 82, 82A to 82C, 88, 88A to 8
8C is a contact hole shaped area (contact in the wiring diagram) 68 is a semiconductor substrate 101-104, 201-206, 301-304, 3
01A~304A, 301B~304B, 301
C to 304C are wiring] ゛, TASTB, TC are active regions 101 to 104: Wiring Figure 3B Ω group WI4B Figure 301 to 304: Wiring 301A to 304A: Wiring wiring constituting the same circuit as the circuit in Figure 5B Rematurn Figure 7 Partial planar pattern of gate array (Second example) No. 6
Figure 8 301B to 304B: Wiring No. 9 wiring pattern constructing the same circuit as the circuit in Figure 5B
Figures 301C to 304C: Wiring pattern 11 constituting the same circuit as the circuit in Figure 5
Figure P-ah Tr. : P-channel MOSFET N-ah Tr. : N-channel MOSFET P-channel MOSFET and N-channel MOSFET
Arrangement row 1 2A Figure 2 P-ah Tr. : P-channel MOSFET N-ah Tr. : N-channel MOSFET P-channel MOSFET and N-channel MOSFET
Arrangement row 1 2B Figure 1 m ψ 〇12 P-ah Tr. : P channel IIOSFETI
I-ah Tr. : IT channel MOSFETP
Channel ilOsFET and 舊channel IIOSFE
Circuit diagram of the basic cell 1o shown in FIG. 14, FIG. 13, and FIG. 15.

Claims (1)

[Claims] A P-channel MOSFE is provided on the surface of the semiconductor substrate (68).
The T-channel and N-channel MOSFETs are adjacent to each other as basic cells, and the basic cells are arranged in a grid pattern, and the MOSFETs are arranged on the area between the adjacent MOSFETs.
Contacts (84, 88, 84A to 76C) connecting the gate electrodes (76, 76A to 76C) and the wiring of the upper wiring layer
88C) is formed on both end sides of the gate electrode, and the MOSF
A gate array characterized in that the contacts of one of the MOSFETs adjacent to each other in one direction of the ET array are arranged close to each other.