JPH03104236A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device with good yield by forming a low concentration diffused layer through introducing an impurity into a substrate with a temporary gate electrode pattern being used as a mask, forming a temporary side wall pattern on the side wall of the temporary gate electrode pattern and forming a high concentration diffused layer through using the temporary gate electrode pattern and side wall pattern as a mask. CONSTITUTION:A gate electrode 6 is formed by etching back to leave a high melting point metal layer 5 only in an aperture 4 through anisotropic RIE. At that time, the gate electrode 6 is formed to the above part of low concentration diffused layers 36a, 36b constituting an LDD structure via a gate insulating film 34. Thus, the gate electrode 6 is provided to the above part of the low concentration diffused layers 36a, 36b so that the gate electrode 6 can have a larger width than, even if the thickness thereof is same as, the case of prior art wherein a gate electrodes is provided on a substrate 31 via the gate insulating film 34 to increase the metal amount, thus a larger amount of the carrier can be controlled. Therefore, the controllability of the gate electrode 6 and the element characteristics can be improved.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device that can improve device characteristics, improve device reliability, and realize device planarization by reducing unevenness. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can improve the manufacturing yield by forming a gate insulating film on a substrate, and forming a temporary gate electrode pattern on the gate insulating film. a step of introducing an impurity into the substrate using the temporary gate electrode pattern as a mask to form a low concentration diffusion layer; a step of forming a temporary sidewall pattern on the sidewall of the temporary gate electrode pattern; By introducing impurities into the substrate using the temporary gate electrode pattern and the temporary sidewall pattern as a mask to form a high concentration diffusion layer, a source/drain consisting of the low concentration diffusion layer and the high concentration diffusion layer is formed. a step of forming a diffusion layer; and a step of forming a film having etching selectivity with respect to the temporary gate electrode pattern and the temporary sidewall pattern so as to cover the temporary gate electrode pattern and the temporary sidewall pattern. selectively etching the film having etching selectivity to expose the temporary gate electrode pattern and the temporary sidewall pattern; and using the film having etching selectivity as a mask to expose the temporary gate electrode pattern. The method is designed to include the steps of forming an opening by removing the pattern and the temporary sidewall pattern, and forming a gate electrode within the opening.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device, and
The present invention can be applied to a manufacturing method for forming an S-FET in a completely self-aligned manner, and particularly relates to a manufacturing method for a semiconductor device that can reduce unevenness and realize element planarization.

The degree of integration of MOS-LSI is increasing year by year, and as MOS-LSI becomes highly integrated, MOS-LSI
It is also necessary to downsize the MOS-FET, which is a structural element that constitutes I.

In order to reduce the size of MOS-FET elements, it is necessary not only to simply reduce the size but also to adopt a special structure due to short channel effects, hot carrier effects, etc. In the case of NMOS, this is called an LDD structure. It is. On the other hand, PMOS takes the form of a buried LDD structure.

[Conventional technology]

FIGS. 2(a) to 2(e) are diagrams illustrating a conventional method of manufacturing a semiconductor device. The illustrated example semiconductor device is an LDD type NM.
This is a case where it is applied to an OS-FET.

In these figures, 31 is a p-type substrate made of Si, for example, and 32 is a p-type channel stone bar, for example.
33 is a field oxide film made of, for example, Sin; 34
For example, Sin. 35 is a gate electrode made of, for example, polysilicon, 36a and 36b are n
The type 1 low concentration diffusion layer 37 is, for example, a Sin. 38a and 38b are, for example, n-type high concentration diffusion layers, 39a is a source diffusion layer consisting of a low concentration diffusion layer 36a and a high concentration diffusion layer 38a, and 39b is a low concentration diffusion layer 3.
6b and a drain diffusion layer consisting of a high concentration diffusion layer 38b,
40 is, for example, LTO (Low Te+mperature
41a, 4lb, 41G are contact holes, 42a, 42b, 42C are wiring layers made of A/, for example, and the wiring layer 42a is a contact hole 41.
The wiring layer 42b is a wiring that contacts the source diffusion layer 39a through a contact hole 4lb, and the wiring layer 42c is a wiring that contacts the gate electrode 35 through a contact hole 41c. This is the wiring that is in contact with 39b.

Next, the manufacturing method will be explained.

Here, Si is first deposited on the substrate 3l by, for example, the CVD method.
n, and Si. N. After depositing a silicon oxide film with a thickness of, for example, 200 nm and a silicon nitride film with a thickness of, for example, 1500 nm, and buttering the silicon nitride film by, for example, RIE to form a mask made of the silicon nitride film. , for example, the impurity is B (boron) and the energy is 5.
A channel stopper 32 is formed in the substrate 3l by ion implantation at 0 KeV and a dose of IXIOI3c+i-.Next, using a mask made of a silicon nitride film,
After oxidizing the base vi31 by LOGOS oxidation to form a film Ii33 having a film thickness of, for example, 5,000 people (field oxidation), the silicon nitride film and silicon oxide film used as a mask are removed (FIG. 2(a)).

Next, as shown in FIG. 2(b), the substrate 31 is oxidized by, for example, thermal oxidation to form a gate insulating film 34 having a thickness of, for example, 150 to 200 layers. Next, using a lamp annealing device (a heating furnace may be used), the temperature is, for example, 1000°C.
The gate insulating film 34 is nitrided in an NH3 gas atmosphere for a processing time of 100 seconds.

At this time, the upper part of the gate insulating film 34 and the interface between the gate insulating film 34 and the substrate 31 are particularly nitrided. Next, Figure 2 (c
), a gate electrode 35 is formed by depositing polysilicon to a thickness of, for example, 2,000 by, for example, the CVD method, and then patterning the polysilicon by, for example, RIE. Next, for example, if the impurity is P and the energy is 5,
After introducing an impurity into the gate electrode 35 by ion implantation with a dose of 0 KeV and a dose of I to XIO "elm-" to make it an n-type,
Impurities are introduced into the substrate 31 using the gate electrode 35 as a mask by ion implantation at KeV with a dose of IXIO"Cal-" to form n-type low concentration diffusion layers 36a and 36b. Note that here, impurities are introduced into the gate electrode 35 to make it n-type, but it is not necessary to introduce impurities.

Next, as shown in FIG. 2(d), SiOz is deposited to a thickness of, for example, 1500 to 2000 to cover the gate electrode 35 by, for example, the CVD method, and an anisotropic R
After forming a side wall 37 on the side wall of the gate electrode 35 by etching bank SiO t by IE, for example, the impurity is As, the energy is 40 KeV, and the dose is 3.
By ion implantation of XIQ15aa-'', impurities are introduced into the substrate 31 using the gate electrode 35 and sidewalls 37 as masks to form n-type high concentration diffusion layers 38a and 38b.
form. At this time, an LDD structure is formed with a source diffusion layer 39a consisting of a low concentration diffusion layer 36a and a high concentration diffusion layer 38a, and a drain diffusion layer 39b consisting of a low concentration diffusion layer 36b and a high concentration diffusion layer 38b.

Then, after forming the eyebrow insulating film 40 and forming contact holes 41a, 4lb, and 41c in the interlayer insulating film 40, the source diffusion layer 39a1, the gate electrode 35, and the drain diffusion layer 39b are connected through the contact holes 41a, 4lb%, and 41C. The wiring layers 42a and 42 are in contact with each other.
By forming 42b and 42c, a semiconductor device having a structure as shown in FIG. 2(e) is completed.

As for the manufacturing method of the LDD type PMOS-FET, the same manufacturing method as that for the above NMOS may be used, and the conductivity type of each layer may be changed as appropriate from that of the NMOS.

[Problems to be Solved by the Invention] However, in the conventional manufacturing method of LDD type NMOS-FET explained in FIGS. If the width is not sufficiently optimized, there is a problem in that the device characteristics will deteriorate significantly in the initial stage of a stress test.

Specifically, when a transistor is actually incorporated into a product and operated, a voltage is applied or not applied to the source electrode, gate electrode, and drain electrode. As this process is repeated many times, the concentration, especially in the diffusion layer, gradually increases. For this reason, the holes may be further accelerated and collide with the crystal lattice to create new electrons. Then, the carriers are transferred to the gate insulating film 34.
It is driven into the air and creates a charge trap. Each electrode is formed on the gate insulating film 34, and the same effect as when a voltage is constantly applied is produced. For this reason, if the device is used for a long period of time, the number of truncations increases, resulting in deterioration of device characteristics such as switching speed. The degree of this deterioration is particularly significant at the beginning of use.

In addition, in the case of PMOS, in order to form p-type high concentration diffusion layers (source/drain), it is necessary to "shallow" the Si substrate, so it is necessary to make the Si substrate non-quality (amorphous) in advance. ) is necessary. To do this, before implanting boron difluoride ions (BF.''), Si' ions (Ge' ions may also be used) must be temporarily implanted into the St base.These ions are also implanted into the sidewalls. For this reason, there was a problem in that after a stress test, the deterioration (life) of the device deteriorated by two orders of magnitude compared to the case where the deterioration of the element characteristics did not lead to quality deterioration.

Specifically, when a p type high concentration diffusion layer is formed deeply, a carrier spill phenomenon occurs between the p~ type low concentration diffusion layer formed directly under the sidewall and the p type high concentration diffusion layer. occurs, and since there are more carriers in the p° type high concentration diffusion layer, the carriers spill out toward the p type low concentration diffusion layer. Therefore, in order to further reduce the channel width, it was necessary to form a shallow p-type high concentration diffusion layer. Also,
BF in the amorphous state. ” is used to make it difficult for the channeling phenomenon to occur.Si +
This is used to make the p-type high concentration diffusion layer shallow.

In addition to the above problem, another problem is that unevenness is formed on the surface of the substrate due to the gate electrode and the field oxide film.

Furthermore, according to the conventional method of manufacturing a semiconductor device as shown in FIGS. 2(a) to 2(e), there is a risk of disconnection of the wiring layer. In other words, since it is formed on the uneven surface of the gate electrode and field oxide film, unevenness is formed all over the substrate surface, and the glabella insulating film is formed on this surface using a normal method (for example, CVD formation). Then, the interlayer insulating film is formed to have a uniform thickness over the entire surface, and naturally the surface of the interlayer insulating film also becomes uneven. Furthermore, contact holes are formed on this uneven surface and electrodes are filled in, but problems arise such as the patterning cannot be carried out with high accuracy, which in turn affects the manufacturing yield.

Therefore, the present invention can improve device characteristics, improve device reliability, reduce unevenness and realize device planarization, and improve manufacturing yield. The purpose is to provide a method for manufacturing semiconductor devices. [Means for Solving the Problems] In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes the steps of forming a gate insulating film on a substrate, and forming a temporary gate electrode pattern on the gate insulating film. a step of forming;
a step of introducing impurities into the substrate using the temporary gate electrode pattern as a mask to form a low concentration diffusion layer; a step of forming a temporary sidewall pattern on the sidewall of the temporary gate electrode pattern; and a step of forming a temporary sidewall pattern on the sidewall of the temporary gate electrode pattern. A source/drain diffusion layer consisting of the low concentration diffusion layer and the high concentration diffusion layer is formed by introducing impurities into the substrate using the electrode pattern and the temporary sidewall pattern as a mask to form a high concentration diffusion layer. a step of forming a film having etching selectivity with the temporary gate electrode pattern and the temporary sidewall pattern so as to cover the temporary gate electrode pattern and the temporary sidewall pattern; A step of selectively etching the film having selectivity to expose the temporary gate electrode pattern and the temporary sidewall pattern, and etching the temporary gate electrode pattern and the temporary sidewall pattern using the film having etching selectivity as a mask. The method includes the steps of: forming an opening by removing the sidewall pattern; and forming a gate electrode within the opening. [Function] As shown in FIGS. 1(a) to 1(f), the present invention provides a substrate 3
1, a gate insulating film 34 is formed on the gate insulating film 34.
A temporary gate electrode pattern l is formed on the sidewall of the temporary gate electrode pattern 1, and impurities are introduced into the substrate 3l using the temporary gate electrode pattern l as a mask to form low concentration diffusion layers 36a and 36b. A temporary sidewall pattern 2 is formed. Next, impurities are introduced into the substrate 31 using the temporary gate electrode pattern 1 and the temporary sidewall pattern 2 as masks to form high concentration diffusion layers 38a and 38.
b is formed, the low concentration diffusion layers 36a, 36
Temporary gate electrode pattern 1 and temporary sidewall pattern 2 are formed so that source/drain diffusion layers 39a and 39b consisting of high concentration diffusion layers 38a and 38b are formed and cover temporary gate electrode pattern l and temporary sidewall pattern 2. sidewall pattern 2 and a film 3 with etching selectivity (
For example, a Si 3 Nm film) is formed, the film with etching selectivity is selectively etched to expose the temporary gate electrode pattern 1 and the temporary sidewall pattern 2, and the film 3 with etching selectivity is masked. After the temporary gate electrode pattern l and the temporary sidewall pattern 2 are removed to form the opening 4, the opening 4 is removed.
A gate electrode 6 is formed therein.

Therefore, according to the present invention, the gate electrode 6 can be formed on the low concentration diffusion layers 36a and 36b via the gate insulating film 34, and the gate electrode 6 can be made of a high melting point metal, so that the device characteristics can be improved. It becomes possible to improve the reliability of the device. Furthermore, it becomes possible to realize flattening of the element by reducing unevenness, and it becomes possible to improve the manufacturing yield. Details will be explained in Examples.

〔Example〕

The present invention will be explained below based on the drawings. Figure l(a)
-(g) are diagrams illustrating an embodiment of the method for manufacturing a semiconductor device according to the present invention. The illustrated example semiconductor device is applied to an LDD type NMOS-FET.

In these figures, the same reference numerals as in FIGS. 2(a) to (e) indicate the same or corresponding parts, 1 is a temporary gate electrode pattern made of, for example, poly-Si, and 2 is a temporary sidewall pattern made of, for example, Sing. , 3 is a film having etching selectivity with respect to the temporary gate electrode pattern 1 and the temporary sidewall pattern 2, and is made of Si, N. It is made of a silicon nitride film (or a silicon oxide film such as SiO2). 4 is an opening for forming a gate electrode, 5 is a high melting point metal layer made of a high melting point metal such as W, and 6 is a gate electrode made of a high melting point metal such as W.

Next, the manufacturing method will be explained.

Here, first, Si is deposited on the substrate 31 by, for example, the CVD method.
n! and St., N. After depositing a silicon oxide film with a thickness of, for example, 200 and a silicon nitride film with a thickness of, for example, 1,500, and forming a mask by buttering the silicon nitride film by, for example, RIE, (Boron), energy is 50 KeV and dose is I
XIO13al-” (7) Group 131 by ion implantation
A channel stopper 32 is formed within. Next, using a mask made of a silicon nitride film, the substrate 31 is oxidized by LOGOS oxidation to form a field oxide film 33 having a film thickness of, for example, 5000, and then the silicon nitride film and the silicon oxide film used as the mask are removed. <Figure 1 (a)>
).

Next, as shown in FIG. 1B, the substrate 31 is oxidized by, for example, thermal oxidation to form a gate insulating film 34 having a thickness of, for example, 150 to 200 layers. Next, using a lamp annealing device (a heating furnace may be used), the temperature is, for example, 1000°C.
, the gate insulating film 34 is nitrided in an NH3 gas atmosphere for a processing time of 100 seconds. At this time, the gate insulating film 34
In particular, the upper part of the gate insulating film 34 and the interface between the gate insulating film 34 and the substrate 31 are nitrided. Next, as shown in FIG. 1(c), for example, C
After depositing polysilicon to a film thickness of, for example, 2,000 layers using the VD method, the polysilicon is patterned using, for example, RIE to form a temporary gate electrode 1 .

Next, for example, the impurity is P (phosphorus), the impurity is introduced into the temporary gate electrode pattern l by ion implantation with an energy of 50 KeV, and a dose of IXIO "elm-" to make it an n-type. , energy is 50
At KeV, the dose is I x 10"C!m-" (7)
Impurities are introduced into the substrate 31 by t-ion implantation using the temporary gate electrode pattern 1 as a mask to form n-type low concentration diffusion layers 36a and 36b. Note that it is not necessary to introduce impurities into the temporary gate electrode pattern l. Next, the first
As shown in Figure (d), stow is deposited to a thickness of, for example, 1,500 to 2,000 to cover the temporary gate electrode pattern 1 by, for example, the CVD method, and by, for example, anisotropic RIE.
By Sin. After forming a temporary sidewall pattern 2 on the sidewall of the temporary gate electrode pattern 1 by etching bank, for example, the impurity is A3% and the energy is 40KeV.
Impurities are introduced into the substrate 31 by ion implantation at a dose of 3×10” am−2 using the temporary gate electrode pattern 1 and the temporary sidewall pattern 2 as masks to form n-type high concentration diffusion layers 38a and 38b. At this time, an LDD structure is formed of a source diffusion layer 39a consisting of a low concentration diffusion Ji 36a and a high concentration diffusion layer 38a, and a drain diffusion layer 39b consisting of a low concentration diffusion layer 36b and a high concentration diffusion ii 38b. Next, for example, Temporary gate electrode pattern 1 and temporary sidewall pattern 2 are formed by CVD method.
For example, the thickness of SizNa is 2000 mm over the entire surface so as to cover the
A film 3 deposited manually and having etching selectivity with a temporary gate electrode pattern 1 and a temporary sidewall pattern 2
form. After this, the surface of this film 3 (StiN* film) inherits the unevenness of the underlying layer as it is, so the surface of this film 3 is coated with SOG (Sp
-In On Glass) is spin-coated to a sufficient thickness and heated to solidify to make the surface flat.
Next, the surface of this SOG is subjected to RIE, and a controlled etch bank is performed until most of the temporary sidewall pattern 2 is exposed. At this time, the temporary gate electrode pattern 1 is also exposed. Next, as shown in FIG. 1(e), the temporary gate electrode pattern 1 and the temporary sidewall pattern 2 are all removed by, for example, wet etching using the film 3 having etching selectivity as a mask to form a gate electrode. opening 4
form. At this time, the gate insulating film 34 is exposed within the opening 4. Next, the opening 4 is formed by, for example, a spatter method.
The high melting point metal layer 5 is formed by depositing W to a thickness of, for example, 4,000 to cover the wafer.

Next, as shown in FIG. 1(f), for example, an anisotropic RI
A gate electrode 6 is formed by etching back the high melting point metal layer 5 using E so that it remains only in the opening 4. At this time, the gate electrode 6 is formed through the gate insulating film 34 up to the low concentration diffusion layers 36a and 36b forming the LDD structure. Then, after forming a glabellar insulating film 40 made of PSG by, for example, the CVD method and forming contact holes 41a, 4lb, and 41c in the glabellar insulating II 140, the source diffusion layer 3 is formed through the contact holes 41a and 41bs 41c.
9a, wiring layers 42a, 42b, and 42c are formed to make contact with the gate electrode 6 and the drain diffusion layer 39b, thereby completing the semiconductor device having the structure shown in FIG. That is, in the above embodiment, since the gate electrode 6 was formed so as to extend over the low concentration spreading layers 35a and 36b through the gate insulating film 34, Compared to the case where the gate electrode 35 is provided, the width of the gate electrode 6 can be increased even though the thickness is the same as in the conventional case, and the amount of metal can be increased, so that more carriers can be controlled. Therefore, controllability of the gate electrode 6 can be improved, and device characteristics can be improved. Therefore, the reliability of the device can also be improved.

Further, since the gate electrode 6 can be made of a high melting point metal such as W, the resistance can be lowered than in the conventional case of using polysilicon, and gate delay can be prevented. Furthermore, the heat resistance can be improved compared to the case where a metal other than a high melting point metal is used, and the film thickness can be made thinner. Further, by spin coating a material such as SOG on the surface of the substrate 31 which has irregularities formed by the gate electrode 6 and the field oxide film 33, the surface can be made flat.
In the end, it is possible to reduce the unevenness and achieve flattening of the device, thereby improving the manufacturing yield. Further, after removing the temporary gate electrode pattern 1 and the temporary sidewall pattern 2 to form the inside of the opening 4, the high melting point metal layer 5 is buried in the opening 4 to form the gate electrode 6. , the low-concentration diffusion layers 36a, 36b, the high-concentration diffusion layers 38a, 38b, and the gate electrode 6 can be formed by aligning them in perfect self-alignment.

In the above embodiment, the gate electrode 6 is made of a high melting point metal such as W, but the present invention is not limited to this, and the gate electrode 6 may be made of a high melting point metal silicide such as W3i, TiSi, etc. It is also possible to configure Although the above embodiment has been described with reference to the case where it is applied to an LDD type NMOS-FET, the present invention is not limited thereto, and may be applied to an LDD type PMOS-FET.

〔Effect of the invention〕

According to the present invention, device characteristics can be improved, device reliability can be improved, and device flattening can be realized by reducing unevenness, and manufacturing yield can be improved. There is an effect that it can be done.

31...Substrate, 34...Gate insulating film, 36a, 36b...Low concentration diffusion layer, 37...
...Side wall, 38a, 38b...High concentration diffusion layer, 39a...
...Source diffusion layer, 39b...Drain diffusion layer.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating an embodiment of a semiconductor device manufacturing method according to the present invention, and FIG. 2 is a diagram illustrating a conventional manufacturing method. ...temporary gate electrode pattern, ...temporary sidewall pattern, ...film with etching selectivity, ...opening, ... ...High melting point metal layer, ...gate electrode, Figure 1 explaining the manufacturing method of one embodiment. Figure 1 explaining the manufacturing method of one embodiment. Figure 1 explaining the manufacturing method of one embodiment. Fig. 2 A diagram explaining the manufacturing method of the conventional example Fig. 2 A diagram explaining the manufacturing method of the embodiment Example l Fig. 2 A diagram explaining the manufacturing method of the conventional example

Claims (1)

[Claims] A step of forming a gate insulating film on a substrate, a step of forming a temporary gate electrode pattern on the gate insulating film, and introducing an impurity into the substrate using the temporary gate electrode pattern as a mask. forming a temporary sidewall pattern on the sidewall of the temporary gate electrode pattern; and forming a low concentration diffusion layer on the substrate using the temporary gate electrode pattern and the temporary sidewall pattern as a mask. forming a source/drain diffusion layer consisting of the low concentration diffusion layer and the high concentration diffusion layer by introducing impurities to form a high concentration diffusion layer, and forming the temporary gate electrode pattern and the temporary sidewall. forming a film having etching selectivity with the temporary gate electrode pattern and the temporary sidewall pattern so as to cover the pattern; and selectively etching the film with etching selectivity to form the temporary gate electrode pattern and the temporary sidewall pattern. exposing the electrode pattern and the temporary sidewall pattern;
forming an opening by removing the temporary gate electrode pattern and the temporary sidewall pattern using the film having etching selectivity as a mask; and forming a gate electrode within the opening. A method for manufacturing a featured semiconductor device.