JPH03104126A - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JPH03104126A JPH03104126A JP24143689A JP24143689A JPH03104126A JP H03104126 A JPH03104126 A JP H03104126A JP 24143689 A JP24143689 A JP 24143689A JP 24143689 A JP24143689 A JP 24143689A JP H03104126 A JPH03104126 A JP H03104126A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- compound semiconductor
- electron
- semiconductor layer
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 150000001875 compounds Chemical class 0.000 title claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
化合物半導体装置に関し,
マイクロ波帯で高耐圧高電子移動度を有する化合物半導
体装置を目的とし,
化合物半導体基板上に順次積まれた第1の化合物半導体
層,第2の化合物半導体層.第3の化合物半導体層と,
該第3の化合物半導体層に接触するゲート電極と,該ゲ
ート電極の両側に配置され該第2の化合物半導体層に電
気的に接続するソース・ドレイン電極とを有し,かつ該
第1の化合物半導体層は第lの電子親和力を有する電子
走行層,該第2の化合物半導体層は第1の電子親和力よ
り小さい第2の電子親和力を有する電子供給層,該第3
の化合物半導体層は該第2の化合物半導体層より小さい
電子親和力を有する高抵抗層である化合物半導体装置に
より構或する。[Detailed Description of the Invention] [Summary] Regarding a compound semiconductor device, with the aim of a compound semiconductor device having high breakdown voltage and high electron mobility in the microwave band, first compound semiconductor layers sequentially stacked on a compound semiconductor substrate, Second compound semiconductor layer. a third compound semiconductor layer;
a gate electrode in contact with the third compound semiconductor layer; source/drain electrodes arranged on both sides of the gate electrode and electrically connected to the second compound semiconductor layer; The semiconductor layer includes an electron transport layer having a lth electron affinity, the second compound semiconductor layer having an electron supply layer having a second electron affinity smaller than the first electron affinity, and the third compound semiconductor layer having an electron transport layer having a second electron affinity.
The compound semiconductor layer is constituted by a compound semiconductor device which is a high resistance layer having a smaller electron affinity than the second compound semiconductor layer.
本発明は化合物半導体装置に関する。 The present invention relates to a compound semiconductor device.
マイクロ波帯において高耐圧高電子移動度を有する化合
物半導体装置が要求されている。There is a demand for compound semiconductor devices having high breakdown voltage and high electron mobility in the microwave band.
現在,離島や過疎地域との通信,或いは衛星放送にマイ
クロ波が使用されている。パワーの大きいマイクロ信号
を増幅するためには,その信号に耐える増幅素子が要求
される。Currently, microwaves are used for communication with remote islands and depopulated areas, and for satellite broadcasting. In order to amplify high-power microsignals, an amplification element that can withstand the signals is required.
従来.マイクロ波帯において電子移動度を有する化合物
半導体装置として高電子移動度トランジスタ(HEMT
)がある。Conventional. High electron mobility transistor (HEMT) is a compound semiconductor device that has electron mobility in the microwave band.
).
第4図は従来の高電子移動度トランジスタを説明するた
めの断面図であり,1は化合物半導体基板,2はバッフ
ァ層,3は電子走行層,4は電子供給層,6はゲート電
極,7,8はソース・ドレイン電極,2DECは2次元
電子ガスを表す。FIG. 4 is a cross-sectional view for explaining a conventional high electron mobility transistor, in which 1 is a compound semiconductor substrate, 2 is a buffer layer, 3 is an electron transport layer, 4 is an electron supply layer, 6 is a gate electrode, and 7 is a cross-sectional view for explaining a conventional high electron mobility transistor. , 8 are source/drain electrodes, and 2DEC is a two-dimensional electron gas.
ところで,電子供給層4は不純物濃度が高くゲート電極
6の金属層とのポテンシャル障壁が低いので,ゲートに
大信号が加わると多大なゲート電流が流れてしまい,増
幅動作が不能になるといった問題を生じる。また,多大
なゲート電流が流れる結果,機能が劣化してトランジス
タの信頼度が低下するといった問題もある。By the way, since the electron supply layer 4 has a high impurity concentration and a low potential barrier with the metal layer of the gate electrode 6, when a large signal is applied to the gate, a large gate current flows, causing the problem that the amplification operation becomes impossible. arise. Additionally, as a result of a large amount of gate current flowing, there is the problem that functionality deteriorates and the reliability of the transistor decreases.
電子供給層4の不純物濃度を低くして抵抗を高くすれば
ゲート耐圧は上がるが,今度はソース・ドレイン抵抗が
増加するといった問題が生じる。If the impurity concentration of the electron supply layer 4 is lowered and the resistance is increased, the gate breakdown voltage will increase, but this will cause a problem such as an increase in source/drain resistance.
(発明が解決しようとする課題)
従って,従来の高電子移動度トランジスタでは大信号の
マイクロ波入力に対する増幅の際,問題が生じる。(Problems to be Solved by the Invention) Therefore, problems arise in conventional high electron mobility transistors when amplifying a large signal microwave input.
本発明は.ゲート耐圧を高くする構造により,ソース・
ドレイン抵抗を増加させずに大信号のマイクロ波入力に
対する増幅を信頼性よく行う化合物半導体装置を提供す
ることを目的とする。The present invention is. Due to the structure that increases the gate breakdown voltage, the source
An object of the present invention is to provide a compound semiconductor device that can reliably amplify a large microwave input signal without increasing drain resistance.
第1図は本発明の化合物半導体装置を説明するための断
面図であり,1は化合物半導体基板,2はバッファ層,
3は第1の化合物半導体層であって電子走行層,4は第
2の化合物半導体層であって電子供給層,5は第3の化
合物半導体層であって高抵抗層,6はゲート電極,7,
8はソース・ドレイン電極,2DEGは2次元電子ガス
を表す。FIG. 1 is a cross-sectional view for explaining the compound semiconductor device of the present invention, in which 1 is a compound semiconductor substrate, 2 is a buffer layer,
3 is a first compound semiconductor layer, which is an electron transport layer; 4 is a second compound semiconductor layer, which is an electron supply layer; 5 is a third compound semiconductor layer, which is a high resistance layer; 6 is a gate electrode; 7,
8 represents a source/drain electrode, and 2DEG represents a two-dimensional electron gas.
上記課題は,化合物半導体基板l上に順次積層された第
1の化合物半導体層3,第2の化合物半導体層4,第3
の化合物半導体層5と,該第3の化合物半導体層5に接
触するゲート電極6と,該ゲート電極6の両側に配置さ
れ該第2の化合物半導体層4に電気的に接続するソース
・ドレイン電極7,8とを有し,かつ該第1の化合物半
導体層3は第1の電子親和力を有する電子走行層,該第
2の化合物半導体層4は第1の電子親和力より小さい第
2の電子親和力を有する電子供給層,該第3の化合物半
導体層5は該第2の化合物半導体層4より小さい電子親
和力を有する高抵抗層である化合物半導体装置によって
解決される。The above problem is solved by the first compound semiconductor layer 3, the second compound semiconductor layer 4, and the third compound semiconductor layer stacked sequentially on the compound semiconductor substrate l.
a compound semiconductor layer 5, a gate electrode 6 in contact with the third compound semiconductor layer 5, and source/drain electrodes arranged on both sides of the gate electrode 6 and electrically connected to the second compound semiconductor layer 4. 7 and 8, the first compound semiconductor layer 3 is an electron transit layer having a first electron affinity, and the second compound semiconductor layer 4 is an electron transit layer having a second electron affinity smaller than the first electron affinity. This problem is solved by a compound semiconductor device in which the third compound semiconductor layer 5 is a high-resistance layer having a smaller electron affinity than the second compound semiconductor layer 4.
本発明では第1図の如く,ゲート電極6と電子供給層4
の間に電子供給層4より電子親和力の小さい高抵抗層5
を設けてある。第2図はそのエネルギーバンド図である
。高抵抗層5を設けることにより,ポテンシャル障壁が
高くなり,電子供給層4からゲート電極6への電子の流
入が困難となる。その結果,マイクロ波の大信号がゲー
トに人力されてもゲート電流は流れにくくなり,ゲート
耐圧が向上する。In the present invention, as shown in FIG.
In between, a high resistance layer 5 having a lower electron affinity than the electron supply layer 4 is formed.
is provided. Figure 2 is its energy band diagram. By providing the high resistance layer 5, the potential barrier becomes high, making it difficult for electrons to flow from the electron supply layer 4 to the gate electrode 6. As a result, even if a large microwave signal is manually applied to the gate, the gate current will hardly flow, improving the gate withstand voltage.
一方,ソース・ドレイン電極7,8に接続する電子供給
層4はソース・ドレイン抵抗を小さく維持することがで
きる。On the other hand, the electron supply layer 4 connected to the source/drain electrodes 7 and 8 can maintain low source/drain resistance.
(実施例)
第3図(a). (b)は実施例を説明するための断面
図であり,lは化合物半導体基板,2はバッファ層.3
は第lの化合物半導体層であって電子走行層,4は第2
の化合物半導体層であって電子供給層.5は第3の化合
物半導体層であって高抵抗層,6はゲート電極,7.8
はソース・ドレイン電極32DECは2次元電子ガスを
表す。(Example) Figure 3(a). (b) is a cross-sectional view for explaining an example, where l is a compound semiconductor substrate, 2 is a buffer layer. 3
is the l-th compound semiconductor layer, which is the electron transit layer, and 4 is the second compound semiconductor layer.
The compound semiconductor layer is an electron supply layer. 5 is a third compound semiconductor layer, which is a high resistance layer; 6 is a gate electrode; 7.8
The source/drain electrode 32DEC represents a two-dimensional electron gas.
以下,これらの図を参照しながら本発明の化合物半導体
装置を製造する工程について説明する。Hereinafter, steps for manufacturing the compound semiconductor device of the present invention will be explained with reference to these figures.
第3図(a)参照
化合物半導体基板l上にバッファ層.第1の化合物半導
体層3,第2の化合物半導体層4,第3の化合物半導体
層5を分子線エビタキシー(MBE)により積層する。FIG. 3(a) A buffer layer is formed on the reference compound semiconductor substrate l. The first compound semiconductor layer 3, the second compound semiconductor layer 4, and the third compound semiconductor layer 5 are laminated by molecular beam epitaxy (MBE).
各層の組或と厚さは次の如くである。The composition and thickness of each layer are as follows.
1.化合物半導体基板 GaAs
2.バッファ層 GaAs 2000人
3,第1の化合物半導体層 GaAs 300人4.
第2の化合物半導体層
(nドープ) n ” −AIGaAs 600
人5.第3の化合物半導体層
(アンドープ) i −AIGaAs 150人
第3図(b)参照
第3の化合物半導体層5の上に,ゲート電極6形戒用の
レジストパターン(図示せず)を形威してアルミニウム
(At)を蒸着し,ゲート電極6を形戒する。1. Compound semiconductor substrate GaAs 2. Buffer layer GaAs 2000 people 3. First compound semiconductor layer GaAs 300 people 4.
Second compound semiconductor layer (n-doped) n”-AIGaAs 600
People 5. Third compound semiconductor layer (undoped) i -AIGaAs 150 people See Figure 3(b) On the third compound semiconductor layer 5, a resist pattern (not shown) for gate electrode 6 is formed. Aluminum (At) is then vapor-deposited to form the gate electrode 6.
ゲート電極6をマスクにして,第3の化合物半導体層5
をエッチング除去する。Using the gate electrode 6 as a mask, the third compound semiconductor layer 5 is
Remove by etching.
次いで.ゲート電極6の両側の第2の化合物半導体層4
上に, AuGe/Ni/Auを蒸着してソース・ドレ
イン電極7.8を形或し,拡散熱処理により少なくも第
1の化合物半導体層3内まで拡散させて合金層を形或す
る。Next. Second compound semiconductor layer 4 on both sides of gate electrode 6
AuGe/Ni/Au is deposited thereon to form source/drain electrodes 7.8, and diffused into at least the first compound semiconductor layer 3 by diffusion heat treatment to form an alloy layer.
第lの化合物半導体層である電子走行層3には第2の化
合物半導体層である電子供給層4から電子が供給されて
,2次元電子ガスが形威される。Electrons are supplied to the electron transport layer 3, which is the first compound semiconductor layer, from the electron supply layer 4, which is the second compound semiconductor layer, and a two-dimensional electron gas is formed.
かくして,ソース・ドレイン抵抗は低く,ゲート耐圧は
高い化合物半導体装置が実現される。In this way, a compound semiconductor device with low source/drain resistance and high gate breakdown voltage is realized.
この化合物半導体装置は.マイクロ波帯での大信号入力
を.信頼性よく増幅する。This compound semiconductor device. Large signal input in the microwave band. Amplify reliably.
なお,電子供給層である第2の化合物半導体層4は電子
走行層である第1の化合物半導体層3よりも電子親和力
が小さく,高抵抗層である第3の化合物半導体層5は第
2の化合物半導体層4よりも電子親和力が小さい。実施
例では第3の化合物半導体層5としてi−AIGaAs
を示したが,さらに電子親和力の小さいAIAsやAI
Sn等の化合物半導体層を使用することもできる。Note that the second compound semiconductor layer 4, which is an electron supply layer, has a lower electron affinity than the first compound semiconductor layer 3, which is an electron transit layer, and the third compound semiconductor layer 5, which is a high resistance layer, has a lower electron affinity than the first compound semiconductor layer 3, which is an electron transit layer. The electron affinity is smaller than that of the compound semiconductor layer 4. In the embodiment, i-AIGaAs is used as the third compound semiconductor layer 5.
However, AIAs and AI, which have even smaller electron affinities,
A compound semiconductor layer such as Sn can also be used.
以上説明したように,本発明によればソース・ドレイン
抵抗は低く,ゲート耐圧の高い化合物半導体装置が実現
される。As described above, according to the present invention, a compound semiconductor device with low source/drain resistance and high gate breakdown voltage can be realized.
本発明の化合物半導体装置は,マイクロ波帯での大人力
信号の増幅に大きな効果を奏するものである。The compound semiconductor device of the present invention is highly effective in amplifying adult power signals in the microwave band.
である。It is.
図において,
1は化合物半導体基板,
2はバッファ層,
3は第lの化合物半導体層であって電子走行層,4は第
2の化合物半導体層であって電子供給層,5は第3の化
合物半導体層であって高抵抗層,6はゲート電極.
7.8はソース・ドレイン電極.
2DEGは2次元電子ガスIn the figure, 1 is a compound semiconductor substrate, 2 is a buffer layer, 3 is a first compound semiconductor layer, which is an electron transport layer, 4 is a second compound semiconductor layer, which is an electron supply layer, and 5 is a third compound semiconductor layer. The semiconductor layer is a high resistance layer, and 6 is a gate electrode. 7.8 is the source/drain electrode. 2DEG is two-dimensional electron gas
第l図は本発明の化合物半導体装置を説明するための断
面図,
第2図はエネルギーバンド図,
第3図(a). (b)は実施例を説明するための断面
図,
第4図は従来例の断面図
エネIl/ギーバ′ンド図
g2目
(帥
実 杷倒
万3図
咲
来
中Fig. 1 is a cross-sectional view for explaining the compound semiconductor device of the present invention, Fig. 2 is an energy band diagram, and Fig. 3(a). (b) is a sectional view for explaining the embodiment, and Figure 4 is a sectional view of the conventional example.
Claims (1)
物半導体層(3)、第2の化合物半導体層(4)、第3
の化合物半導体層(5)と、該第3の化合物半導体層(
5)に接触するゲート電極(6)と、該ゲート電極(6
)の両側に配置され該第2の化合物半導体層(4)に電
気的に接続するソース・ドレイン電極(7、8)とを有
し、かつ 該第1の化合物半導体層(3)は第1の電子親和力を有
する電子走行層、該第2の化合物半導体層(4)は第1
の電子親和力より小さい第2の電子親和力を有する電子
供給層、該第3の化合物半導体層(5)は該第2の化合
物半導体層(4)より小さい電子親和力を有する高抵抗
層であることを特徴とする化合物半導体装置。[Claims] A first compound semiconductor layer (3), a second compound semiconductor layer (4), and a third compound semiconductor layer, which are sequentially stacked on a compound semiconductor substrate (1).
a compound semiconductor layer (5), and a third compound semiconductor layer (5);
a gate electrode (6) in contact with the gate electrode (6);
), the first compound semiconductor layer (3) has source/drain electrodes (7, 8) arranged on both sides of the second compound semiconductor layer (4) and electrically connected to the second compound semiconductor layer (4); the second compound semiconductor layer (4) has an electron affinity of
The third compound semiconductor layer (5) is a high-resistance layer that has a smaller electron affinity than the second compound semiconductor layer (4). Characteristic compound semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24143689A JPH03104126A (en) | 1989-09-18 | 1989-09-18 | Compound semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24143689A JPH03104126A (en) | 1989-09-18 | 1989-09-18 | Compound semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03104126A true JPH03104126A (en) | 1991-05-01 |
Family
ID=17074281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24143689A Pending JPH03104126A (en) | 1989-09-18 | 1989-09-18 | Compound semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03104126A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5473177A (en) * | 1990-11-16 | 1995-12-05 | Sumitomo Electric Industries, Ltd. | Field effect transistor having a spacer layer with different material and different high frequency characteristics than an electrode supply layer thereon |
JPH0837292A (en) * | 1994-07-25 | 1996-02-06 | Nec Corp | Field effect semiconductor device |
KR100484486B1 (en) * | 2002-10-18 | 2005-04-20 | 한국전자통신연구원 | Nitride semiconductor field effect transistor(FET) fabrication method thereof |
-
1989
- 1989-09-18 JP JP24143689A patent/JPH03104126A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5473177A (en) * | 1990-11-16 | 1995-12-05 | Sumitomo Electric Industries, Ltd. | Field effect transistor having a spacer layer with different material and different high frequency characteristics than an electrode supply layer thereon |
JPH0837292A (en) * | 1994-07-25 | 1996-02-06 | Nec Corp | Field effect semiconductor device |
US6049097A (en) * | 1994-07-25 | 2000-04-11 | Nec Corporation | Reliable HEMT with small parasitic resistance |
KR100484486B1 (en) * | 2002-10-18 | 2005-04-20 | 한국전자통신연구원 | Nitride semiconductor field effect transistor(FET) fabrication method thereof |
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