JPH03103700U

JPH03103700U -

Info

Publication number: JPH03103700U
Application number: JP1238090U
Authority: JP
Priority date: 1990-02-08
Filing date: 1990-02-08
Publication date: 1991-10-28

Description

[Brief explanation of drawings]

第１図は本考案の一実施例である音場構成装置
１の簡略化した電気的構成を示すブロツク図、第
２図はストア領域ｍａのストア内容を示す図、第
３図は処理回路６における操作スイツチ群７から
の入力操作の判別処理を説明するためのフローチ
ヤート、第４図は本実施例の時間延長スイツチ＋
の操作に基づく時間延長処理を説明するためのフ
ローチヤート、第５図は本実施例の音場の切換再
生処理を説明するためのフローチヤート、第６図
は音場切換スイツチＥＦＣの操作に基づく音場切
換処理を説明するためのフローチヤート、第７図
はメモリ操作スイツチＳｍｉの操作に基づく登録
処理を説明するためのフローチヤート、第８図は
メモリ操作スイツチＳｍｉの操作に基づく読出処
理を説明するためのフローチヤート、第９図は本
実施例の音場構成装置１における音場遷移図、第
１０図は従来の音場構成装置における音場遷移図
である。１……音場構成装置、４……デジタルシグナル
プロセツサ、６……処理回路、９……リードオン
リメモリ（ＲＯＭ）、１０……ランダムアクセス
メモリ（ＲＡＭ）、Ｆ……定数、Ｃ……モードカ
ウンタ値、ＥＦＣ……音場切換スイツチ、＋……
時間延長スイツチ、−……時間短縮スイツチ、Ｓ
ｍａ〜Ｓｍｄ……メモリ操作スイツチ、Ｍ１〜Ｍ
３……サブメモリ、Ｍｔ……退避メモリ、ｍａ〜
ｍｄ……副メモリ、ｔ１……切換時間、Ｔ……基
準音場、Ｙ……調整音場。 FIG. 1 is a block diagram showing a simplified electrical configuration of a sound field configuration device 1 which is an embodiment of the present invention, FIG. 2 is a diagram showing the stored contents of the store area ma, and FIG. 3 is a processing circuit 6. FIG. 4 is a flowchart for explaining the process of determining the input operation from the operation switch group 7 in the time extension switch + of the present embodiment.
FIG. 5 is a flowchart for explaining the sound field switching reproduction processing of this embodiment, and FIG. 6 is a flowchart for explaining the time extension processing based on the operation of the sound field switching switch EFC. A flowchart for explaining the sound field switching process, FIG. 7 is a flowchart for explaining the registration process based on the operation of the memory operation switch Smi, and FIG. 8 is a flowchart for explaining the readout process based on the operation of the memory operation switch Smi. FIG. 9 is a sound field transition diagram in the sound field configuration device 1 of this embodiment, and FIG. 10 is a sound field transition diagram in the conventional sound field configuration device. DESCRIPTION OF SYMBOLS 1...Sound field configuration device, 4...Digital signal processor, 6...Processing circuit, 9...Read only memory (ROM), 10...Random access memory (RAM), F...Constant, C... Mode counter value, EFC...Sound field selection switch, +...
Time extension switch, -...Time reduction switch, S
ma~Smd...Memory operation switch, M1~M
3...Sub memory, Mt...Evacuation memory, ma~
md...Sub-memory, t1...Switching time, T...Reference sound field, Y...Adjustment sound field.

Claims

[Claims for Utility Model Registration] (1) A memory that stores constants for configuring multiple types of reference sound fields for each sound field, and a memory that is operated to switch between the reference sound fields. a first operating switch; a second operating switch operated to change the constant; and a second operating switch that selectively switches and reads constants from the memory in response to the output of the first operating switch;
a constant changing means for changing the read constant in response to an output from an operating switch; a sound field made up of the changed constant; and a constant that is a reference for the sound field and is stored in the memory. 1. A sound field configuration device comprising: a sound field switching configuration means configured to alternately switch and configure a sound field. (2) The sound field configuration device according to claim 1, wherein the sound field switching configuration means automatically switches the sound field alternately at predetermined time intervals. (3) The sound field switching configuring means responds to the first operating switch, and when the sound field is configured by alternately switching, and when the first operating switch is operated, the sound field switching configuration means responds to the first operating switch. 3. The sound field configuring device according to claim 2, wherein the switching of the constant is stopped and the sound field is constructed using the changed constant.