JPH03101313A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the variation of the delay time of an output signal from a reset release signal by delaying the release of the resetting of one flip flop compared to that of the other flip flop and setting a threshold as against the reset release signal of the flip flop to a different value so as to realize the time difference. CONSTITUTION:When FET of Vth=O[V] is used for the flip flop(FF), the ratio of the gate widths of FET 51 and 52 in the D-type flip flop(DEF) 31 is set to 1.5:1.0, and the ratio of the gate widths of the other FF 32-38 is to 1:1, for example. Thus, the threshold of DFF 31 as against the reset release signal becomes high compared to the threshold of the other FF 32-33. Thus, the output of a dual modulus pre-scaler (PSC) 6 appears after prescribed time from the release of the resetting of DFF 31 without fail and it does not depend on the order of the reset release of the other FF 32-38. Then, time till the leading-in of a frequency and the establishment of synchronization is shortened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor circuits, and in particular to a prescaler IC suitable for reducing the power consumption of equipment, which is widely used in the field of mobile communication such as car phones and mobile phones. It is related to.

[Conventional technology]

BACKGROUND OF THE INVENTION In recent years, due to the development of the information society, demand for mobile wireless communication devices such as car phones and mobile phones has increased. It is inherently difficult to supply power to these communication devices due to their mobile nature, and the key is to reduce the power consumption of these devices to efficiently use the power in their built-in batteries and to lengthen the charging interval. .

For this reason, gallium arsenide (GaAs) ICs, which are said to have low power consumption, can replace conventional silicon (St) ICs.
are being developed for these applications.

In Fig. 2, the signals often used for generating the reference signal are:
1 is a block diagram of a PLL (phase-locked loop) circuit using a dual modulus prescaler method (pulse swirl method).

1 is a reference oscillation source (frequency f) made using a crystal oscillator, etc., 2 is a phase frequency comparator (φDet), and 3 is a low-pass filter (LP) that removes high frequency components from the output of the phase frequency comparator 2. F), 4 is a voltage-frequency converter (VCO: voltage-contrast oscillator) that changes its oscillation frequency according to the signal output from the phase frequency comparator 2. In addition, 5 is a terminal that outputs a reference signal (frequency f.) based on the reference oscillation source 1 using this system, and 6 is a terminal that can be divided into two ways: 1/P and 1/P+1 (where P is a natural number). Dual conflict modulus
Prescaler (PSC), 7 is a modulus counter (MC) that counts the output of PSC6 and controls the division ratio of PSC6, 8 counts the output of PSC6, resets MC7, and outputs the input signal of phase frequency comparator 2. This is a program counter (PC) to be generated.

Here, the count number A of MC7 is the frequency division ratio P of PSC6
, is set smaller than the count number N of PC8. The operation of this PSC 6 is as follows.

■At the beginning of its operation, PSC6 sets the output of VCO4 to P.
The frequency is divided by +1.

(2) When the number of outputs from the PSC6 reaches A, the frequency division ratio of the PSC6 is changed to P from then on by the MC7. By this time, there have been (P+1)XA pulse inputs to the input of the PSC6.

■Furthermore, when the number of outputs from PSC6 is counted (N-A), the total number of outputs from PSC6 is N, and MC7 is reset to the initial state by PC8, and the frequency division ratio of PSC6 returns to P+1. do.

During this period, there were px (N-A) pulse inputs to the PSC6.

■Therefore, from the initial state to the initial state again, there were (P+1)XA+PX (N-A)-A+PXN inputs to PSC6, and by changing the value of A by 1, f Reference signals f differing only in frequency.

can be obtained.

In this system, the highest speed operation is required and the PSC6 is the cause of the increase in power consumption, and attempts are being made to realize this circuit with GaAs1C in order to reduce power consumption.

FIG. 4 shows an example of a block configuration of a PSC 6 that performs a typical 128/129 two-modulus operation.

PSC6 consists of three D-type flip-flops (DFF
) 11 to 13 and five T-type flip-flops (
TFF) 14 to 18, and each FF constitutes a frequency dividing circuit. The reference signal output from the PLL circuit is returned to the clock input terminal 19 of the PSC 6 configured inside the PLL circuit. The PSC 6 performs a frequency division operation of 128/129 according to a control signal input to the terminal 20. Then, the input reference signal is frequency-divided and the frequency-divided signal is output to the terminal 21. Based on this frequency-divided signal, a signal is given to the phase frequency comparator 2, which compares and adjusts the phase of the reference signal output from the system with the phase of the oscillation signal given from the reference oscillation source 1, and outputs the reference signal. The signal is synchronized to the oscillating signal.

On the other hand, in order to further reduce the power consumption of equipment, rather than having the system operate all the time, it is necessary to
One possible method is to perform nloff frequently and operate intermittently to reduce average power consumption. However, a characteristic of the PLL circuit using the phase frequency comparator 2 is that synchronization can be established quickly when the phase and frequency are close together, but it takes time to establish synchronization when they are far apart. be. Therefore, turn off the power frequently.
Even in the case of nloff, the input of the phase frequency comparator 2 must be close to the phase of the reference oscillation source 1 to some extent.

Therefore, the following PSC was devised. In other words, P
A reset terminal is provided on each FF that makes up the SC, and the reset is canceled after the power is turned on so that the input of the phase frequency comparator 2 will not be out of phase with the reference oscillation source 1 even immediately after the power is turned on. A method was tried.

[Problem to be solved by the invention]

However, even the conventional circuit configuration having this reset function had the following problems. In other words,
If each flip-flop (FF) is designed with the same threshold value for the reset signal, ideally the reset should be released at the same time, but in reality, due to variations in device manufacturing, etc. The order of canceling the reset is inconsistent. Therefore, even though the states of all FFs have been reset, the time from when the reset release signal is input until the output of the PSC appears is
The phase of the input signal of the phase frequency comparator 2 may be different from the phase of the reference oscillation source.

As a result, there was a possibility that a malfunction would occur immediately after the reset was released.

[Means to solve the problem]

The semiconductor device of the present invention has been made in view of the above-mentioned problems, and includes the FF closest to the input of the FFs constituting the PSC.
That is, the FF is designed so that the reset release of the FF, in which the outputs of other FFs do not change unless the output of the FF changes, is slower than the delay of the reset release signal due to element variations.

Furthermore, specifically, in differential configuration circuits often used in FF circuits, the size of the pair of transistors that handle the reset release signal, for example, the emitter width in the case of a bipolar transistor, and the gate in the case of a field effect transistor. This can be achieved by changing the ratio of width etc. using FF.

Note that there is a method of delaying reset release only for a certain FF by using a delay circuit to delay the reset release signal supplied to that FF, but it is difficult to integrate the delay circuit into an IC, and the reset release signal for that FF is delayed. The present invention, in which the threshold value for the target is changed compared to other methods, is more practical.

[Effect]

The reproducibility of the time from the reset release signal input to the PSC output, that is, the reproducibility of the phase of the input signal of the phase frequency comparator is improved.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to the PSC 6 shown in FIG. 4.

Reference numerals 31 to 33 represent DFFs, and reference numerals 34 to 38 represent TFFs. The threshold values for reset release signals for FFs 32 to 38 other than DFF 31 are set to be the same, and the order in which the reset is released is determined by manufacturing variations of the elements and the state at that moment, but the reset release signal for DFF 31 is Only the threshold for the signal is set higher than others, regardless of element variations and other effects.
It is always the last to be reset. Also, unless the output signal of DFF31 changes, no change will appear in the output of other FFs, and when the reset of DFF31 is finally released, PSC6 starts the frequency dividing operation, and the terminal (OU
A frequency-divided signal is output from T) 45.

Note that the terminal 44 receives the reference clock (CLK) from the VCO4.
) signal is input, and the terminal (MC) 46
is given a control signal from MC7, and the PSC
A frequency division ratio of 6 is controlled.

Further, a reset release signal is applied to the terminal 47, and each F
It is transmitted to F31-38.

In addition, Fig. 3 shows PSC6 as G a A s M E S
A circuit diagram of DFFs 31 to 33 realized using FETs is shown.

The TFFs 34 to 38 are realized by adding paths for feeding back the outputs of the DFFs 31 to 33 to inputs.

Each FF31 to 38 is configured in a master-slave manner,
The slave FF has a reset terminal (R) and a reset release terminal (R). Two FETs indicated by symbols 51 and 52 determine the threshold for the reset release signal, and if FETs with the same threshold voltage vth are used, both FETs
The threshold value is determined by the ET gate width. For example, the threshold value of each FF is determined as follows. Vth-0 [V
], FET51゜5 of DFF31 is used.
The gate width ratio of 2 is set to 1.5:1.0, and the other FF
The ratio of the gate widths of 32 to 38 is set to 1:1. Therefore, the threshold value of the DFF 31 for the reset release signal is higher than the threshold values of the other FFs 32 to 33.

Therefore, the output of the PSC 6 always appears after a certain period of time after the reset of this DFF 31 is released, and does not depend on the order of reset release of the other FFs 32 to 38. In other words, the phase reproducibility is stabilized, and the input phase of the phase frequency comparator 2 can be adjusted to be close to the phase of the reference oscillation source 1, which greatly reduces the time required to pull in the frequency and establish synchronization. Can be shortened.

In the above description, a prescaler with a frequency division ratio of 128/129 has been described, but it goes without saying that the present invention can be applied to prescalers with a fixed frequency division ratio as well as prescalers with other frequency division ratios.

〔Effect of the invention〕

As explained above, according to the present invention, variations in the delay time of the output signal from the reset release signal of the psc output, which are caused by element variations and other influences, are eliminated, and the input phase of the phase frequency comparator is stabilized. According to P.L.
The time required to establish synchronization of the L circuit is shortened. For this reason,
It becomes possible to reduce power consumption by frequently turning on and off the power supply, and it is possible to realize a mobile communication device that can operate for a longer time without charging than before.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the internal configuration of a 280 circuit 6 according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a PLL circuit which is an example of a reference signal generator, and FIG.
This figure is a circuit diagram for explaining the internal structure of DFFs 31 to 33 shown in FIG. 1, and FIG. 4 is a block diagram showing the internal structure of a conventional 280 circuit. 6...Dual modulus conflict prescaler (PSC
) circuit, 31...D-type flip-flop (DFF) with different thresholds for reset release signals, 3
2.33...DFF, 34-38...T-type flip-flop (TFF), 51.52...A pair of FETs with different transistor gate width ratios.

Claims (1)

[Claims] 1. In a prescaler IC composed of a plurality of flip-flops having a reset function, the reset release of one flip-flop is delayed than the reset release of other flip-flops, and this time difference is compensated for by the flip-flop 1. A semiconductor device characterized in that the semiconductor device is realized by setting thresholds for reset release signals of a preset to different values. 2. The flip-flop is realized by a differential configuration circuit,
2. The semiconductor device according to claim 1, wherein the threshold value for the reset signal is set by changing the size ratio of paired transistors for each flip-flop. 3. The semiconductor device according to claim 1 or 2, wherein the prescaler IC is monolithically constructed using a GaAs MESFET.