JPH03101289A - Packaging structure of semiconductor device - Google Patents

Packaging structure of semiconductor device

Info

Publication number
JPH03101289A
JPH03101289A JP23860289A JP23860289A JPH03101289A JP H03101289 A JPH03101289 A JP H03101289A JP 23860289 A JP23860289 A JP 23860289A JP 23860289 A JP23860289 A JP 23860289A JP H03101289 A JPH03101289 A JP H03101289A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor package
substrate
wiring board
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23860289A
Other languages
Japanese (ja)
Inventor
Hidekazu Sato
英一 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23860289A priority Critical patent/JPH03101289A/en
Publication of JPH03101289A publication Critical patent/JPH03101289A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Abstract

PURPOSE:To reduce occurrence of non-conforming articles after mounting to a substrate and to enable functions of the substrate to be maintained normally by exchanging a small number of semiconductor elements even if defective articles may occur by mounting relatively small number of semiconductor packages on a middle substrate for performing various kinds of tests and by mounting only the middle substrates which passed this onto a plurality of substrates. CONSTITUTION:The tip part of a conduction pattern 18 which is provided at each semiconductor package placement position, 19, 19a, 19b, and 19c on a middle substrate 17 and a lead 3 of a semiconductor package D whose functions are tested previously are adjusted and electrical joint is performed by soldering, etc. Functional test is performed again in this state and only the package of the semiconductor package D which is decided to be defective is replaced by a new one. After this, resin sealing is performed to the lead 3 of each semiconductor package D and a joint part of the conduction pattern 18 for protection. Then, the middle substrate 17 which was subjected to resin sealing is mounted to a printed-wiring board 14 and the terminal on the middle substrate 17 and a wiring pattern 15 which is provided on the printed wiring board 14 are connected and current conductor test is performed, thus completing packaging of a number of semiconductor packages D.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は多数の半導体パッケージをプリント配線基板上
に高密度実装する半導体装置の実装構造に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mounting structure for a semiconductor device in which a large number of semiconductor packages are mounted on a printed wiring board at high density.

[従来の技術] 半導体パッケージは、−82にリードフレームに設けた
ダイパッドに半導体素子を取り付け、半導体素子の電極
と、リードフレームの端子とをそれぞれワイヤーで接続
し、半導体素子とワイヤの周囲及び端子の一部を樹脂、
もしくはセラミックでパッケージしたのち、端子部分で
切断し、端子を適宜折り曲げて接続している。このため
パッケージが厚くなり、全体として大型になっている。
[Prior art] A semiconductor package is manufactured by attaching a semiconductor element to a die pad provided on a lead frame at -82, connecting the electrodes of the semiconductor element and terminals of the lead frame with wires, and connecting the semiconductor element and the surroundings of the wires and the terminals. Part of the resin,
Alternatively, after packaging it in ceramic, it is cut at the terminals, and the terminals are bent appropriately to connect. This makes the package thicker and larger overall.

ところで最近は電子機器の小型化、薄型化にともない、
これに使用する半導体パッケージも高密度実装するため
、薄くかつ小型の半導体パッケージの出現が望まれてい
る。
By the way, recently, as electronic devices have become smaller and thinner,
The semiconductor packages used for this purpose are also required to be mounted in high density, so there is a desire for thinner and smaller semiconductor packages.

このような要請に答えるべく、フィルムキャリアのデバ
イスホールに半導体素子を配設して、半導体素子の電極
とフィルムキャリアのリードとを直接接続し、これに液
状の樹脂(例えばエポキシ樹脂)からなる封止材料を印
刷あるいはボッティックシテパッケージした方式の半導
体パッケージが使用されるようになった。
In order to meet these demands, a semiconductor element is placed in the device hole of a film carrier, the electrodes of the semiconductor element are directly connected to the leads of the film carrier, and a seal made of liquid resin (e.g. epoxy resin) is applied. Semiconductor packages that are printed or packaged with adhesive materials have come into use.

第3図はフィルムキャリアを用いた半導体パッケージを
説明するための平面図である。図において、1は長さ方
向に等間隔に、後述の半導体素子6゜6a、  6b、
  ・・・の表面積より大きい面積のデバイスホール2
. 2a、  2b・・・が設けられた厚さ25から1
25μm程度のフィルムキャリア(以下フィルムという
)である。3はフィルム1に設けられた銅の如き導電率
の高い厚さ10〜70μm、幅30〜300μm程度の
金属箔からなる多数のリードで、その一部はデバイスホ
ール2内に突出して自由端となっている。4はフィルム
1を搬送するためのスプロケット穴である。第4図は上
記のようなフィルム1に半導体素子6を取り付ける装置
の一例を示す模式図で、半導体素子搭載台5上に載置さ
れた半導体素子6は、位置決めガイド7により所定の位
置に位置決めされる。一方テープレール8にガイドされ
、スプロケットにより紙面の垂直方向に送られたフィル
ム1は、そのデバイスホール2が半導体素子6上に達し
た位置で停止し、半導体素子6に設けた多数の電極9と
各リード3とをそれぞれ整合させる。ついで加熱された
ボンディングツール10を下降させて各リード3を加圧
し、所定の角度に成形して各リード3と電極9を接合し
接続する。次に、フィルム1を移動して第5図のごとく
それぞれリード3を切断し、またはスキージ印刷、ボッ
ティング等により半導体素子6及びリード3の一部を液
状の対土用樹脂にて封止して硬化させ、樹脂封止部11
を形成した後リード3を切断して、半導体パッケージD
を製造する。
FIG. 3 is a plan view for explaining a semiconductor package using a film carrier. In the figure, 1 denotes semiconductor elements 6° 6a, 6b, which will be described later, arranged at equal intervals in the length direction.
Device hole 2 with an area larger than the surface area of...
.. 2a, 2b... thickness 25 to 1
It is a film carrier (hereinafter referred to as a film) of about 25 μm. 3 is a large number of leads made of a highly conductive metal foil such as copper, with a thickness of 10 to 70 μm and a width of 30 to 300 μm, provided on the film 1, some of which protrude into the device hole 2 and serve as free ends. It has become. 4 is a sprocket hole for conveying the film 1. FIG. 4 is a schematic diagram showing an example of a device for attaching the semiconductor element 6 to the film 1 as described above. be done. On the other hand, the film 1 guided by the tape rail 8 and sent in the direction perpendicular to the plane of the paper by the sprocket stops at the position where the device hole 2 reaches the top of the semiconductor element 6, and the film 1 stops at the position where the device hole 2 reaches the top of the semiconductor element 6. Align each lead 3 with each other. Next, the heated bonding tool 10 is lowered to apply pressure to each lead 3 and form it at a predetermined angle to bond and connect each lead 3 and the electrode 9. Next, the film 1 is moved and the leads 3 are cut as shown in FIG. 5, or the semiconductor element 6 and a part of the leads 3 are sealed with liquid soil-retaining resin by squeegee printing, botting, etc. to harden the resin sealing part 11.
After forming the lead 3, the semiconductor package D is cut.
Manufacture.

上記のようにして製造された半導体パッケージDは、例
えば第5図、第6図に示すように複数個の半導体パッケ
ージDの能動面13をプリント配線基板14偏に向けて
搭載し、リード3をプリント配線基板14の表面に形成
した配線パターン15にそれぞれ接続したのち、スキー
ジ印刷やボッティング等により半導体素子6の周囲及び
リード3を樹脂等で封止して樹脂封止範囲16を形成し
て半導体装置を実装していた。
The semiconductor packages D manufactured as described above are mounted with the active surfaces 13 of a plurality of semiconductor packages D facing toward the printed wiring board 14, for example, as shown in FIGS. 5 and 6, and the leads 3 are mounted. After each connection is made to the wiring pattern 15 formed on the surface of the printed wiring board 14, the periphery of the semiconductor element 6 and the leads 3 are sealed with resin or the like by squeegee printing, botting, etc. to form a resin sealing area 16. Semiconductor devices were mounted.

[発明が解決しようとする課題及び目的]上記のごとき
実装構造によれば、−枚の基板上に多数の半導体素子を
高密度実装できるという特長を有するため、最近では広
〈実施されている。
[Problems and Objects to be Solved by the Invention] The above-mentioned mounting structure has the advantage of being able to mount a large number of semiconductor elements on a single substrate at high density, and has recently been widely implemented.

しかしながら、ボッティングあるいは印刷により半導体
素子を封止した後、半導体装置の良否を試験するために
通電試験や耐熱衝撃試験を行う必要があるが、もし多数
の半導体素子のうち一個でも不良品が発生すると、他の
良品を含めて基板全体を廃棄処分しなければならず、き
わめて不経済であった。
However, after sealing a semiconductor element by botting or printing, it is necessary to conduct a current test and a thermal shock resistance test to test the quality of the semiconductor device, but if even one of the many semiconductor elements is defective. Then, the entire board, including other non-defective products, had to be disposed of, which was extremely uneconomical.

本発明は上記の課題を解決すべくなされたもので基板へ
の実装後に不良品が発生する恐れがなく、もし不良品が
発生しても小数の半導体素子を交換するだけで、基板の
機能を正常に戻すことのできる半導体装置の実装構造を
得ることを目的としたものである。
The present invention was made to solve the above problems, and there is no risk of defective products occurring after mounting on a board. Even if a defective product occurs, the function of the board can be maintained by simply replacing a small number of semiconductor elements. The objective is to obtain a mounting structure for a semiconductor device that can be returned to normal operation.

[課題を解決するための手段] 本発明に係る半導体装置の実装構造は、フィルムキャリ
アに半導体素子を配設し、該半導体素子に設けた多数の
電極に前記フィルムキャリアのリードをそれぞれ接続し
て前記リードを切断し、または前記半導体素子及びリー
ドの一部を樹脂などで封止した後前記リードを切断して
なる半導体パッケージと、耐熱フィルム上に導電パター
ンを有する中間基板上にほぼ等間隔に半導体パッケージ
を配設して、前記半導体パッケージのリードと、中間基
板の導電パターンとを、それぞれ接続してなる複数の中
間基板と、配線パターンが形成されたプリント配線基板
からなり、該プリント配線基板上に前記複数の中間基板
を搭載し、該中間基板の導電パターンを直接または端子
を介して前プリント配線記基板の配線パターンに接続し
たものである。
[Means for Solving the Problems] A mounting structure for a semiconductor device according to the present invention includes a semiconductor element disposed on a film carrier, and leads of the film carrier each connected to a large number of electrodes provided on the semiconductor element. A semiconductor package obtained by cutting the leads or sealing a part of the semiconductor element and the leads with resin or the like and then cutting the leads, and an intermediate substrate having a conductive pattern on a heat-resistant film at approximately equal intervals. A printed wiring board comprising a plurality of intermediate substrates on which semiconductor packages are disposed and connecting leads of the semiconductor packages and conductive patterns of the intermediate substrate, respectively, and a printed wiring board on which a wiring pattern is formed. The plurality of intermediate boards are mounted thereon, and the conductive patterns of the intermediate boards are connected directly or via terminals to the wiring patterns of the previous printed wiring board.

[作用] 耐熱フィルム基板上に一部ボンディングした後、液状の
封止材料で封止された半導体パッケージは、二の段階で
機能試験を行い不良の半導体パッケージが発見され除外
される。しかし、耐熱フィルム基板より半導体パッケー
ジを切断等の手段により個別の半導体パッケージに分離
する段階において、リード切れ、欠は等の機能不良が発
生しても不良として除去することは困難であった。従っ
て複数の半導体パッケージが、中間基板上に実装された
後、不良品が発生することがあった。しかし中間基板に
実装されたのちにもしも不良が発見された場合でもこの
段階で不良半導体パッケージを除外することが出来るた
め、プリント配線基板上に中間基板が実装された後の不
良品の発生する確立はさらに減少する。もしもプリント
配線基板に実装された後に不良が発生した場合には、当
該半導体パッケージが実装された中間基板のみを交換す
ればよい。
[Operation] The semiconductor package, which is partially bonded onto a heat-resistant film substrate and then sealed with a liquid sealing material, is subjected to a functional test in the second step, and defective semiconductor packages are found and removed. However, at the stage of separating the semiconductor packages from the heat-resistant film substrate into individual semiconductor packages by means such as cutting, even if functional defects such as broken leads or chips occur, it is difficult to eliminate them as defects. Therefore, after a plurality of semiconductor packages are mounted on an intermediate substrate, defective products may occur. However, even if a defect is discovered after being mounted on the intermediate board, the defective semiconductor package can be excluded at this stage, so there is a high probability that a defective product will occur after the intermediate board is mounted on the printed wiring board. decreases further. If a defect occurs after the semiconductor package is mounted on a printed wiring board, only the intermediate board on which the semiconductor package is mounted needs to be replaced.

[実施例] 第1図は本発明の実施例における斜視図である。[Example] FIG. 1 is a perspective view of an embodiment of the present invention.

図に於て、17,17a、17b、17cは耐熱フィル
ム上に導電パターン15を有する中間基板であり、中間
基板17上にはほぼ等9間隔に複数の半導体パッケージ
Dを搭載して、半導体パッケージDのリード3と、導電
パターン18はそれぞれ電気的に接続している。14は
プリント配線基板で、表面に配線パターン15を有し、
それぞれの中間基板17の導電パターン18と、プリン
ト配線基板14の配線パターン15は、それぞれ電気的
に接続している。第2図(a)は中間基板17に半導体
パッケージDを実装した実施例の平面図、(b)は模式
的に示したその断面図である。中間基板17は、長さ方
向に等間隔に複数個の半導体パッケージ配置箇所19.
 19 a、  19 b、  19Cが設けられてい
る。半導体パッケージ配置箇所19.19&、19b、
19c毎に、中間基板17上に設けられた導電率の高い
材料からなる導電パターン18の先端部が、半導体パッ
ケージDのリード3と対向して配置されている。それぞ
れの導電パターン18と、半導体パッケージDのり−ド
3は電気的に接続されている。次に上記のごとく構成し
た本実施例を説明する。 先ず中間基板、7上の各半導
体パッケージ配置箇所19,19a、19b、19cに
設けられた導電パターン18の先端部と、あらかじめ通
電試験等の機能試験を行った半導体パッケージDのリー
ド3を整合させ、半田付け、導電接着剤、異方性導電樹
脂等により電気的接合を行う。この状態で再び機能試験
を行う、中間基板17上の機能試験で不良と判定された
半導体パッケージDはその半導体パッケージDのみを交
換すればよい。この後者半導体パッケージDのリード3
と、導電パターン18の接合部をエポキシ樹脂等の封止
樹脂にて樹脂封止を行い接合部の保護を行う。中間基板
17上の機能試験に合格し樹脂封止を行った中間基板1
7をプリント配線基板14上に搭載し、中間基板17上
の導電パターン18の端子と、プリント配線基板14に
設けた配線パターン15とをそれぞれ接続する。その後
中間基板17の各端子とプリント配線基板14の配線パ
ターン15との通電試験を行えばプリント配線基板15
に対する多数の半導体パッケージDの実装は完了する。
In the figure, reference numerals 17, 17a, 17b, and 17c are intermediate substrates having a conductive pattern 15 on a heat-resistant film, and a plurality of semiconductor packages D are mounted on the intermediate substrate 17 at approximately equal intervals of 9 to form a semiconductor package. The leads 3 of D and the conductive pattern 18 are electrically connected to each other. 14 is a printed wiring board having a wiring pattern 15 on its surface;
The conductive pattern 18 of each intermediate board 17 and the wiring pattern 15 of the printed wiring board 14 are electrically connected to each other. FIG. 2(a) is a plan view of an embodiment in which the semiconductor package D is mounted on the intermediate substrate 17, and FIG. 2(b) is a schematic cross-sectional view thereof. The intermediate substrate 17 has a plurality of semiconductor package placement locations 19. arranged at equal intervals in the length direction.
19a, 19b, and 19C are provided. Semiconductor package placement location 19.19&, 19b,
For each 19c, the tip of a conductive pattern 18 made of a material with high conductivity and provided on the intermediate substrate 17 is arranged to face the lead 3 of the semiconductor package D. Each conductive pattern 18 and the semiconductor package D glue 3 are electrically connected. Next, the present embodiment configured as described above will be explained. First, the tips of the conductive patterns 18 provided at the respective semiconductor package placement locations 19, 19a, 19b, and 19c on the intermediate substrate 7 are aligned with the leads 3 of the semiconductor package D, which has been previously subjected to a functional test such as an energization test. , electrical connection is performed by soldering, conductive adhesive, anisotropic conductive resin, etc. In this state, the function test is performed again, and if the semiconductor package D is determined to be defective in the function test on the intermediate board 17, only that semiconductor package D needs to be replaced. Lead 3 of this latter semiconductor package D
Then, the joint portion of the conductive pattern 18 is sealed with a sealing resin such as epoxy resin to protect the joint portion. Intermediate board 1 that passed the functional test on intermediate board 17 and was sealed with resin
7 is mounted on the printed wiring board 14, and the terminals of the conductive pattern 18 on the intermediate board 17 and the wiring pattern 15 provided on the printed wiring board 14 are respectively connected. After that, if a conduction test is performed between each terminal of the intermediate board 17 and the wiring pattern 15 of the printed wiring board 14, the printed wiring board 15
The mounting of a large number of semiconductor packages D on the is completed.

もし多数の半導体パッケージDのうちに不良品が発生し
た場合にはその半導体パッケージDの実装されている中
間基板17のみを交換すればよい。
If a defective product occurs among a large number of semiconductor packages D, only the intermediate substrate 17 on which the semiconductor package D is mounted needs to be replaced.

[発明の効果] 以上述べたごとく本発明によれば比較的小数の半導体パ
ッケージを中間基板上に実装して各種の試験を行った後
これに合格した中間基板のみを複数個基板上に実装する
ようにしたため基板に装着後年良品の発生することはほ
とんどない。またもし不良品の発生したときは、当該半
導体パッケージの実装された中間基板のみを交換すれば
よい。
[Effects of the Invention] As described above, according to the present invention, a relatively small number of semiconductor packages are mounted on an intermediate substrate, various tests are conducted, and only those intermediate substrates that have passed the tests are mounted on a plurality of substrates. As a result, there are almost no defective products after being mounted on a board. Furthermore, if a defective product occurs, only the intermediate board on which the semiconductor package is mounted needs to be replaced.

したがって、信頼性を大幅に向上させるばかりでなく、
経済的にもきわめて有利であり、製造コストを低減する
ことが出来る。
Therefore, it not only significantly improves reliability, but also
It is extremely advantageous economically and can reduce manufacturing costs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す斜視図。 第2図(a
)は本発明の中間基板上に半導体パッケージを実装した
一実施例の平面図。第2図(b)は本発明の中間基板上
に半導体パッケージを実装した本発明の一実施例を模式
逍に示す断面図。第3の半導体装置の実装例を示す説明
図である。 1:フイルム、2ニデバイスホール、3 :リード、4
:スプロケット穴、5:半導体素子塔載台、6: 半導
体素子、7:位置決めガイド、8: テープレール、9
:電極、 10: ボンディングツール、11:樹脂封
止部、13:能動面、14ニブリント配線基板、15:
配線パターン、16:樹脂封止範囲、17:中間基板、
18:導電パターン、19:パッケージ配置箇所、D=
半導体パッケージ。 以上
FIG. 1 is a perspective view showing one embodiment of the present invention. Figure 2 (a
) is a plan view of one embodiment of the present invention in which a semiconductor package is mounted on an intermediate substrate. FIG. 2(b) is a sectional view schematically showing an embodiment of the present invention in which a semiconductor package is mounted on an intermediate substrate of the present invention. FIG. 7 is an explanatory diagram showing a mounting example of a third semiconductor device. 1: Film, 2 device holes, 3: Lead, 4
: Sprocket hole, 5: Semiconductor element mounting stand, 6: Semiconductor element, 7: Positioning guide, 8: Tape rail, 9
: Electrode, 10: Bonding tool, 11: Resin sealing part, 13: Active surface, 14 Niblint wiring board, 15:
Wiring pattern, 16: Resin sealing range, 17: Intermediate board,
18: Conductive pattern, 19: Package placement location, D=
semiconductor package. that's all

Claims (1)

【特許請求の範囲】[Claims]  フイルムキャリアに半導体素子を配設し、該半導体素
子に設けた多数の電極と前記フイルムキャリアのリード
をそれぞれ接続して前記リードを切断し、または前記半
導体素子及びリードの一部を樹脂などで封止したのち前
記リードを切断してなる半導体パッケージを、耐熱フイ
ルム上に導電パターンを有する中間基板上にほぼ等間隔
に配設して、前記半導体パッケージのリードと、中間基
板の導電パターンとを、それぞれ接続してなる複数の中
間基板と、配線パターンが形成されたプリント配線基板
からなり、該プリント配線基板上に、前記複数の中間基
板を搭載し、該中間基板の導電パターンを直接または端
子を介して前記プリント配線基板の配線パターンに接続
したことからなる半導体装置の実装構造。
A semiconductor element is disposed on a film carrier, a number of electrodes provided on the semiconductor element are connected to leads of the film carrier, and the leads are cut, or a part of the semiconductor element and the leads are sealed with resin or the like. After stopping, a semiconductor package obtained by cutting the leads is arranged at approximately equal intervals on an intermediate substrate having a conductive pattern on a heat-resistant film, and the leads of the semiconductor package and the conductive pattern of the intermediate substrate are connected. It consists of a plurality of intermediate boards connected to each other and a printed wiring board on which a wiring pattern is formed, and the plurality of intermediate boards are mounted on the printed wiring board, and the conductive pattern of the intermediate board is connected directly or with a terminal. A mounting structure for a semiconductor device, which is connected to a wiring pattern of the printed wiring board through a semiconductor device.
JP23860289A 1989-09-14 1989-09-14 Packaging structure of semiconductor device Pending JPH03101289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23860289A JPH03101289A (en) 1989-09-14 1989-09-14 Packaging structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23860289A JPH03101289A (en) 1989-09-14 1989-09-14 Packaging structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03101289A true JPH03101289A (en) 1991-04-26

Family

ID=17032627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23860289A Pending JPH03101289A (en) 1989-09-14 1989-09-14 Packaging structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03101289A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7634849B2 (en) 2001-09-12 2009-12-22 Formfactor, Inc. Method of assembling and testing an electronics module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7634849B2 (en) 2001-09-12 2009-12-22 Formfactor, Inc. Method of assembling and testing an electronics module

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