JPH03100945U - - Google Patents

Info

Publication number
JPH03100945U
JPH03100945U JP765890U JP765890U JPH03100945U JP H03100945 U JPH03100945 U JP H03100945U JP 765890 U JP765890 U JP 765890U JP 765890 U JP765890 U JP 765890U JP H03100945 U JPH03100945 U JP H03100945U
Authority
JP
Japan
Prior art keywords
averaging
display device
signals
address detection
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP765890U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP765890U priority Critical patent/JPH03100945U/ja
Publication of JPH03100945U publication Critical patent/JPH03100945U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、考案の一実施例に係るCPU負荷表
示装置のブロツク図、第2図はCPU負荷測定の
原理図、第3図はCPU負荷装置の構成ブロツク
図である。第4図は、信号を示す。 2……実行番地検出装置、4……平均化装置、
6……表示装置、7……領域設定器。
FIG. 1 is a block diagram of a CPU load display device according to an embodiment of the invention, FIG. 2 is a principle diagram of CPU load measurement, and FIG. 3 is a block diagram of the configuration of the CPU load device. FIG. 4 shows the signals. 2...Execution address detection device, 4...Averaging device,
6...display device, 7...area setter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] コンピユータシステムにおいて、CPU(中央
処理装置)が実行する命令の番地が、予め定めら
れた領域内にあるか否かを検出する実行番地検出
装置と、前記実行番地検出装置が検出した信号を
平均化する平均化装置と、前記平均化装置の信号
を表示する表示装置とを具備することを特徴とす
るCPU負荷表示装置。
In a computer system, an execution address detection device detects whether the address of an instruction executed by a CPU (central processing unit) is within a predetermined area, and averages signals detected by the execution address detection device. 1. A CPU load display device comprising: an averaging device that displays signals from the averaging device; and a display device that displays signals from the averaging device.
JP765890U 1990-01-30 1990-01-30 Pending JPH03100945U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP765890U JPH03100945U (en) 1990-01-30 1990-01-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP765890U JPH03100945U (en) 1990-01-30 1990-01-30

Publications (1)

Publication Number Publication Date
JPH03100945U true JPH03100945U (en) 1991-10-22

Family

ID=31511313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP765890U Pending JPH03100945U (en) 1990-01-30 1990-01-30

Country Status (1)

Country Link
JP (1) JPH03100945U (en)

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