JPH0299440U

JPH0299440U -

Info

Publication number: JPH0299440U
Application number: JP809089U
Authority: JP
Priority date: 1989-01-26
Filing date: 1989-01-26
Publication date: 1990-08-08

Description

[Brief explanation of the drawing]

第１図は本考案に係るサンプルホールド回路の
実施例を示す図、第２図は第１図回路の上半分の
等価回路を示す図、第３図は従来のサンプルホー
ルド回路を示す図、第４図は第３図回路の上半分
の等価回路を示す図、第５図は入力信号の波形例
を示す図である。Ｃ１，Ｃ２……ホールド用コンデンサ、Ｄ１，
Ｄ２……ダイオード、ＳＷ１〜ＳＷ４……スイツ
チ、Ａ１，Ａ２……バツフアアンプ、Ｒ１，Ｒ２
，ｒ１，ｒ２……抵抗。 FIG. 1 is a diagram showing an embodiment of the sample and hold circuit according to the present invention, FIG. 2 is a diagram showing an equivalent circuit of the upper half of the circuit in FIG. 1, and FIG. 3 is a diagram showing a conventional sample and hold circuit. 4 is a diagram showing an equivalent circuit of the upper half of the circuit of FIG. 3, and FIG. 5 is a diagram showing an example of the waveform of an input signal. C1, C2...Hold capacitor, D1,
D2...Diode, SW1-SW4...Switch, A1, A2...Buffer amplifier, R1, R2
, r1, r2...resistance.

Claims

[Claims for Utility Model Registration] A hold capacitor that introduces an input signal through a rectifier D1, a buffer amplifier that introduces the voltage of this hold capacitor and outputs a voltage having the same value as the introduced voltage; A semiconductor switch SW3 whose one end is connected to the hold capacitor through the resistor R2 and whose other end is connected to a certain potential, and a connection point between the first resistor R2 and the semiconductor switch SW3 and the output terminal of the buffer amplifier. A second resistor provided in between has a value RF1 such that RF1≪
A sample-and-hold circuit with a feedback resistor R2;