JPH0298644U - - Google Patents
Info
- Publication number
- JPH0298644U JPH0298644U JP733689U JP733689U JPH0298644U JP H0298644 U JPH0298644 U JP H0298644U JP 733689 U JP733689 U JP 733689U JP 733689 U JP733689 U JP 733689U JP H0298644 U JPH0298644 U JP H0298644U
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- center
- semiconductor package
- forming
- periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Die Bonding (AREA)
Description
第１図Ａ，Ｂは本考案に係る半導体パツケージ
の第１の実施例を示す断面図と平面図、第２図Ａ
，Ｂは本考案による第２の実施例を示す断面図と
平面図、第３図Ａ，Ｂは従来例の断面図と平面図
である。
１，１１……キヤビテイ、１ａ……第２のキヤ
ビテイ、２，１２……ステツチ、３，１３……外
部導出ピン、４，１４……半導体パツケージ、５
，１５……半導体チツプ、６，１６……ボンデイ
ングワイヤ。
FIGS. 1A and 1B are a sectional view and a plan view showing a first embodiment of a semiconductor package according to the present invention, and FIG.
, B are a sectional view and a plan view showing a second embodiment of the present invention, and FIGS. 3A and 3B are a sectional view and a plan view of a conventional example. 1, 11... Cavity, 1a... Second cavity, 2, 12... Stitch, 3, 13... External lead-out pin, 4, 14... Semiconductor package, 5
, 15... semiconductor chip, 6, 16... bonding wire.
Claims (1)
タ部を周辺部より一段低い階段状に形成するか或
いはキヤビテイの４辺をセンタに向かつて傾斜さ
せて形成することにより、キヤビテイ面の周辺と
センタで高さが違うことを特徴とする半導体パツ
ケージ。 In a semiconductor package, the height of the cavity surface is different between the periphery and the center by forming the center part of the cavity into a step-like shape that is one step lower than the peripheral part, or by forming the cavity with the four sides inclined toward the center. A semiconductor package featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP733689U JPH0298644U (en) | 1989-01-24 | 1989-01-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP733689U JPH0298644U (en) | 1989-01-24 | 1989-01-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0298644U true JPH0298644U (en) | 1990-08-06 |
Family
ID=31212264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP733689U Pending JPH0298644U (en) | 1989-01-24 | 1989-01-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0298644U (en) |
-
1989
- 1989-01-24 JP JP733689U patent/JPH0298644U/ja active Pending