JPH0298217A - A/d conversion circuit and comparator using the same circuit - Google Patents

Abstract

PURPOSE:To suppress the variance in the characteristic of a product such as a comparator using an A/D conversion circuit by converting a counted value of a counter latching a value being converted an analog signal into a digital value, into a pulse pattern signal with a corresponding pulse width, integrating the signal and using the result as a comparison reference voltage of the analog comparator circuit. CONSTITUTION:A comparator 1 consists of an A/D converting circuit section 2 and a comparison section 3. The A/D converting circuit section 2 consists of an analog comparator circuit 4, a counter 5 counting a clock signal in response to the result of comparison of the analog voltage comparison circuit and a pulse signal generating circuit 7 generating a pulse pattern signal of a prescribed level in which the overall pulse width corresponds to the count of the counter. Then an input signal is given to the analog voltage comparator circuit 4 and a voltage signal integrating the pulse pattern signal is given to the other input. Thus. the dispersion in the characteristic of the A/D conversion circuit or a products such as a comparator using the A/D conversion circuit is suppressed.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to an A/D conversion circuit and a comparator using this circuit, and more specifically, to suppressing variations in the voltage that is the comparison standard of the analog comparison circuit. The present invention relates to a circuit that can realize an A/D conversion circuit or a comparator with uniform characteristics.

[Prior Art] A conventional A/D conversion circuit or a comparator using an A/D conversion circuit has an analog comparison circuit section, which is usually composed of an operational amplifier, and whose comparison reference voltage is connected to a power source. A configuration in which the voltage, etc. is divided by resistance is often adopted.

[Problem to be Solved] Such an analog comparison circuit section has a drawback that in addition to the offset caused by the operational amplifier, the detection level varies due to variations in the resistor voltage divider circuit, and the A/D conversion value varies.

As a result, when mass-produced, conversion errors due to this variation become large, resulting in poor product yield.

The present invention solves the problems of the prior art, and provides an A/D conversion circuit or a comparator using this A/D conversion circuit that can manufacture products with little variation. With the goal.

[Means for Solving the Problems] The A/D conversion circuit of the present invention to achieve such an object includes an analog voltage comparison circuit and a clock signal counted according to the comparison result of the analog voltage comparison circuit. It is equipped with a counter and a pulse signal generation circuit that generates a constant level pulse pattern signal whose total pulse width is the period corresponding to the count value of this counter, and an analog voltage comparison circuit is input to one side. It receives a signal, and the other input receives a voltage signal obtained by integrating the pulse pattern signal.

The comparator of the present invention also includes an analog voltage comparison circuit, a counter that counts clock signals according to the comparison result of the analog voltage comparison circuit, and a constant pulse width whose total pulse width is a period corresponding to the count value of the counter. A pulse signal generation circuit that generates a level pulse ts'1 turn signal, a base value generation circuit that generates a digital reference value, and a comparison between the reference value of this reference value generation circuit and the digital value of the counter. The counter is an up/down counter that counts up or down depending on the comparison result of the analog voltage comparison circuit, and the analog voltage comparison circuit receives an input signal on one side and receives an input signal on the other side. A voltage signal obtained by integrating the /f pulse pattern signal is received, and when the count value of the counter reaches or exceeds a reference value, a detection signal thereof is obtained from the digital comparison circuit.

[Operation] In this way, the count value of the counter that holds the value obtained by converting the analog signal into a digital value is converted into a pulse pattern signal with the corresponding pulse width, which is integrated and used as the comparison standard on the analog comparison circuit side. By using a voltage, the reference voltage on the analog comparator circuit side does not need to be generated in the form of resistor voltage division.

As a result, there is no variation in the comparison reference voltage of the A/D conversion circuit, so that the A/D conversion circuit or this A/D conversion circuit
Variations in characteristics of products such as comparators using the /D conversion circuit can be suppressed.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the comparator to which the comparator of the present invention is applied, and FIG. 2 is an explanatory diagram of the operation of converting the count value of the counter into the pulse width of the corresponding period. .

In FIG. 1, ``■'' is a comparator, which is composed of an A/D conversion circuit section 2 and a comparison section 3. In FIG. The A/D conversion circuit section 2 includes an analog comparator circuit 4 composed of an operational amplifier, and an up/down counter 5 that receives the output of the analog comparator circuit 4 and counts a clock signal CLK.
, the value of this up/down counter 5 and the pulse generation circuit 6
, and the total pulse width is the period “O” corresponding to the value of the up/down counter 5.
A pulse pattern signal generation circuit 7 that generates a pattern of pulses (no.
and an integrating circuit 8 which integrates the voltage value and adds the integrated voltage value to the (-) phase side input of the analog comparator circuit 4. Note that the capacitor Ci is connected to the input signal IN
This is an input capacitor that cuts the direct wave component of and adds it to the (+) phase side input of the analog comparator circuit 4.

The comparator 3 includes a digital comparator circuit 10 that receives the output of the up-down counter 5 for each digit, and a ROM II that provides a reference digital value for comparison of the digital comparator circuit 10.

Next, to explain its operation, first, the analog input signal input to the (+) phase side of the analog comparator circuit 4 is compared with the output of the integrating circuit 8 input to the (-) phase side, and the input signal is When the voltage of Each time it is received, it is counted up and the count value is increased. Conversely, when the voltage of the input signal is lower than the voltage of the output signal of the integrating circuit 8, the output of the analog comparator circuit 4 becomes a LOW level (hereinafter referred to as "L"), and the The down counter 5 counts down each time it receives the clock signal CLK and decreases the count value. The current count value of the up/down counter 5 is sent to the pulse pattern signal generation circuit 7.

On the other hand, the pulse pattern signal generation circuit 7 has a
The pulse signal shown in a) is supplied from the pulse generating circuit e corresponding to each digit. That is, as shown in Figure 2 (a), starting from the most significant bit, the period is: Lmost-L digit: T, second digit: 2T, third digit: 4T.
, 4th digit 28T, ... nth digit: 2TI-1
becomes.

Then, the second pulse is generated as a pulse that fills every other "L" section of the most significant digit, and is the 311th pulse.
The pulse of the second digit is generated as a pulse that combines the pulses of the most significant digit and the second digit and fills every other interval where these become "L", and the subsequent digits are generated in the same manner. digit pulses are generated.

The output signals of these respective digit positions are sent to the pulse pattern signal generation circuit 7 corresponding to each digit position of the up/down counter 5, and at the same time, the pulse pattern signal generation circuit 7 receives signals from each digit of the up/down counter 5. “1” corresponds to the digit.
In response to signals representing count values of `` and 0'', corresponding digits of the up/down counter 5 and the pulse generating circuit 6 are combined here.

This synthesis picks up only the pulses of a certain digit of "1" in the up/down counter 5 and generates them as a continuous pulse pattern signal, which is then sent to the integrating circuit 8.
added to. For example, as shown in FIG. 2(b), the value of the up/down counter 5 is "1101...
”, the most significant digit is “1”, so the pulse signal of the most significant digit is selected, and for the digits below that, the pulse signal with “1” in the lower digit is selected. It is added to compensate for the absence of pulses in (C
) is generated and applied to the integrating circuit 8.

As a result, the integrating circuit 8 is supplied with a continuous pulse signal having a total pulse width that is "H" for a period corresponding to the count value of the up/down counter 5, and the pulse signal is "H".
'' is obtained at the capacitor C, and is input to the (-) phase side of the analog comparator circuit 4.

Therefore, the voltage of the input signal IN is compared with this voltage on the reference side by the analog comparator circuit 4, and the value of the up/down counter 5 is increased or decreased according to the results of these comparisons. This increase/decrease value is compared with the value of ROMII of the comparator 3 by the digital comparator circuit 10, and if they are equal or exceed this, the digital comparator circuit 10 detects this and inverts its output signal. to generate the detection signal.

In the above embodiment, when the frequency of the clock signal CLK applied to the up/down counter 5 is sufficiently large compared to the frequency of the input signal, in other words, when the number of samples per cycle of the input signal is sufficiently large, A /
The D conversion error is only the offset of the operational amplifier constituting the analog comparison circuit 4 and the error of the least significant bit of the pulse pattern signal generation circuit 7.

Therefore, the variations in the comparators are also similar.

In addition, in this example, the output of ROMI 1 is used as the comparison standard for digital values, so by changing this,
It is possible to have multiple comparison levels. That is,
In this embodiment, ROMI 1 has different comparison level values stored at respective addresses and accessed by separate control circuits. Therefore, a reference value depending on the situation can be supplied to the digital comparison circuit 10, and a corresponding detection signal can be obtained from the comparator 1. As a result, it becomes easy to provide the comparator with hysteresis characteristics.

Note that the up-down counter 5 can also be simply calculated by taking the AND of the values at each necessary digit position of the up-down counter 5.
It is possible to detect that the value of
II is no longer necessary.

The above explanation focuses on the comparator, but when this circuit is used as an A/D conversion circuit, the up/down counter 5 is used as an up counter or a down counter, and the output of the comparison detection value of the analog comparison circuit 4 is transferred to the integration circuit. If the counter continues to count the clock signal until the output is equal to or exceeds the reference value of 8, and stops counting when the output is equal to or exceeds the reference value, the count value at this time can be set to A of the human input signal. /D conversion value. That is, this circuit can be used as a normal A/D conversion circuit.

As described above, the pulse generation period T of the most significant digit of the pulse generation circuit in the embodiment is determined by the frequency of the clock signal of the pulse generation circuit, and can be selected as appropriate. In particular, if this frequency is set high, the capacitance of the capacitor of the integrating circuit can be reduced, and a circuit suitable for integration can be realized.

Note that the period of the clock signal counted by the up/down counter is preferably set to be sufficiently larger than the frequency of the input signal.

Furthermore, in the embodiment, a pulse generation circuit that generates a pulse signal corresponding to each digit position of the counter is used to obtain a pulse pattern with a width corresponding to the count value of the up/down counter. , a continuous pulse pattern with a constant level such as "H"("L" in negative logic) for a certain period of time, and the pulse width is not limited to that of the embodiment. In short, it is sufficient if the total pulse width is at a constant level during the period corresponding to the count value of this counter.

[Effects of the Invention] As can be understood from the above explanation, in the present invention, the count value of a counter that holds a value obtained by converting an analog signal into a digital value is converted into a pulse pattern signal with a pulse width corresponding to the count value. , and by integrating it and using it as a comparison reference voltage on the analog comparison circuit side, it is not necessary to generate the reference voltage on the analog comparison circuit side in the form of resistive voltage division.

As a result, there is no variation in the comparison reference voltage of the A/D conversion circuit, so this A/D conversion circuit characteristic
Variations in characteristics of products such as comparators using the /D conversion circuit can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an m-embodiment comparator to which the comparator of the present invention is applied, and FIG. 2 is an explanatory diagram of the operation of converting the count value of the counter into the pulse width of the corresponding period. 1... Comparator, 2... A/D conversion circuit section, 3
... Comparison section, 4... Analog comparison circuit, 5... Up/down counter, 6... Pulse generation circuit, 7... Pulse pattern signal generation circuit, 8... Integrating circuit, lO... -Digital comparison circuit, 11...ROM.

Claims (2)

[Claims] (1) An analog voltage comparison circuit, a counter that counts clock signals according to the comparison result of this analog voltage comparison circuit, and a pulse pattern signal of a constant level whose total pulse width corresponds to the count value of this counter. and a pulse signal generation circuit that generates a pulse pattern signal, wherein the analog voltage comparison circuit receives an input signal on one side and receives a voltage signal obtained by integrating the pulse pattern signal on the other side. (2) An analog voltage comparison circuit, a counter that counts clock signals according to the comparison result of this analog voltage comparison circuit, and a pulse pattern signal of a constant level whose total pulse width corresponds to the count value of this counter. a pulse signal generation circuit that generates a reference value of a digital value; a reference value generation circuit that generates a reference value of a digital value; and a digital comparison circuit that compares the reference value of the reference value generation circuit with the value of the counter; An up/down counter that counts up or down depending on the comparison result of the analog voltage comparison circuit, and the analog voltage comparison circuit receives an input signal on one side and receives a voltage signal obtained by integrating the pulse pattern signal on the other side. The comparator is characterized in that it obtains a detection signal from the digital comparison circuit when the count value of the counter reaches or exceeds the reference value.