JPH0298195A - Manufacture of multilayer printed board - Google Patents
Manufacture of multilayer printed boardInfo
- Publication number
- JPH0298195A JPH0298195A JP25022588A JP25022588A JPH0298195A JP H0298195 A JPH0298195 A JP H0298195A JP 25022588 A JP25022588 A JP 25022588A JP 25022588 A JP25022588 A JP 25022588A JP H0298195 A JPH0298195 A JP H0298195A
- Authority
- JP
- Japan
- Prior art keywords
- pin
- shape memory
- multilayer printed
- memory alloy
- printed board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000011162 core material Substances 0.000 claims abstract description 25
- 229910001285 shape-memory alloy Inorganic materials 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000000465 moulding Methods 0.000 abstract description 8
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は多層プリント基板の成形に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to the molding of multilayer printed circuit boards.
従来は、多層プリント基板を成形する際、第2図(a)
に示す様に、銅は〈2.プリプレグ(接着シート)3.
コア材4を重ね合せ、コア材4の位置決め穴に菟銅、ア
ルミ等の材質による位置合わせ用のピンを11通し、内
層コア材を固定していた。Conventionally, when molding a multilayer printed circuit board, the process shown in Fig. 2(a)
As shown in 2. Prepreg (adhesive sheet) 3.
The core materials 4 were stacked one on top of the other, and 11 positioning pins made of materials such as copper or aluminum were passed through the positioning holes of the core materials 4 to fix the inner layer core materials.
しかし、従来の位置合わせ用ピンでは、第2図(b)に
示すように、プレス成形時プリプレグの樹脂流出により
板厚が薄くなると、ピンが挫屈し、コア材間の位置粒度
が悪くなる問題があった。However, with conventional positioning pins, as shown in Figure 2 (b), when the plate thickness becomes thinner due to resin leakage from the prepreg during press molding, the pins buckle and the positional grain size between the core materials deteriorates. was there.
この発明は、上記のような問題を解決するためになされ
たもので、プレス成形時にコア間の位置ズレの無い、高
粒度の多層プリント基板を得ることのできる多層プリン
ト基板の製造方法を提供することを目的とするものであ
る。This invention was made to solve the above-mentioned problems, and provides a method for manufacturing a multilayer printed circuit board that can produce a multilayer printed circuit board with high grain size and no misalignment between cores during press molding. The purpose is to
この発明は、上記目的を達成するため、形状記憶合金製
の位置合わせピンを用い内層コア材を所定位置に固定す
るもので、位置合わせピンは、形状記憶温度以上で先端
が変形し、コア材を所定の厚さとするよう折れ曲がるよ
うに形状記憶されている。In order to achieve the above object, the present invention fixes the inner layer core material in a predetermined position using a positioning pin made of a shape memory alloy. The shape is memorized so that it can be bent to a predetermined thickness.
詳しくは、多層プリント基板の製造方法においてつざの
工程を備えるようにする。Specifically, the method for manufacturing a multilayer printed circuit board includes a final step.
即ち、プリプレグを挟んで重ねられる複数枚のコア材の
位置決め穴に、一方または両方の端部を少くとも2つ以
上に分割し所定温度以上でこの分割部より先端が広がる
特性を付与した形状記憶合金製ピンを貫通して該複数枚
のコア材の位置決めをする工程と、該工程を経たものを
上記所定温度以上で加熱し、加圧する工程とを備えるよ
うにする。In other words, shape memory is created by dividing one or both ends into at least two or more parts in the positioning holes of multiple core materials stacked with prepreg in between, and giving the property that the tip expands from the divided part at a predetermined temperature or higher. The method includes a step of positioning the plurality of core materials by penetrating the alloy pin, and a step of heating the core material that has passed through the step above the predetermined temperature and pressurizing it.
上記構成によれば、加熱加圧時に形状記憶合金製ピンが
変形し、内層コア材を所定の厚さに保持するとともに、
所定の17さとなった内層コア材間に位置する形状記憶
合金製ピンはその間で短縮される、即ち理屈しようとす
る力が働かないため形状記憶ピン合金製は変形せず、し
たがって内層コア材間の位置ずれが防止される。According to the above configuration, the shape memory alloy pin is deformed when heated and pressurized to maintain the inner layer core material at a predetermined thickness, and
The shape memory alloy pin located between the inner layer core materials that has reached the predetermined 17 is shortened between them, that is, the shape memory alloy pin is not deformed because no force is applied to it, and therefore the shape memory alloy pin located between the inner layer core materials is shortened. positional shift is prevented.
以下この発明を実施例で説明する。 This invention will be explained below with reference to Examples.
第1図(a)〜(d)は、この発明の一実施例である「
多層プリント基板の製造方法Jの工程の説明図で、(a
)、(b)は、プレス成形前を、(c)、(d)はプレ
ス成形後を示す。FIGS. 1(a) to 1(d) show an embodiment of the present invention.
An explanatory diagram of the process of manufacturing method J of a multilayer printed circuit board, (a
) and (b) show before press molding, and (c) and (d) show after press molding.
第1図(a)、(b)において、1は形状記憶合金製ピ
ンで、一端にはつば1aが設けられ、他端には2つに分
割された分割部1bが設けられ、所定温度以上でこの分
割部1bより先端が広がる特性が付与されている。また
、2は銅はく、3はプリプレグ、4はコア材で、所定の
順序に積層され、コア材の位置決め穴に前記形状記憶合
金製ピンが貫通されている。In FIGS. 1(a) and (b), 1 is a shape memory alloy pin, one end of which is provided with a collar 1a, and the other end of which is provided with a divided portion 1b that is divided into two. A characteristic is given that the tip becomes wider than this divided portion 1b. Further, 2 is a copper foil, 3 is a prepreg, and 4 is a core material, which are laminated in a predetermined order, and the shape memory alloy pin is passed through the positioning hole of the core material.
この状態で加熱、加圧すると、第1図(C)。When heated and pressurized in this state, the image shown in Fig. 1 (C) is obtained.
(d)に示すように、ピン1の分割部1bは所定の形状
記憶温度以上となって変形し、分割部1bより先端が広
がり、この広かった部分とつばIaとの間の間隔が所定
の値となりピンの全長が縮まるので、理屈等が発生せず
、コア材間の位置ずわが発生しない。As shown in (d), the divided portion 1b of the pin 1 is deformed when the temperature exceeds a predetermined shape memory temperature, and the tip becomes wider than the divided portion 1b, and the distance between this wide portion and the collar Ia becomes a predetermined distance. Since the total length of the pin is reduced, no logic problems occur, and no positional distortion occurs between the core materials.
なお、複数枚のコア材の位置決めは、コア材、プリプレ
グが重ね合わされた状態で、ピンを貫通するか、ピンに
コア材、プリプレグを順次刺し積み重ねるかのいづれに
よって行ってもよく、また、分割部をピンの一端だけで
なく両端に設けるようにしてもよい。The positioning of multiple pieces of core material may be done either by penetrating the pins with the core materials and prepregs stacked one on top of the other, or by sequentially pricking the core materials and prepregs through the pins and stacking them. The portion may be provided not only at one end of the pin but also at both ends.
(発明の効果〕
以上説明したように、この発明によれば、プレス成形の
際、プリプレグの樹脂流れによりその板厚が減っても、
位置合わせ用ピンは変形し、締め付は間隔が減り全長が
縮まるので、理屈せず、各層が正しい位置に配置された
まま成形されるので、コア材間の位置ずれのない高錆度
の多層プリント基板を得ることができる。(Effects of the Invention) As explained above, according to the present invention, even if the thickness of the prepreg is reduced due to resin flow during press molding,
The positioning pins are deformed and the tightening distance is reduced and the total length is shortened, so each layer is molded in the correct position without any logic, so it is possible to create a multi-layer structure with high rust resistance without misalignment between the core materials. Printed circuit boards can be obtained.
第1図(a)〜(d)はこの発明の一実施例の工程を説
明する図、第2図(a)、(b)は従来例の工程を説明
する図である。
図中、1は形状記憶合金製ピン、1aはつば、ibは分
割部、3はプリプレグ、4はコア材である。
なお、図中同一符号は同
又は相当部分を示
す。FIGS. 1(a) to 1(d) are diagrams explaining the steps of an embodiment of the present invention, and FIGS. 2(a) and (b) are diagrams explaining the steps of a conventional example. In the figure, 1 is a shape memory alloy pin, 1a is a collar, ib is a divided portion, 3 is a prepreg, and 4 is a core material. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
決め穴に、一方または両方の端部を少くとも2つ以上に
分割し所定温度以上でこの分割部より先端が広がる特性
を付与した形状記憶合金製ピンを貫通して該複数枚のコ
ア材の位置決めをする工程と、該工程を経たものを上記
所定温度以上で加熱し、加圧する工程とを備えたことを
特徴とする多層プリント基板の製造方法。Made of a shape memory alloy that divides one or both ends into at least two or more parts in the positioning holes of multiple core materials stacked with prepreg sandwiched in between, giving the tip the property of expanding from this divided part at a certain temperature or higher. A method for manufacturing a multilayer printed circuit board, comprising the steps of: positioning the plurality of core materials by penetrating the pins; and heating the material that has passed through the step above the predetermined temperature and pressurizing it. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25022588A JPH0298195A (en) | 1988-10-04 | 1988-10-04 | Manufacture of multilayer printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25022588A JPH0298195A (en) | 1988-10-04 | 1988-10-04 | Manufacture of multilayer printed board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0298195A true JPH0298195A (en) | 1990-04-10 |
Family
ID=17204701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25022588A Pending JPH0298195A (en) | 1988-10-04 | 1988-10-04 | Manufacture of multilayer printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0298195A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5336353A (en) * | 1990-05-16 | 1994-08-09 | Polyclad Europe Ab | Process for the production of a multilayer printed circuit board |
CN113133227A (en) * | 2019-12-31 | 2021-07-16 | 塔德克公司 | Method for manufacturing multilayer printed circuit board |
US11252823B2 (en) * | 2019-07-02 | 2022-02-15 | Tadco, Inc. LLC | Manufacturing method of multilayer printed circuit boards |
-
1988
- 1988-10-04 JP JP25022588A patent/JPH0298195A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5336353A (en) * | 1990-05-16 | 1994-08-09 | Polyclad Europe Ab | Process for the production of a multilayer printed circuit board |
US11252823B2 (en) * | 2019-07-02 | 2022-02-15 | Tadco, Inc. LLC | Manufacturing method of multilayer printed circuit boards |
CN113133227A (en) * | 2019-12-31 | 2021-07-16 | 塔德克公司 | Method for manufacturing multilayer printed circuit board |
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