JPH0297296A - Motor controller - Google Patents

Abstract

PURPOSE:To transmit and receive the data of low-speed and high-speed processing easily by installing a buffer between both principal arithmetic operation by a host microprocessor and high-speed processing arithmetic operation by a high-speed clock and synchronizing data access from the host microprocessor by the high-speed clock. CONSTITUTION:Buffers 4, 5 for data interfaces are mounted between both principal arithmetic operation by a host microprocessor 1 and high-speed processing arithmetic operation operated by a high-speed clock 10. A signal is acquired by synchronizing data access from the processor 1 by the clock 10, thus easily transmitting and receiving data over and from the digital processing system of low-speed and high-speed processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a motor control device that performs digital speed control of an electric motor.

(Prior Art) With the spread of microcomputers, microcomputers have spread to the field of control, and have become indispensable because they can perform complex and advanced controls. A conventional technique for digital speed control of an electric motor using such a microcomputer will be explained using elevator electric motor control as an example.

FIG. 5 shows a block diagram of the speed control system in the elevator. In the figure, 31 is a three-phase AC power supply, 32 is a converter, 33 is a DC smoothing capacitor, and 34 is an inverter. It is converted into variable frequency alternating current and supplied to the induction motor 37. 38 is a rotation angle detector installed on the motor shaft, and is composed of a pulse generator or a resolver. 3
9 is a sheave, and on this sheave 39 are a counterweight 40 attached to a rope passed over, and an elevator car 41.
By rotating the sheave 39 with an electric motor,
It will be run. A load detector 41a installed in the elevator car 41 outputs a load detection signal.

The speed of the elevator is controlled by applying a constant base drive signal to the inverter 34, and this control will be explained next.

The speed command value output by the speed command value generation block 50 and the rotation angle information output from the rotation angle detector 48 are input to the rotation angle/speed conversion block, and the deviation from the speed detected value obtained thereby. is manually inputted to the speed control block 49, its output and load detection number 47 are inputted to the addition block 47, and the torque command signal is inputted to the vector control calculation block 46.

This vector control calculation block 46 includes a rotation angle detector 4
The rotation angle information output from 8 is also input.

As a result, the vector control calculation block 46 outputs the current command value to the induction motor 37, and the deviation between this and the current detection signal output from the current detector is input to the current control block 45, and this output A certain voltage command signal and the carrier triangular wave output from the carrier triangular wave generation block 44 are input to the comparator 43, and the output of the base signal is inputted to the base drive circuit to generate the base drive signal. 4
7. By supplying this to the inverter, the speed of the elevator is controlled.

In an electric digital speed control system configured as described above, conventionally, the part surrounded by the dotted line in FIG. 5 is a general-purpose microprocessor (hereinafter referred to as a microcomputer),
The operating sequence and protection sequence were digitally processed using a digital circuit made up of IC elements. Then, the digital current command value signal output from the microcomputer is converted into an analog signal by a D/A converter,
The subsequent current control block, carrier ball square wave generation block, and comparator were processed by analog circuits.

However, in analog current control, the analog signal is easily susceptible to changes due to the environment, such as the offset of the operational amplifier, the circuit constant, the μ degree and humidity, and the influence of external noise. There was a point. If you increase the loop cane to further improve the followability of current control,
Since the voltage waveform is disturbed, there is a limit to the followability of current control.

(Problem to be Solved by the Invention) As described above, elevator speed control systems using microcomputers have appeared in order to perform 1m'Af control and fine-grained control. In addition to performing digital processing, the current value command obtained through digital processing is used as a speed command to control the electric motor.

Therefore, the digital current command value signal output from the microcontroller is converted into an analog signal by a D/A converter.
The subsequent current control block, carrier triangular wave generation block, and comparator are processed and controlled by analog circuits. This is because there is a problem with processing speed when current control, gear triangular wave generation, comparator processing, etc. are performed using conventional microcomputers and ICs, so the processing after current control has been configured using analog circuits. .

However, analog current control has problems such as the off-cent and circuit constants of operational amplifiers changing depending on the temperature and humidity environment, and analog signals being easily susceptible to the influence of external noise. Ta. Furthermore, if the loop gain was increased in an attempt to improve the followability of current control, the voltage waveform would be disturbed, so there was a limit to the followability of current control.

On the other hand, in recent years, digital signal processors (hereinafter referred to as DSPs) and custom ICs (hereinafter referred to as A
With the advent of SIC (hereinafter referred to as SIC), high-speed digital signal processing became possible, and current control became possible with digital circuits.

This makes it possible to avoid the effects of the environment and noise mentioned above, and to improve the followability of current control.

However, if all speed control of the Nirebeta, including the current control section, is performed using digital signals, the processing speed of current control, speed detection, etc. is required to be faster than that of a microcomputer. For this reason, either this part is driven by a high-speed clock that is asynchronous to the microcontroller, or the interface between the microcontroller and this part must output both timing signals to each other and be synchronized, which makes this part complicated. For,
Problems arise in that data transfer is restricted and the load on the microcomputer increases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital control type motor control device that is easy to control, does not impose restrictions on data transfer, and does not increase the load on the microcomputer.

[Configuration of the Invention] (Means for Solving the Problems) In order to achieve the objects 1-2, the present invention is configured as follows. In other words, there is a microprocessor at the 1"7 position that performs the main calculations for motor control, and a digital processor that performs high-speed processing calculations and generates motor control values by operating at a clock faster than the operating clock of this microprocessor. In an all-digital motor control system consisting of a processing system, a buffer is provided for a data interface between the two, and data access from the host microprocessor is accessed to the buffer using a signal synchronized by the high-speed clock. It is configured to give and receive.

(Function) In such a configuration, the host microprocessor performs the main control, obtains control information from it, and the digital processing system generates data for direct control of the motor.
Control the electric motor. Since the operating clock of the digital processing system is high speed, there is a speed difference between the digital processing system and the host microcomputer. Therefore,
A buffer is provided for a pig interface between the two, and data access from the host microprocessor is accessed to the buffer using a signal synchronized by the high-speed clock to exchange data.

In other words, in an elevator control device, etc., which has a high-speed digital processing system that controls the system sequence using a host microcomputer and also detects the speed of the system's drive source and controls the current control system, a data buffer is provided to Since data transfer between the computer and the digital processing system is performed using this buffer, the speed detection section and current control section can be allocated to the address space of the host microcontroller, one of the peripherals τj. This makes it possible to handle the data as one, simplifying the data transfer during this time and making it more general-purpose. Therefore, the first microcontroller, speed detection section, and current control section can access this data buffer when exchanging data without any problem even between the host microcontroller, speed detection section, and current control section, which have different operating speeds. You can easily send and receive data.

If all elevator speed control, including the current control section, is performed using digital signals, f! Processing speeds such as current control and speed detection are required to be faster than microcontrollers. For this reason, this part must be driven by a high-speed clock that is asynchronous to the microcontroller, or the interface between the microcontroller and this part must output both timing signals to each other and be synchronized, making it complicated. As a result, data transfer may be restricted or the microcontroller's negative 4
According to the second aspect of the present invention, data can be exchanged between a low-speed digital processing system and a high-speed digital processing system easily and without any burden.
It is possible to provide a digital control type electric motor control device that can be implemented easily and that does not impose restrictions on data transfer.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an elevator all-digital speed control system according to an embodiment of the present invention. In the figure, 1 is a microcomputer, and 2 is a data bus.

3 is a data bus control signal, which is composed of a read signal, a write signal, a chip select signal, and an address bus. Reference numeral 9 indicates a two-phase pulse signal which is the output of the pulse generator, and this two-phase pulse signal 9 is a speed detection ASIC (Appli
cation 5specific +integrate
dCircuit; IC for specific applications) Manually powered by 4. 5 is an ASIC that performs processing after current control together with the DSP 6, and outputs a base drive signal 11.

]0 8 is an analog current detection signal, which is converted into a digital signal by an A/D converter 7 and is applied to the ASIC 5. Reference numeral 10 is a high-speed clock generator for driving 4 to 7, and processing in 4 to 7 is performed in synchronization with this clock.

Next, the operation of the device having such a configuration will be explained.

The microcomputer 1 generates the speed command value (as shown in Fig. 5) along with the operation sequence processing and protection sequence processing.
50), rotation angle/speed conversion (48), speed control (49)
, and the load detection signal (47), and transmits the torque command and the like to ASICs 4 and 5 via the data bus 2.

The ASIC 4 obtains a two-phase pulse signal 9 which is the pulse generator output, converts it into rotation angle information, and sends it to the microcomputer 1.
Transfer to. In addition, part of the vector control calculation 46 in FIG. 5 is performed using this rotation angle information and the slip frequency transferred from the microcomputer 1, and the current command value phase reference signal is
Transfer to SIo5. The DSP 6 performs vector control calculation 46 and current control 45 in FIG. 5 using the current detection signal, current command value phase reference signal, and torque command obtained via the ASIo 5, and transfers the voltage command signal obtained as a result to the ASIC 5. . In ASIC5, the DS mentioned earlier
Interfacing data to P, generating a carrier triangular wave (44) and comparing the voltage command signal and the carrier triangular wave (43) in FIG. 5 are performed. Base drive circuit (4
2) Generates a base signal to be output to.

The data interface between the microcomputer 1 and the ASIo 5 in the all-digital elevator speed control system constructed as described above will be explained with reference to FIG. FIG. 2 is a block diagram of the data bus input/output portion within ASIo.

In FIG. 2, 1 to 4 are the pig bus control signals in FIG. 1, 12 is a read signal, 13 is a chip select signal, 14 is an address bus, ]5 is a write signal,
microcontroller] to the ASIC. 16 is a data bus also shown in FIG. A decoder 17 decodes the data bus control signals 1 to 4, and data such as rotation angles and slip frequencies are input/output from the register in the ASIo to the data bus 16 in response to the data access signal output from this decoder. 19 is the high-speed clock generator I in FIG.
This timing clock is obtained by frequency-dividing the high-speed clock output from O by a counter, and then passing it through decoding and a shift register. A synchronization circuit 18 synchronizes the data access signal output from the decoder 17 with the timing clock 19.

The synchronization circuit 18 can be constructed of a DQ flip-flop, for example, as shown in FIG.

In FIG. 3, 29 is a data access signal, 28 is a synchronization circuit output, and 19 is a timing clock.

In FIG. 2, 20 is a data bus input/output buffer composed of a tri-state buffer with a large output capacity and an input buffer for inputting and outputting data from an input data bus 22 and an output data bus 23 inside the ASIC to the data bus. This output dry state buffer opens its gate by ANDing the read signal and the chip select signal, and outputs the data on the internal output data bus 12 to the data bus 15. Data to be transferred to the microcomputer as a signal within the ASIo, such as the rotation angle, is indicated by ] 3 26 in FIG. These signals are taken into the register 25 by the synchronization circuit output, and the gate of the tri-state buffer 13 connected to the register output is opened by the data access signal which is the synchronization circuit input to the synchronization circuit output, and the internal output It is output to the data bus 12. Then, it passes through the tri-state buffer of the data bus input/output buffer circuit, is output to the pig bus, and is transferred to the microcomputer. Data transferred from the microcomputer to the ASIo is output from the data bus 16 to the internal input data bus 22 via the manual buffer of the data bus input/output buffer circuit 20.

Then, the write signal 15 from the microcomputer is sent to the register 25.
By supplying the data to the internal input data bus, the data is taken into the second stage internal input bus 25a from the internal input data bus. Furthermore, each data is taken into each register 25b by the synchronization circuit output.

In this way, if the input data bus inside the ASIC is configured in two stages and the data is loaded into the first stage register using only the RAID signal, it is difficult to synchronize with the data on the data bus due to the delay of the decoder and synchronization circuit. This is to prevent the timing with the synchronized data access signal, which is the output of the synchronization circuit, from being disrupted and the data on the data bus I- not being taken into the register.

The registers 1, 4, I 5 and 1.7 can be constructed by DQ flip-flops as shown in FIG.

In FIG. 4, ] is a register input signal, 2 is a register output signal, and 28 is a clock input signal, which corresponds to the synchronization circuit output in FIG. 2.

When the data bus input part in the ASIC is configured as described in [1] above, the data transferred from the microcontroller to the ASIC is captured into the registers 25 and 25b in the ΔSIC at an appropriate timing by the synchronization circuit output, and Data transferred from the ASIC to the microcomputer is taken into the register 25 inside the ASIC at appropriate timing by the synchronization circuit output. Therefore, the microcomputer can access data to the ASIC in the same way as accessing data to one address in the address space.

In this way, there is a write data buffer between the detection section and current control section.
A register) and a read data buffer (register) are provided, and the input data hash inside the ASIC is configured in two stages.
By using this buffer to exchange data, it is possible to treat the speed detection section and current control section as one of the peripherals assigned to the address space of the first microcontroller, and data transfer during this time. will be simplified and made more general. Therefore, the first microcontroller, speed detection section, and current control section only need to access these write data buffers and read data buffers when exchanging data. Even if you have one, you can send and receive data without any problems, and the interface is simple.

Therefore, in the present invention, a data access signal from a microcomputer to a circuit part that requires high-speed processing, such as current control, is synchronized with a high-speed clock of a high-speed processing part, thereby providing a versatile elevator. It becomes possible to implement total speed control.

[Effects of the Invention] As stated above, according to the present invention, data exchange between a low-speed processing digital processing system and a high-speed processing digital processing system can be carried out easily and without burden. It is possible to provide a digital control type electric motor control device that does not have restrictions on data transfer.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of an elevator all-digital speed control device showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the structure of the first circuit, and FIG. 4 is a block diagram of a second circuit. FIG. 5 is a diagram showing the register circuit in FIG. ]...Microcomputer, 2...Data bus, 4
．． 5...ASIC, 6...DSP, 7...A/D converter, 10...High speed clock generator, 16...Data bus, 17...Decoder, 18...Synchronization circuit, 25...
register. Applicant's agent Patent attorney Takehiko Suzuobe Figure 3

Claims (1)

[Claims] A host microprocessor that performs the main motor control calculations,
In an all-digital motor control system consisting of a digital processing system that operates at a clock faster than the operating clock of this host microprocessor, performs high-speed processing calculations, and generates motor control values, a buffer is used as a data interface between the two. A motor control device characterized in that a data access from a host microprocessor is synchronized with a signal synchronized by the high speed clock to access the buffer and exchange data.