JPH0297055A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH0297055A
JPH0297055A JP25014988A JP25014988A JPH0297055A JP H0297055 A JPH0297055 A JP H0297055A JP 25014988 A JP25014988 A JP 25014988A JP 25014988 A JP25014988 A JP 25014988A JP H0297055 A JPH0297055 A JP H0297055A
Authority
JP
Japan
Prior art keywords
fixed
terminal
semiconductor device
chips
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25014988A
Other languages
Japanese (ja)
Inventor
Yukio Murakami
村上 幸男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP25014988A priority Critical patent/JPH0297055A/en
Publication of JPH0297055A publication Critical patent/JPH0297055A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce a stress of expansion and contraction due to the heat of a sealing resin, which acts on semiconductor chip through a connecting terminal, to prevent the mechanical breakage of the chips and the like and to obtain a semiconductor device having an improved reliability by a method wherein the connecting terminal is provided in such a way that part of the connecting terminal is fixed on an insulating substrate. CONSTITUTION:In a semiconductor device; wherein an insulating substrate 1, a plurality of metallic electrodes 2a and 2b fixed on the substrate 1, a plurality of semiconductor chips 31a and 31b which are respectively fixed on the surface on one side of each of the electrodes 2a and 2b, and a connecting terminal 51, to which the surfaces on the other sides of the chips 31a and 31b on the electrodes 2a and 2b different from each other are connected directly or through auxiliary connecting components 41a and 41b, are provided and those circuit constituent parts are housed in an enclosure and are resin-sealed; the terminal 51 is provided in such a way that part of the terminal 51 is fixed on the substrate 1. For example, a connecting terminal 51 is fixed on an insulating substrate 1 between metallic electrodes 2a and 2b at its lower end and part of the terminal 51 is connected with auxiliary connecting leads 41a and 41b which are respectively fixed on diode chips 31a and 31b.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、インバータ装置、チョッパ装置などの各種
変換装置に用いられるダイオードブリッジなどの複合形
半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a composite semiconductor device such as a diode bridge used in various conversion devices such as an inverter device and a chopper device.

〔従来の技術〕[Conventional technology]

このような半導体装置の例として、第4図に示したよう
な回路のダイオードブリッジの一例の内部構造を第5図
に、外形図を第6図に示す。第5図(a)は平面図、第
5図11))は第5図(a)の左方から見た側面図であ
って、放熱器への取付はベース8に固着された絶縁基板
l上に金属電極2a、2bが固着されており、金属電極
2a上にはダイオードチップ31a、32a、33aが
、また、金属電極2b上にはダイオードチップ31 b
、 32 b、 33 bがそれぞれ固着されている。
As an example of such a semiconductor device, FIG. 5 shows the internal structure of an example of a diode bridge of the circuit shown in FIG. 4, and FIG. 6 shows an external view. FIG. 5(a) is a plan view, and FIG. 5(11)) is a side view seen from the left side of FIG. 5(a). Metal electrodes 2a, 2b are fixed on top, diode chips 31a, 32a, 33a are on metal electrode 2a, and diode chip 31b is on metal electrode 2b.
, 32b, and 33b are fixed to each other.

チップ31aとチップ31bはこれらのチップにそれぞ
れ固着された補助接続リード41a、41bを介して交
流入力用の接続端子51へ、同様にしてチップ32aと
チップ32bはこれらのチップにそれぞれ対応して固着
された補助接続リード42a、42b(図示せず)を介
して接続端子52へ、同様にしてチップ33aとチップ
33bはそれぞれ対応する補助接続リード43a、43
b(図示せず) を介して接続端子53へ接続されて第
4図に示した回路を構成している。lla、llbはそ
れぞれ金属電極2a、2b上に取り付けられた直流出力
用の外部導出端子である。第6図(a)は外形平面図、
第6図ら)は外形側面図で、第5図に示した回路構底部
は樹脂からなる外枠(外囲器)9内に収められ、封止樹
脂10で封止されている。外部導出端子11a、llb
および接続端子51.52.53の一端は封止樹脂10
の外へ引き出されており、外部回路との接続に用いられ
る。
Chips 31a and 31b are connected to connection terminals 51 for AC input via auxiliary connection leads 41a and 41b fixed to these chips, respectively, and chips 32a and 32b are similarly fixed to these chips in correspondence with each other. Similarly, the chips 33a and 33b are connected to the corresponding auxiliary connection leads 43a and 43 through the auxiliary connection leads 42a and 42b (not shown), respectively, to the connection terminal 52.
b (not shown) to the connecting terminal 53 to form the circuit shown in FIG. lla and llb are external lead-out terminals for direct current output mounted on the metal electrodes 2a and 2b, respectively. Figure 6(a) is an external plan view;
6) are external side views, and the bottom portion of the circuit structure shown in FIG. 5 is housed in an outer frame (envelope) 9 made of resin and sealed with a sealing resin 10. External lead-out terminals 11a, llb
And one end of the connection terminal 51, 52, 53 is sealed with a sealing resin 10
It is pulled out to the outside and is used for connection with external circuits.

上述の例では、半導体チップ(ダイオードチップ)と接
続端子とは補助接続リードを介して接続されているが、
両者が直接接続されてもよい。また、放熱器への取り付
はベースをなくして、絶縁基板自体を取り付はベースと
してもよい。
In the above example, the semiconductor chip (diode chip) and the connection terminal are connected via the auxiliary connection lead,
Both may be directly connected. Furthermore, the base may be omitted for attachment to the heat sink, and the insulating substrate itself may be used as the base for attachment.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第5図に見られる通り、従来の半導体装置では接続端子
は半導体チップに支持されているだけである。このよう
な構成で樹脂封止されているため、半導体装置が運転さ
れるときの半導体チップの発熱による熱サイクルによっ
て封止樹脂が膨張・収縮すると、そのとき発生して接続
端子に加わる応力が全て半導体チップに作用することに
なり、半導体チップが機械的に破壊するなどの問題があ
った。
As seen in FIG. 5, in the conventional semiconductor device, the connection terminals are simply supported by the semiconductor chip. Because the resin is sealed with such a configuration, when the sealing resin expands and contracts due to thermal cycles caused by the heat generated by the semiconductor chip when the semiconductor device is operated, all the stress generated at that time and applied to the connection terminals is absorbed. This causes problems such as mechanical destruction of the semiconductor chip as it acts on the semiconductor chip.

この発明は、上述の問題点を解消して、接続端子を介し
て半導体チップに作用する、封止樹脂の熱による膨張・
収縮の応力を低減し、半導体チップの機械的破壊などを
防止して、信頼性の向上した半導体装置を提供すること
を目的とする。
This invention solves the above-mentioned problems and prevents thermal expansion of the sealing resin that acts on the semiconductor chip through the connection terminal.
The purpose of the present invention is to provide a semiconductor device with improved reliability by reducing shrinkage stress and preventing mechanical breakage of semiconductor chips.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的を達成するために、この発明によれば、絶縁
基板と、その基板上に固着された複数の金属電極と、こ
れら各金属電極上に一方の面で固着された複数の半導体
チップと、それぞれ異なる金属電極上の半導体チップの
他方の面を直接または補助接続部品を介して接続する接
続端子とを備え、これら回路構成部を外囲器の中に収め
樹脂封止してなる半導体装置において、前記接続端子の
一部が前記絶縁基板上に固定されている構成の半導体装
置とする。さらに、前記接続端子の一部が絶縁ブロック
を介して金属電極上に固定されている構成の半導体装置
とすることも望ましい。
In order to achieve the above object, the present invention includes an insulating substrate, a plurality of metal electrodes fixed on the substrate, and a plurality of semiconductor chips fixed on one side on each of the metal electrodes. , connection terminals that connect the other side of semiconductor chips on different metal electrodes directly or through auxiliary connection parts, and these circuit components are housed in an envelope and sealed with resin. In the semiconductor device, a part of the connection terminal is fixed on the insulating substrate. Furthermore, it is also desirable that the semiconductor device be configured such that a part of the connection terminal is fixed onto a metal electrode via an insulating block.

〔作用〕[Effect]

接続端子の一部を絶縁基板または金属電極に固定したの
で、封止樹脂の熱による膨張・収縮によって接続端子に
加わる応力は、絶縁基板または金属電極と半導体チップ
とに分散されるので、半導体チップへの応力は緩和され
ることになる。
Since a part of the connection terminal is fixed to the insulating substrate or metal electrode, the stress applied to the connection terminal due to the thermal expansion and contraction of the sealing resin is dispersed between the insulating substrate or metal electrode and the semiconductor chip. The stress on will be alleviated.

〔実施例〕〔Example〕

第1図は、第4図に示した回路の半導体装置にこの発明
を適用した一実施例について、発明に係わる内部構造を
示す。第1図(a)は平面図であるがダイオードブリッ
ジの各相の構造は同一であるから一相分だけを部分平面
図として示してあり、第1図(b)は同じく側面図を示
す。従来例の第5図と同じ部分には共通の符号を付しで
ある。放熱器への取付はベース8上に固着された絶縁基
板1上に金属電極2a、2bが固着され、金属電極2a
上にはダイオードチップ31aがそのアノード側を下に
して固着され、金属電極2b上にはダイオードチップ3
1bがそのカソード側を下にして固着されている。ダイ
オードチップ31a、31b上にはそれぞれ補助接続リ
ード41a、41bが固着されている。
FIG. 1 shows the internal structure of an embodiment in which the invention is applied to the semiconductor device of the circuit shown in FIG. 4. Although FIG. 1(a) is a plan view, since the structure of each phase of the diode bridge is the same, only one phase is shown as a partial plan view, and FIG. 1(b) similarly shows a side view. The same parts as in the conventional example shown in FIG. 5 are given the same reference numerals. The metal electrodes 2a and 2b are fixed on the insulating substrate 1 fixed on the base 8, and the metal electrodes 2a and 2b are attached to the heat sink.
A diode chip 31a is fixed on the top with its anode side facing down, and a diode chip 31a is fixed on the metal electrode 2b.
1b is fixed with its cathode side facing down. Auxiliary connection leads 41a and 41b are fixed on the diode chips 31a and 31b, respectively.

接続端子51はその下端で金属電極2aと2bの間の絶
縁基板1上においてこれらの金属電極から絶縁分離され
て固定され、かつ、接続端子51の一部はダイオードチ
ップ31a、31bの上に延びていて、それぞれ補助接
続リード41a、41bと接続されている。
The connecting terminal 51 is fixed at its lower end on the insulating substrate 1 between the metal electrodes 2a and 2b while being insulated and separated from these metal electrodes, and a part of the connecting terminal 51 extends over the diode chips 31a and 31b. and are connected to auxiliary connection leads 41a and 41b, respectively.

第2図は、この発明の異なる実施例を示すもので、第2
図(a)は内部構造の部分平面図、第2図(b)は同じ
く側面図を示す。第1図に示した実施例と異なるところ
は、接続端子51の下端が絶縁ブロック61を介して金
属電極2a、2b上に固着されている点であり、各チッ
プの補助接続リードと接続される点は第1図の実施例と
同様である。
FIG. 2 shows a different embodiment of the invention.
FIG. 2(a) is a partial plan view of the internal structure, and FIG. 2(b) is a side view. The difference from the embodiment shown in FIG. 1 is that the lower end of the connection terminal 51 is fixed onto the metal electrodes 2a, 2b via an insulating block 61, and is connected to the auxiliary connection lead of each chip. This is similar to the embodiment shown in FIG.

第3図は、この発明のさらに異なる実施例を示すもので
、その内部構造の部分平面図を示す。第1図に示した実
施例と異なるところは、補助接続リード41a、41b
を省いて、厚さの薄い補助接続端子71を用いて直接に
ダイオードチップ31a、31bと接続端子51の下端
部とを接続した点であり、その分、組立部品数を減らす
ことができる。さらに、この補助接続端子の形状を“く
”の字形とすることにより、ダイオードチップ、接続端
子の高さのズレおよび補助接続端子自体の寸法誤差など
があっても9例えばはんだ付けなどの接続が確実にでき
る利点も得られる。なお、第3図は第1図に示した実施
例、すなわち接続端子が絶縁基板にダイオードチップの
下の金属電極から絶縁分離されて固定されている場合の
例であるが、第2図に示した実施例、すなわち接続端子
がダイオードチップの下のものと共通の金属電極2a、
2b上に固定されている場合にも、この“く”の字形補
助接続端子71は前述と同様に有効である。
FIG. 3 shows still another embodiment of the present invention, and shows a partial plan view of its internal structure. The difference from the embodiment shown in FIG. 1 is that auxiliary connection leads 41a, 41b
This is because the diode chips 31a, 31b and the lower end of the connection terminal 51 are directly connected using the thin auxiliary connection terminal 71, and the number of assembled parts can be reduced accordingly. Furthermore, by making the shape of this auxiliary connection terminal into a dogleg shape, even if there is a height difference between the diode chip and the connection terminal, or a dimensional error of the auxiliary connection terminal itself, the connection can be made by, for example, soldering. You can also get certain benefits. Note that FIG. 3 shows the embodiment shown in FIG. 1, that is, an example in which the connection terminal is fixed to an insulating substrate insulated and separated from the metal electrode under the diode chip. In this embodiment, the metal electrode 2a whose connecting terminal is common to that below the diode chip,
2b, this dogleg-shaped auxiliary connection terminal 71 is also effective in the same manner as described above.

このようにして組み立てられた回路構成部を従来と同様
に外囲器に収め、樹脂で封止して、第6図に示した従来
例と同様な外形の各実施例の半導体装置が得られる。
The circuit components assembled in this way are placed in an envelope as in the conventional case and sealed with resin to obtain the semiconductor device of each embodiment having the same external shape as the conventional example shown in FIG. .

上述の実施例では、放熱器への取り付はベースを用いて
いるが、これをなくして、絶縁基板自体を取り付はベー
スとしてもよい。
In the embodiments described above, a base is used for attachment to the heat sink, but this may be omitted and the insulating substrate itself may be used as the base for attachment.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、接続端子の一端が半導体チップ上に
直接固着されて支持されるのではなく、半導体チップの
下側の絶縁基板または金属電極にもその一部が固定され
支持される端子構成となっている。従って、封止樹脂の
熱による膨張・収縮によって接続端子に加わる応力は半
導体チップと絶縁基板または金属電極に分散されること
になり、半導体チップへの応力は緩和される。その結果
、熱サイクルによる半導体チップの損傷やパワーサイク
ルによる1例えばはんだ付けなどの固着部の疲労を防止
することができ、信頼性の向上した半導体装置を得るこ
とが可能となる。
According to this invention, one end of the connection terminal is not directly fixed and supported on the semiconductor chip, but a terminal structure in which a part of the connection terminal is also fixed and supported on the insulating substrate or metal electrode below the semiconductor chip. It becomes. Therefore, the stress applied to the connection terminal due to thermal expansion and contraction of the sealing resin is dispersed between the semiconductor chip and the insulating substrate or metal electrode, and the stress on the semiconductor chip is alleviated. As a result, it is possible to prevent damage to the semiconductor chip due to thermal cycling and fatigue of fixed parts such as soldering due to power cycling, and it is possible to obtain a semiconductor device with improved reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はこの発明に係わる半導体装置のそ
れぞれ異なる実施例の内部構造を示すもので、第1図お
よび第2図の各(a)は部分平面図、第1図および第2
図の各ら)は側面図である。第3図はさらに異なる実施
例の内部構造の部分平面図である。第4図は半導体装置
の一例の回路図である。第5図は半導体装置の従来例の
内部構造を示すもので、第5図(a)は平面図、第5図
(b)は側面図である。第6図は半導体装置の従来例お
よび実施例の外形の一例を示すもので、第6図(a)は
平面図、第6図ら)は側面図である。 1 絶縁基板、2a、2b  金属電極、9 外枠(外
囲器)、10  封止樹脂、31a、31b  ダイオ
ードチップ(半導体チップ)、41a、41b  補助
接続リード、51  接続端子、61  絶縁ブロック
、71  “く”の字形補助接続端子。 (C1)   第  コ  [ミ(1 (b) 第2図 (a) 第 図 第 図 第 図 (b) 第 図
1 and 2 show the internal structures of different embodiments of the semiconductor device according to the present invention, and (a) in each of FIGS. 1 and 2 is a partial plan view, and (a) in each of FIGS.
Each of the figures) is a side view. FIG. 3 is a partial plan view of the internal structure of yet another embodiment. FIG. 4 is a circuit diagram of an example of a semiconductor device. FIG. 5 shows the internal structure of a conventional example of a semiconductor device, with FIG. 5(a) being a plan view and FIG. 5(b) being a side view. FIG. 6 shows an example of the external appearance of a conventional example and an example of a semiconductor device, and FIG. 6(a) is a plan view, and FIGS. 6(a) and 6(b) are side views. 1 Insulating substrate, 2a, 2b Metal electrode, 9 Outer frame (envelope), 10 Sealing resin, 31a, 31b Diode chip (semiconductor chip), 41a, 41b Auxiliary connection lead, 51 Connection terminal, 61 Insulation block, 71 “V” shaped auxiliary connection terminal. (C1) No. Ko [Mi (1 (b) Fig. 2 (a) Fig. Fig. Fig. (b) Fig.

Claims (1)

【特許請求の範囲】[Claims] 1)絶縁基板とその基板上に固着された複数の金属電極
とこれら各金属電極上に一方の面で固着された複数の半
導体チップとそれぞれ異なる金属電極上の半導体チップ
の他方の面を直接または補助接続部品を介して接続する
接続端子とを備え、これら回路構成部を外囲器の中に収
め樹脂封止してなる半導体装置において、前記接続端子
の一部が前記絶縁基板上に固着されていることを特徴と
する半導体装置。
1) An insulating substrate, a plurality of metal electrodes fixed on the substrate, a plurality of semiconductor chips fixed on one side on each of these metal electrodes, and the other side of the semiconductor chips on different metal electrodes directly or In a semiconductor device comprising connection terminals connected via auxiliary connection parts, and in which these circuit components are housed in an envelope and sealed with resin, a part of the connection terminals is fixed on the insulating substrate. A semiconductor device characterized by:
JP25014988A 1988-10-04 1988-10-04 Semiconductor device Pending JPH0297055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25014988A JPH0297055A (en) 1988-10-04 1988-10-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25014988A JPH0297055A (en) 1988-10-04 1988-10-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0297055A true JPH0297055A (en) 1990-04-09

Family

ID=17203546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25014988A Pending JPH0297055A (en) 1988-10-04 1988-10-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0297055A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012059876A (en) * 2010-09-08 2012-03-22 Sanken Electric Co Ltd Semiconductor module and manufacturing method of the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139054A (en) * 1984-12-11 1986-06-26 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139054A (en) * 1984-12-11 1986-06-26 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012059876A (en) * 2010-09-08 2012-03-22 Sanken Electric Co Ltd Semiconductor module and manufacturing method of the same

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