JPH02188946A - Resin-sealed semiconductor device and manufacture thereof - Google Patents

Resin-sealed semiconductor device and manufacture thereof

Info

Publication number
JPH02188946A
JPH02188946A JP1009382A JP938289A JPH02188946A JP H02188946 A JPH02188946 A JP H02188946A JP 1009382 A JP1009382 A JP 1009382A JP 938289 A JP938289 A JP 938289A JP H02188946 A JPH02188946 A JP H02188946A
Authority
JP
Japan
Prior art keywords
resin
sealed
molded part
heat sink
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1009382A
Other languages
Japanese (ja)
Inventor
Hidekazu Awaji
淡路 英一
Tatsuya Kato
達也 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1009382A priority Critical patent/JPH02188946A/en
Publication of JPH02188946A publication Critical patent/JPH02188946A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To supply a device in which various kinds of circuit constitutions have been compounded, which does not require an external insulation treatment and which is small-sized and can be handled simply and easily by a method wherein a heat sink on which a semiconductor chip has been mounted is sealed with a first resin, a circuit component is then mounted on a lead and this whole assembly is sealed with a second resin. CONSTITUTION:A heat sink 22 on which a semiconductor chip 21 has been mounted is sealed in a first resin-molded part 27; a circuit component 25 is mounted on a lead 24b which is interlinked with the first resin-molded part 27; said first resin-molded part 27 and said circuit component 25 are sealed with a second resinmolded part 29. For example, a heat sink 22 on which a semiconductor chip 21 has been mounted is sealed with a first resin in a state that strips 23 extended from the heat sink 22 and leads 24a are gripped by using a first metal mold and that the heat sink 22 is levitated in a space inside the metal mold. Then, the strips 23 and one part of the leads 24a are cut; a circuit component 25 is mounted on a remaining lead 24b; and an electrical connection such as a soldering operation or the like is executed. After that, a first resin-molded part 27 and external leads 24c are gripped by using a second molding metal mold and are positioned; and a second resin-molded part 29 is formed.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は放熱板が絶縁封止された樹脂封止型半導体装置
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a resin-sealed semiconductor device in which a heat sink is insulated and sealed.

〈発明の概要〉 本発明は、半導体チップを搭載した放熱板を第1の樹脂
で封止後、抵抗やコンデンサ等の回路部品をリード上に
搭載・接続し、全体を第2の樹脂で封止することによっ
て従来の外付は部品を一体化した電力用の樹脂封止型半
導体装置を提供する。
<Summary of the Invention> The present invention involves sealing a heat sink on which a semiconductor chip is mounted with a first resin, mounting and connecting circuit components such as resistors and capacitors on the leads, and sealing the entire thing with a second resin. By doing so, it is possible to provide a resin-sealed semiconductor device for electric power in which conventional external components are integrated.

〈従来の技術〉 近年、機器制御用リレーの高信頼性・長寿命の要望に対
応し、無接点リレーすなわち樹脂封止型半導体装置であ
るソリッドステートリレーが進展している。一般的なソ
リッドステートリレーは第8図に例示のような回路で構
成されている。
<Prior Art> In recent years, in response to the demand for high reliability and long life of device control relays, non-contact relays, that is, solid state relays that are resin-sealed semiconductor devices have been developed. A general solid state relay is constructed of a circuit as illustrated in FIG.

この例において、ソリッドステートリレーは発光ダイオ
ード1と7オトサイリスタが逆並列されたフォトトライ
アック2からなる光結合部3と、光結合部3の出力によ
って駆動されるトライアック4から構成されており、入
力信号がリミット抵抗RLを介して発光ダイオード1に
印加されると、フォトトライアック2がターンオンし、
トライアック4のゲートに電流を供給してトライアック
4をターンオンさせることだよって、右方部上回路のス
イッチングを行なう。
In this example, the solid state relay is composed of an optical coupling section 3 consisting of a phototriac 2 in which light emitting diodes 1 and 7 otothyristors are connected in antiparallel, and a triac 4 driven by the output of the optical coupling section 3. When a signal is applied to the light emitting diode 1 through the limit resistor RL, the phototriac 2 turns on,
By supplying current to the gate of the triac 4 to turn on the triac 4, switching of the upper right circuit is performed.

このような動作を行なうソリッドステートリレーは、従
来光結合素子やトライアック等の個別部品やリード端子
をプリント基板に組込み、樹脂封止して形成されていた
。これに対し、本出願人は半導体チップのみによって構
成した樹脂封止型のソリッドステートリレーを提案した
(例えば特願昭57−153617号)。この構造を第
9図に示す。
Solid state relays that perform such operations have conventionally been formed by incorporating individual components such as optical coupling elements and triacs and lead terminals into a printed circuit board and sealing the board with resin. In response to this, the present applicant has proposed a resin-sealed solid state relay constructed only of semiconductor chips (for example, Japanese Patent Application No. 153617/1982). This structure is shown in FIG.

第9図において、ソリッドステートリレーは、放熱板5
上に、フォトトライアック2と透明絶縁層を介し光結合
する発光ダイオード1から成る光結合部3とトライアッ
ク4を搭載して構成しており、前述のプリント基板組込
みタイプに比して大巾な小型が実現されている。
In FIG. 9, the solid state relay has a heat sink 5
On the top, an optical coupling section 3 consisting of a phototriac 2 and a light emitting diode 1 optically coupled through a transparent insulating layer and a triac 4 are mounted. has been realized.

このソリッドステートリレーの機器への組込み例を第1
0図に示す。ソリッドステートリレーは機器放熱体7に
ねじ8によって固定されるが、放熱板5は負荷の電源ラ
インに接続されており、機器放熱体7と電気的絶縁する
ためには絶縁板9が必要となる。
The first example of incorporating this solid state relay into equipment is
Shown in Figure 0. The solid state relay is fixed to the equipment heat sink 7 with screws 8, but the heat sink 5 is connected to the power supply line of the load, and an insulating plate 9 is required to electrically insulate it from the equipment heat sink 7. .

この対応を図るべく、第11図のような成形樹脂lOで
放熱板を絶縁封止した半導体装置の構造が種々提案され
ている(例えば特開昭57178357号公報、特開昭
60−7750号公報)。
In order to cope with this problem, various structures of semiconductor devices have been proposed in which a heat sink is insulated and sealed with molded resin lO as shown in FIG. ).

第11図において、細条突起11は放熱板5を成型金型
内で適正に位置決めするために上下の金型で挾持した細
条の冷片である。
In FIG. 11, the strip projections 11 are strip cold pieces that are held between upper and lower molds in order to properly position the heat dissipation plate 5 within the mold.

〈発明が解決しようとする課題〉 前述のソリッドステートリレーの実際の使用に際しては
、スイッチングノイズの吸収、誤動作の防止を図るため
、第8図に示すように抵抗、コンデンサから成るスナバ
回路6を外部に付加して用いることが多い。このスナバ
回路は一般的にリード抵抗とフィルムコンデンサを用い
るため、ソリッドステートリレー本体の小型化を図って
も外部回路のサイズが大きく、システム全体としては小
型化、高密度実装の実現の支障となり、外部回路を含め
た小型一体化が望まれていた。
<Problems to be Solved by the Invention> When the solid state relay described above is actually used, in order to absorb switching noise and prevent malfunction, the snubber circuit 6 consisting of a resistor and a capacitor is connected externally as shown in FIG. It is often used in addition to. This snubber circuit generally uses a lead resistor and a film capacitor, so even if the solid state relay body is made smaller, the size of the external circuit is large, which hinders the miniaturization of the entire system and the realization of high-density packaging. Compact integration including external circuits was desired.

また放熱板5の絶縁を要することが多く、第11図の構
造を採用することも考えられるが、細条突起11が機器
放熱体7に1〜2厘程度と近接しており、電源ラインと
機器本体との電位差が数百ポルト以上に及ぶため、何ら
かの絶縁処理が必要となる。
In addition, insulation of the heat sink 5 is often required, and it is possible to adopt the structure shown in FIG. Since the potential difference between the device and the main body is several hundred ports or more, some type of insulation treatment is required.

この対策として、細条突起11に樹脂塗布を施す(特開
昭60−16451号公報)ことや、細条突起を再度、
成形封止する(特開昭59−215752号公報)こと
が提案されている。しかしながら、これらの手段は本来
の製品構成に不要な工程を付加するため、製品コストの
上昇を招きやすく、上記の外部回路の一体化と併わせた
絶縁タイプの樹脂封止型半導体装置の開発が望まれてい
た。
As a countermeasure against this, it is possible to coat the strip projections 11 with resin (Japanese Patent Application Laid-Open No. 16451/1983), or to re-apply the strip projections 11 with resin.
It has been proposed to mold and seal (Japanese Unexamined Patent Publication No. 59-215752). However, these methods add unnecessary steps to the original product configuration, which tends to increase product costs, and it is difficult to develop an insulated resin-sealed semiconductor device in conjunction with the integration of the external circuit described above. It was wanted.

く課題を解決するための手段〉 本発明においては、上記の課題を解決すべく第1図から
第4図に示すような樹脂封止型半導体装置の構成とする
Means for Solving the Problems> In the present invention, in order to solve the above problems, a resin-sealed semiconductor device is constructed as shown in FIGS. 1 to 4.

即ち、第1〜第4図において、半導体テップ2工を搭載
した放熱板22を、放熱板22から延長した細条23と
リード24aを第1の金型で挾持し、放熱板22を金型
内の空所に浮かした状態で第1の樹脂で封止する。
That is, in FIGS. 1 to 4, the heat sink 22 on which the two semiconductor chips are mounted is held between the strips 23 and leads 24a extending from the heat sink 22 by a first mold, and the heat sink 22 is placed in the mold. It is sealed with the first resin while floating in the space inside.

しかるのち、細条23とリード24aの一部を切断し、
残存するリード24b上に回路部品25を搭載、半田付
は等の電気的接続を行なう。この後、第2の成形金型2
6にて第1の樹脂成形部27と外部リード24cを挾持
して位置決めし、vj2の樹脂により第4の樹脂成形部
27、回路部品を搭載したリード24b及び第1の樹脂
成形部27から露呈している細条突起28を成形封止し
て第2の樹脂成形部29を形成したのち、外部リード2
4cに連接した共通接続細条30の切断処理を施す。
After that, part of the strip 23 and the lead 24a is cut,
The circuit components 25 are mounted on the remaining leads 24b, and electrical connections such as soldering are made. After this, the second molding die 2
6, the first resin molded part 27 and the external lead 24c are sandwiched and positioned, and the fourth resin molded part 27, the lead 24b on which the circuit component is mounted, and the first resin molded part 27 are exposed by the resin of vj2. After forming the second resin molded part 29 by molding and sealing the striped protrusions 28, the external leads 2
The common connection strip 30 connected to 4c is cut.

〈作 用〉 このような手段を採用することにより、第1の樹脂成形
後、リード24aが第4の樹脂成形部27に固着されて
いるためリード切断が可能となり、また半導体チップ2
1が樹脂封止されていることにより、リード24b上へ
の回路部品25の半田付は処理等が極めて容易に行える
。さらに第2の樹脂成形を行なうことによって回路部品
25を封止するとともに残存している細条突起28を絶
縁封止することが同一工程にて対処できる。この際、第
2の成型金型26における金型内の位置決めは第1の樹
脂成形部27を挾持して行なうため、高精度の成形が可
能である。
<Function> By adopting such a means, after the first resin molding, the leads 24a are fixed to the fourth resin molded part 27, so the leads can be cut, and the semiconductor chip 2
1 is sealed with resin, soldering of the circuit component 25 onto the lead 24b can be performed extremely easily. Further, by performing a second resin molding, it is possible to seal the circuit component 25 and insulate the remaining strip projections 28 in the same process. At this time, since the second molding die 26 is positioned within the mold by holding the first resin molded part 27 between them, highly accurate molding is possible.

〈実施例〉 次に図面に基づき、さらに詳しい実施例について説明す
る。
<Example> Next, a more detailed example will be described based on the drawings.

尚、説明はソリッドステートリレーを引用して行なうが
、本発明はこれだ限定されるものではなく、同様の構成
を持つインバータモジュールやスイッチング電源用レギ
ュレータやDCリレー等の電力用の樹脂封止型半導体装
置、すなわち半導体チップと回路部品が同一パッケージ
内に封止された半導体装置に適用できることは勿論のこ
とである。
Although the description will be made with reference to solid state relays, the present invention is not limited to this, and may be applied to resin-sealed power relays such as inverter modules, switching power supply regulators, and DC relays having similar configurations. Of course, the present invention can be applied to a semiconductor device, that is, a semiconductor device in which a semiconductor chip and circuit components are sealed in the same package.

第1図のソリッドステートリレーを形成するために、ま
ず第2図に示すようなリードフレームが用いられる。リ
ードフレームは放熱板22と放熱板22から延長した細
条23.リード24 (a、CL共通接続細条30等か
ら構成されている。そして放熱板22にトライアック等
の半導体チップ21を半田、付けし、次にアルミ等の金
属細線31によってワイヤポンドした後、第2図中に点
線で記載している形状に第1の樹脂封止を行なう。成形
に際し、第1の金型により細条23とリード24a。
In order to form the solid state relay of FIG. 1, a lead frame as shown in FIG. 2 is first used. The lead frame includes a heat sink 22 and strips 23 extending from the heat sink 22. Leads 24 (a, CL common connection strips 30, etc.) are soldered and attached to the heat sink 22, and then wire-bonded with thin metal wires 31 such as aluminum. 2. First resin sealing is performed in the shape indicated by dotted lines in Figure 2. During molding, the strips 23 and leads 24a are formed using the first mold.

外部リード24c等を挾持して位置決めする。尚この細
条23がなくても成形は可能であるが、放熱板22の位
置精度が悪くなる。
The external lead 24c and the like are held and positioned. Although molding is possible without the strips 23, the positional accuracy of the heat sink 22 will be poor.

第1の樹脂成形後、第3図に示すリードフレーム形状に
すべく、細条23を切断し、細条突起28を形成する。
After the first resin molding, the strips 23 are cut to form strip protrusions 28 to form the lead frame shape shown in FIG.

またこの工程と同時若しくは別にリード24aを部分的
だ切断、打抜いて残存するリード24bを形成する。こ
の工程は完成品において外部リード24c以外に不要な
活軍部分を露呈させないことと、パッケージ内配線の中
継端子を形成するために行なう。細条23及びリード2
4aの切断後、回路部品25 (a+b+c)を搭載す
る。
Further, at the same time as this step or separately, the leads 24a are partially cut and punched to form the remaining leads 24b. This step is performed to prevent unnecessary active portions other than the external leads 24c from being exposed in the finished product and to form relay terminals for wiring within the package. Strip 23 and lead 2
After cutting 4a, circuit components 25 (a+b+c) are mounted.

本例において回路部品25は光結合素子25a。In this example, the circuit component 25 is an optical coupling element 25a.

スナバ回路用のチップ抵抗25b及びチップコンデンサ
25cによって構成している。
It is composed of a chip resistor 25b and a chip capacitor 25c for a snubber circuit.

回路部品25は通常の半田付は工程を用いて行なわれ、
半田付は後、残存する半田フラックスを除去するため、
全体を溶剤洗滌する9この際、半導体チップ21は第1
の樹脂成形部27によって封止されているため、特別な
配慮は不要である。
The circuit component 25 is soldered using a normal soldering process,
After soldering, remove the remaining solder flux.
9. At this time, the semiconductor chip 21 is
Since it is sealed by the resin molded part 27, no special consideration is required.

溶剤洗滌後、第3図中に点線で記載している形状に第2
の樹脂封止をする。これは第4図に示すような第2の成
形金型26 (a、b)を用いて行なわれる。すなわち
、上金型26aと下金型26bとが第1の樹脂成形部2
7及び外部リード24c及び共通接続細条30a、80
bを挾持した状態で、残存するり−ド24b、回路部品
25.第1の樹脂成形部27及び細条突起28を第2の
樹脂によって第2の樹脂成形部29を形成する。その後
、外部リード24cを連接している共通接続細条30a
及び30bを切断し、外部リード24cを分離し、さら
に外部リード24cVC半田メツキを施す。
After solvent cleaning, a second
Seal with resin. This is done using a second mold 26 (a, b) as shown in FIG. That is, the upper mold 26a and the lower mold 26b form the first resin molding part 2.
7 and external leads 24c and common connection strips 30a, 80
The remaining glue 24b and circuit components 25.b are held in place. A second resin molded portion 29 is formed by replacing the first resin molded portion 27 and the strip projection 28 with a second resin. Thereafter, the common connection strip 30a connecting the external lead 24c
and 30b are cut, the external lead 24c is separated, and the external lead 24c is further subjected to VC solder plating.

以上の工程により、半導体テップ21と回路部品25が
一体的に絶縁封止されたソリッドステートリレーが完成
される。
Through the above steps, a solid state relay in which the semiconductor chip 21 and the circuit component 25 are integrally insulated and sealed is completed.

尚、本実施例は第2図だ示す形状のリードフレームを用
いたが、リード24aの補強と第1の樹脂成形時におけ
る樹脂のリード24aへの流入を防止するために、第5
図のように第3の共通接続細条80cを付加し、第1の
樹脂成形後、切断除去することも採用できる。また、第
1の樹脂成形後、リード24aを切断せずに回路部品2
5を搭載し、そののちにリード24aを部分的に切断す
ることも可能である。また、入力側のリミット抵抗を併
せて搭載することもできる。
Although this embodiment used a lead frame having the shape shown in FIG. 2, in order to reinforce the leads 24a and prevent resin from flowing into the leads 24a during the first resin molding, a fifth
As shown in the figure, it is also possible to add a third common connection strip 80c and cut and remove it after the first resin molding. Moreover, after the first resin molding, the circuit component 2 can be removed without cutting the leads 24a.
It is also possible to mount the lead 24a and then partially cut the lead 24a. Additionally, a limit resistor on the input side can also be installed.

次にその他の実施例について説明する。これまでの説明
においては、回路部品25を構成するひとつの部品とし
て個別部品の光結合素子25aを搭載したが、これとは
別に光結合素子を半導体チップ21と同一の樹脂成形部
に封止して形成することができる。第6図及び第7図に
その実施例を示す。
Next, other embodiments will be described. In the explanation so far, the optical coupling element 25a, which is an individual component, is mounted as one component constituting the circuit component 25, but the optical coupling element is separately sealed in the same resin molding part as the semiconductor chip 21. It can be formed by Examples thereof are shown in FIGS. 6 and 7.

ここでフォトトライアックチップ31はポリイミドシー
ト等の絶縁板32を介して放熱板22に搭載され、第6
図においては発光ダイオードチップ33がリード24d
上に搭載され、金線35によるワイヤボンド後、透明シ
リコン樹脂36によって光経路を形成する。第7図の場
合は、発光ダイオード33が、フォトトライアック31
上に積層され発光ダイオード33からの電極取出し部を
備えた透明絶縁層34上に搭載して光結合を行なう。こ
れらの光結合部を封止する第1の樹脂成形部27は、光
電変換効率を向上させるため、光反射性の高い酸化チタ
ンTiO2や炭酸カルシウムCaCO3等の白色顔料を
混入した樹脂を用いることが望ましい。
Here, the phototriac chip 31 is mounted on the heat dissipation plate 22 via an insulating plate 32 such as a polyimide sheet.
In the figure, the light emitting diode chip 33 is connected to the lead 24d.
After wire bonding with a gold wire 35, an optical path is formed with a transparent silicone resin 36. In the case of FIG. 7, the light emitting diode 33 is a phototriac 31
The light-emitting diode 33 is mounted on a transparent insulating layer 34 which is laminated thereon and has an electrode lead-out portion from the light-emitting diode 33 for optical coupling. The first resin molded part 27 that seals these optical coupling parts may be made of a resin mixed with a white pigment such as titanium oxide TiO2 or calcium carbonate CaCO3, which has high light reflectivity, in order to improve photoelectric conversion efficiency. desirable.

〈発明の効果〉 以上に述べたよう忙本発明の樹脂封止型半導体装置は、
半導体チップと回路部品を同一のパッケージ内に封止す
ることが容易に行なわれ、また外部に露呈させたくない
中継端子や細条突起や放熱板を完全に絶縁封止すること
ができる。これらのことによって多種多様な回路構成を
複合化した外部絶縁処理の不要な小型で取扱い簡便なデ
バイスの供給が実現される。
<Effects of the Invention> As described above, the resin-sealed semiconductor device of the present invention has the following advantages:
A semiconductor chip and circuit components can be easily sealed in the same package, and relay terminals, strip projections, and heat sinks that should not be exposed to the outside can be completely insulated and sealed. As a result, it is possible to supply a small and easy-to-handle device that combines a wide variety of circuit configurations and does not require external insulation treatment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の樹脂封止型半導体装置の一実施例の断
面図、第2図(a)及び(b)は同じく半導体チップ搭
載後の状態を表わす平面図及び側面図、第3図(a)及
び(b)は同じく回路部品を搭載した状態を表わす平面
図及び側面図、第4図は第2の樹脂成形の断面図、第5
図は同実施例の異なる形状のリードフレームの平面図、
第6図(a)及び(b)、第7図(a)及び(b)は各
々、本発明のその他の実施例の平面図及び部分断面図、
第8図はソリッドステートリレーの回路図、第9図は従
来のソリッドステートリレーを示す平面図、第1O図は
従来のソリッドステートリレーの機器への取り付は状態
を示す断面図、第11図は従来の放熱板を絶縁封止した
樹脂封止型半導体装置の機器への取り付は状態を示す断
面図である。 21・・・半導体チップ、22・・・放熱板、23・・
・細条、24a・・リード、24b・・・残存するリー
ド、25c・・・外部リード、26・第2の成形金型、
27・・・第1の樹脂成形部、28・・・細条突起、2
9・・・第2の樹脂成形部、30・・・共通接続細条。 代理人 弁理士 杉 山 毅 至(他1名)(σ) (b) 第2図 (G) 萬3図 (b) 第5図 第8図 第1O図
FIG. 1 is a sectional view of an embodiment of a resin-sealed semiconductor device of the present invention, FIGS. 2(a) and (b) are a plan view and a side view showing the state after mounting a semiconductor chip, and FIG. (a) and (b) are a plan view and a side view showing the state in which circuit components are mounted, FIG. 4 is a cross-sectional view of the second resin molding, and FIG.
The figure is a plan view of a lead frame with a different shape in the same example.
6(a) and (b) and FIG. 7(a) and (b) are respectively a plan view and a partial sectional view of other embodiments of the present invention;
Figure 8 is a circuit diagram of a solid state relay, Figure 9 is a plan view showing a conventional solid state relay, Figure 1O is a sectional view showing how the conventional solid state relay is installed in equipment, and Figure 11. 1 is a cross-sectional view showing how a conventional resin-sealed semiconductor device with a heat dissipation plate insulated and sealed is attached to a device. 21... Semiconductor chip, 22... Heat sink, 23...
- Strip, 24a... Lead, 24b... Remaining lead, 25c... External lead, 26 - Second molding die,
27... First resin molded part, 28... Strip projection, 2
9... Second resin molded part, 30... Common connection strip. Agent Patent attorney Takeshi Sugiyama (1 other person) (σ) (b) Figure 2 (G) Figure 3 (b) Figure 5 Figure 8 Figure 1O

Claims (1)

【特許請求の範囲】 1、半導体チップを搭載した放熱板が第1の樹脂成形部
に封止され、前記第1の樹脂成形部に連接するリードに
回路部品を搭載し、前記第1の樹脂成形部及び前記回路
部品を第2の樹脂成形部により封止してなることを特徴
とする樹脂封止型半導体装置。 2、放熱板上に半導体チップを搭載し、前記放熱板から
延長した細条とリードを第1の成形金型で挾持して放熱
板を該金型内の空所に浮かせた状態で第1の樹脂成形部
を形成したのち、前記細条及び前記リードの一部を切断
し、残存するリード上に回路部品を搭載及び電気的接続
し、さらに第2の成形金型にて前記第1の樹脂成形部と
外部リードを挾持して位置決めして第1の樹脂成形部と
前記の回路部品の搭載部と前記第1の樹脂成形部からの
細条突起を封止して第2の樹脂成形部を形成したのち、
外部リードに連接する共通接続細条の切断処理を施すこ
とを特徴とする樹脂封止型半導体装置の製造方法。
[Scope of Claims] 1. A heat dissipation plate mounted with a semiconductor chip is sealed in a first resin molded part, a circuit component is mounted on a lead connected to the first resin molded part, and A resin-sealed semiconductor device, characterized in that a molded part and the circuit component are sealed by a second resin molded part. 2. A semiconductor chip is mounted on a heat sink, the strips and leads extending from the heat sink are held in a first molding mold, and the heat sink is suspended in the cavity in the mold. After forming the resin molded part, the strip and part of the lead are cut, circuit components are mounted and electrically connected on the remaining leads, and then the first part is molded in a second molding die. The resin molded part and the external lead are held and positioned, the first resin molded part, the circuit component mounting part, and the strip projections from the first resin molded part are sealed, and the second resin molded part is molded. After forming the section,
A method of manufacturing a resin-sealed semiconductor device, comprising cutting a common connection strip connected to an external lead.
JP1009382A 1989-01-17 1989-01-17 Resin-sealed semiconductor device and manufacture thereof Pending JPH02188946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1009382A JPH02188946A (en) 1989-01-17 1989-01-17 Resin-sealed semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1009382A JPH02188946A (en) 1989-01-17 1989-01-17 Resin-sealed semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH02188946A true JPH02188946A (en) 1990-07-25

Family

ID=11718904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1009382A Pending JPH02188946A (en) 1989-01-17 1989-01-17 Resin-sealed semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH02188946A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001293213A (en) * 2000-04-11 2001-10-23 Sanyo Product Co Ltd Game machine
JP2008136333A (en) * 2006-10-30 2008-06-12 Denso Corp Power converter
JP2011238906A (en) * 2010-04-14 2011-11-24 Denso Corp Semiconductor module
JP2015228422A (en) * 2014-06-02 2015-12-17 パナソニックIpマネジメント株式会社 Semiconductor device manufacturing method and semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151035A (en) * 1982-03-04 1983-09-08 Toshiba Corp Preparation of semiconductor device
JPS62126657A (en) * 1985-11-28 1987-06-08 Matsushima Kogyo Co Ltd Resin-molded hybrid-ic mounting structure enclosing piezoelectric vibrator
JPS63258028A (en) * 1987-04-15 1988-10-25 Nec Corp Manufacture of semiconductor integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151035A (en) * 1982-03-04 1983-09-08 Toshiba Corp Preparation of semiconductor device
JPS62126657A (en) * 1985-11-28 1987-06-08 Matsushima Kogyo Co Ltd Resin-molded hybrid-ic mounting structure enclosing piezoelectric vibrator
JPS63258028A (en) * 1987-04-15 1988-10-25 Nec Corp Manufacture of semiconductor integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001293213A (en) * 2000-04-11 2001-10-23 Sanyo Product Co Ltd Game machine
JP2008136333A (en) * 2006-10-30 2008-06-12 Denso Corp Power converter
JP2011238906A (en) * 2010-04-14 2011-11-24 Denso Corp Semiconductor module
US8796816B2 (en) 2010-04-14 2014-08-05 Denso Corporation Semiconductor module with electrical switching elements
JP2015228422A (en) * 2014-06-02 2015-12-17 パナソニックIpマネジメント株式会社 Semiconductor device manufacturing method and semiconductor device

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