JPH0296699U - - Google Patents

Info

Publication number
JPH0296699U
JPH0296699U JP538489U JP538489U JPH0296699U JP H0296699 U JPH0296699 U JP H0296699U JP 538489 U JP538489 U JP 538489U JP 538489 U JP538489 U JP 538489U JP H0296699 U JPH0296699 U JP H0296699U
Authority
JP
Japan
Prior art keywords
address
logic level
switching
section
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP538489U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP538489U priority Critical patent/JPH0296699U/ja
Publication of JPH0296699U publication Critical patent/JPH0296699U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路図である
。 １……行アドレスデコーダ、２……列アドレス
デコーダ、３……アドレス切換回路、４……アド
レス切換設定回路、５……マスクＲＯＭ部、６…
…ＥＰＲＯＭ部、７……書込・制御回路、Ｇ１１
〜Ｇ１ｎ，Ｇ２１〜Ｇ２ｎ……ＡＮＤゲート、Ｉ
１〜Ｉｎ……インバータ、Ｍ１〜Ｍｎ……切換用
メモリセル。 FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1... Row address decoder, 2... Column address decoder, 3... Address switching circuit, 4... Address switching setting circuit, 5... Mask ROM section, 6...
...EPROM section, 7...Writing/control circuit, G 11
 〜G 1n , G 21 〜G 2n ...AND gate, I
1 to In ...Inverter, M1 to Mn ...Switching memory cell.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第１及び第２の論理レベルの何れか一方を出力
する複数の切換用メモリセルを備え、これら各切
換用メモリセルの論理レベルに応じてアドレスデ
コーダからの各アドレス出力信号をそれぞれ第１
および第２の出力端の何れか一方へ伝達するアド
レス切換回路と、前記各切換用メモリセルの論理
レベルを設定するアドレス切換設定部と、前記ア
ドレス切換回路の第１の出力端からのアドレス出
力信号の指定するアドレスから記憶されているデ
ータを読出すマスクＲＯＭ部と、前記アドレス切
換回路の第２の出力端からのアドレス出力信号の
指定するアドレスにデータを書込み記憶する一方
、前記第２の出力端からのアドレス出力信号の指
定するアドレスから記憶されているデータを読出
すＥＰＲＯＭ部と、このＥＰＲＯＭ部へのデータ
書込み及びこのＥＰＲＯＭ部の書込み・読出し制
御を行う書込・制御回路とを有することを特徴と
する不揮発性メモリ。 A plurality of switching memory cells outputting either a first or second logic level are provided, and each address output signal from the address decoder is outputted to the first or second logic level in accordance with the logic level of each switching memory cell.
and an address switching circuit for transmitting data to one of the second output terminals, an address switching setting unit that sets the logic level of each of the switching memory cells, and an address output from the first output terminal of the address switching circuit. a mask ROM section that reads stored data from an address specified by the signal; and a mask ROM section that writes and stores data at an address specified by an address output signal from the second output terminal of the address switching circuit; It has an EPROM section that reads stored data from an address specified by an address output signal from an output terminal, and a write/control circuit that writes data to this EPROM section and controls writing/reading of this EPROM section. Non-volatile memory characterized by:
JP538489U 1989-01-20 1989-01-20 Pending JPH0296699U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP538489U JPH0296699U (en) 1989-01-20 1989-01-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP538489U JPH0296699U (en) 1989-01-20 1989-01-20

Publications (1)

Publication Number Publication Date
JPH0296699U true JPH0296699U (en) 1990-08-01

Family

ID=31208718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP538489U Pending JPH0296699U (en) 1989-01-20 1989-01-20

Country Status (1)

Country Link
JP (1) JPH0296699U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS551607A (en) * 1978-06-16 1980-01-08 Nec Corp Read data correction system of mask read-only memory
JPS6051200A (en) * 1983-05-27 1985-03-22 ルブリゾル　ジエネテイクス　インコーポレイテッド Self-unharmonizing sugar protein
JPS60140596A (en) * 1983-12-27 1985-07-25 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data processor for replacing address

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS551607A (en) * 1978-06-16 1980-01-08 Nec Corp Read data correction system of mask read-only memory
JPS6051200A (en) * 1983-05-27 1985-03-22 ルブリゾル　ジエネテイクス　インコーポレイテッド Self-unharmonizing sugar protein
JPS60140596A (en) * 1983-12-27 1985-07-25 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Data processor for replacing address

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