JPH0294933A - Cmos logic circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing a control circuit to sense that a buffer memory is an empty state and hold the internal state of a time multiplex circuit. CONSTITUTION:Inputted data are respectively stored in buffer memories 20-23, and buffer memory empty state informing signals 30-33 to inform a control circuit 40 of the empty state of the respective buffer memories 20-23 are outputted from the respective buffer memories 20-23. Further, the data read from the respective buffer memories 20-23 are inputted to a time multiplex circuit 60. The control circuit 40 sends a holding instruction signal 41 to hold the internal state (or to stop the circuit operation) of the time multiplex circuit 60 to the time multiplex circuit 60 when the respective buffer memories 20-23 are the empty state, and the time multiplex circuit 60 holds it internal state. Thus, an operating frequency can be substantially lowered, and the power consumption in a high-speed operation can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a CMOS logic circuit, and particularly to a logic circuit that stores signals from a plurality of input ports in a buffer memory, and then time-multiplexes and outputs the signals. Regarding.

[Conventional technology]

The propagation delay time of CMOS logic integrated circuits is becoming smaller year by year due to miniaturization. Using this property, high-speed logic (
For example, 100 Hllz or higher) has become possible to realize with CMOS.

A device for time-multiplexing signals from a plurality of input ports, which is used in a broadband communication device, can also be realized using a CMOS logic circuit.

[Problem to be solved by the invention]

However, CMO8 logic circuits have the property that power consumption increases in proportion to the operating frequency, especially in the high operating frequency region, compared to bipolar high-speed logic circuits whose power consumption is almost constant with frequency. , consumes the same amount of power or more. In other words, in the high operating frequency range, CMOS loses its low power consumption properties, which conventionally appear in communication logic devices, etc.
One way to implement a logic circuit that has a plurality of input ports, temporarily stores signals from the input ports in a buffer memory, and then time-multiplexes them is to cyclically and sequentially read out the outputs of the plurality of buffer memories. In this method, reading and processing of the read signals are performed at a constant frequency, so even if a certain buffer memory is empty, empty data is time-multiplexed. When this circuit is actually implemented using CMOS, it has the disadvantage that power consumption cannot be reduced as described above.

An object of the present invention is to provide a CMOS logic circuit that solves the problems mentioned above.

[Means to solve the problem]

To achieve the above object, the present invention provides a logic circuit comprising a plurality of input ports, a buffer memory circuit provided at the input stage of each input port, and a time multiplexing circuit for selecting and outputting the output of each buffer memory. The apparatus includes a control circuit that senses that the buffer memory is empty and maintains the internal state of the time multiplexing circuit.

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

In the figure, 10 to 13 are input ports, 20 to 23 are buffer memories, 40 is a control circuit, and 60 is a time multiplexing circuit.

Input boat 10. Input boat 11. Data input from input boat 12 and input boat 13 are stored in buffer memories 20-23, respectively. Each buffer memory 20
Buffer memory empty status notification signals 30 to 33 are outputted from buffer memory empty status notification signals 30 to 23 that notify the control circuit 40 of the empty status. Further, the data read from each buffer memory is transmitted through the signal line 50.
53 to the time multiplex circuit 60. The control circuit 40 monitors the empty state from each buffer memory 20 to 30, and when the buffer memory 20 to 30 is empty, sends a hold command signal 4 to hold the internal state of the time multiplexing circuit 60 (or stop the circuit operation).
1 to the time multiplex circuit 60. Upon receiving the hold command signal 41, the time multiplexing circuit 60 holds its internal state.

Next, the principle of operation will be explained with reference to FIG.

In Figure 2, 10 to 13 are each input boat, 20 to 2
3 is a buffer memory, and 60 is a time multiplexing circuit. A control circuit for monitoring the empty state of each buffer memory and maintaining the internal state of the time multiplexing circuit 60 is not shown in the figure.

FIG. 2(a) shows a case where each buffer memory 20-23 contains one or more pieces of data. In this case, the time multiplexing circuit 60 includes the buffer memory 20. Buffer memory 21
．． Buffer memory 22. The signals read from the buffer memory 23 are sequentially output. In this case, the output data of the time multiplexing circuit 60 each have the same time interval.

FIG. 2(b) shows a case where there is data in the buffer memory 20.21 and no data in the buffer memory 22.23. In this case, the time multiplex circuit is a buffer memory 20. The data read from the buffer memory 21 is sequentially output, but since the control circuit issues a hold command signal to the time multiplexing circuit based on the empty status notification signal from the buffer 22.23, a read signal for the buffer memory 22.23 is issued. Regardless of the time, the signal read from the buffer memory 21 continues to be held and output. Therefore, in this case, the operating frequency will actually be reduced.

〔Effect of the invention〕

As explained above, the present invention provides a CMO that has a plurality of input ports, a buffer memory at the input stage of each input port, and a time multiplex circuit that selects and outputs the output of each buffer memory.
In the S logic circuit, by providing a control circuit that knows when the buffer memory is empty and maintains the internal state of the time multiplexing circuit, the operating frequency is substantially lowered and the consumption of the CMO8 logic circuit during high-speed operation is reduced. This has the effect of reducing power consumption.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the present invention. 10 to 13... Input ports 20 to 23... Buffer memory 40... Control circuits 50 to 53... Buffer memory read data signal line 60... Time multiplex circuit Patent applicant NEC Corporation Agent Person Patent attorney Naka Kanno (cL) (b) Figure 2

Claims (1)

[Claims] (1) In a logic circuit that includes a plurality of input ports, a buffer memory circuit provided at the input stage of each input port, and a time multiplexing circuit that selects and outputs the output of each buffer memory, the buffer memory is in an empty state. sense that it is,
A CMOS logic circuit comprising a control circuit that maintains an internal state of a time multiplexing circuit.