JPH0293492A - Video signal processor - Google Patents

Abstract

PURPOSE:To simultaneously display a still picture conforming to the lapse of time and a continuous still picture by providing a recording means for holding plural video signals of a prescribed time at a prescribed interval, and a control means for outputting them successively. CONSTITUTION:Under the control of a system controller 6, image processing circuits 10, 29 record and hold a digital image of a prescribed time portion, it is allowed to pass through D/A converting circuits 12, 31, encoders 14, 33 and a changeover switch 15 at a prescribed interval, and a synchronizing signal and a color burst signal are added to a Y signal and a C signal, respectively by adding circuits 34, 36 and sent to a monitor 37. The monitor 37 divides a screen into small screens D1 - D9, based on the signals Y, C, and by a signal from an A system, a still image conforming to the lapse of time is displayed on D1 - D8, and by a signal from a B system, electronic flash reproduction is executed on D9. By this constitution, video processing signal processor which can display continuously the still screen in addition to a conventional multiple screen display is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing device, and particularly to a video signal processing device suitable for performing multi-screen display.

[Summary of the invention]

The present invention provides a video signal processing device that includes a recording means for holding a plurality of video signals of a predetermined time at predetermined intervals, and a control means for sequentially outputting the video signals from the recording means. Displaying multiple still images over time and continuous still images [Prior art] In conventional video signal processing devices, the screen of a monitor is divided into multiple small screens, for example, nine, and each small screen is There is a so-called multi-screen display function that displays still images for each screen.

Multi-screen display allows still images to be displayed on each small screen over time, and is therefore suitable for, for example, sports form analysis.

[Problem to be solved by the invention]

However, in sports form analysis as well as worker movement analysis, if you do not only view still images at each point in time, but also view them continuously, like strobe playback, - It allows for more effective analysis and often achieves the original purpose more effectively. However, with the multi-screen display function of the conventional video signal processing device as described above, although it is possible to display still images on divided small screens according to the temporal lapse of time, it is possible to display still images and play them with a strobe at the same time. I couldn't do it until now. Furthermore, it was not possible to display a moving image obtained by normal playback at the same time as the above-mentioned still image display.

Therefore, an object of the present invention is to provide a video signal processing device that can continuously display still images in addition to conventional multi-screen display.

[Means to solve the problem]

The video signal processing device according to the present invention includes a recording means for holding a plurality of video signals of a predetermined time period at predetermined intervals, and a control means for sequentially outputting the video signals from the recording means.

[Effect]

The recording means holds video signals for a predetermined time at predetermined intervals, for example, at predetermined time intervals.

A video signal for a predetermined period of time is output from the recording means to the monitor in response to a control signal output from the control means.

The monitor is divided into a plurality of small screens, and video signals are displayed as still images over time on each of the small screens.

At this time, by continuously displaying each still image (strobe playback) on some of the small screens, it is possible to simultaneously display a plurality of still images according to the passage of time and continuously display still images.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows a block diagram of the video signal processing device of this embodiment.

First, in FIG. 1, the blocks of system A will be explained.

Terminal 1 is supplied with a composite color video signal, terminal 2 .
3 is supplied with a Y/C separated video signal. The composite color video signal is Y/C separated in a Y/C separation circuit 4,
A Y (luminance) signal and a C (carrier color) signal are supplied to the changeover switch circuit 5.

On the other hand, the Y signal and C signal of the Y/C separated video signal are directly supplied to the changeover switch circuit 5.

In the changeover switch circuit 5, either the above-mentioned composite color video signal or Y/C separated video signal is selected by a control signal from a system controller 6 (hereinafter referred to as system controller).The selected Y signal is: decoder 7,
The signal is supplied to an A/D conversion circuit 8 and a synchronization signal separation circuit 9, respectively. Further, the selected C signal is supplied to the decoder 7.

In the decoder 7, chroma demodulation is performed based on the Y signal and C signal to form R-Y signal and B-Y signal, and A/'
The signal is supplied to the D conversion circuit 8.

The A/D conversion circuit 8 converts the Y signal, RY signal, and BY signal in synchronization with the clock supplied from the system controller 6, respectively.
A/D conversion is performed into 8-bit digital image data (hereinafter referred to as image data).

This image data is supplied to the image processing circuit 10.

On the other hand, the synchronization signal separation circuit 9 separates vertical and horizontal synchronization signals from the Y signal. This synchronization signal is supplied to the timing forming circuit 11.

The timing forming circuit 11 forms a timing control signal that defines the writing and reading timing of a memory (not shown) in the image processing circuit 1o based on the above-mentioned synchronization signal. This timing control signal is supplied to the image processing circuit 10.

The image processing circuit 10 receives a control signal from the system controller 6 and
According to the timing control signal, 8-bit image data [
Y signal, RY signal, BY signal] are written and held in a memory (not shown) for a predetermined period of time. At the same time, Cisco 6
According to control signals from the camera, image data is thinned out to enable multi-screen display, and the image data is
It is supplied to the A conversion circuit 12. Note that this image processing circuit 10
The timing of reading out the image data from the memory and the timing of outputting the thinned out image data from the image processing circuit 10 are based on a control signal supplied from the system controller 6 in correspondence with the sampling interval described below. It can be set as appropriate. The timing at which image data is output is supplied to the PLL 13.

The D/A conversion circuit 12 converts the image data into analog data again in synchronization with the clock supplied from the system controller 6. This image data is supplied to the encoder 14.

The encoder 14 converts the Y signal, RY signal, and B-Y signal into Y signal and C signal again. The Y signal and C signal are supplied to a changeover switch 15.

On the other hand, the PLL 13 described above extracts a clock from the output timing of image data. This clock is supplied to the synchronization signal generation circuit 16.

Next, the blocks of the B system will be explained.

A composite color video signal is supplied to terminal 21, and terminal 2
2.23 is supplied with a Y/C separated video signal. The composite color video signal is Y/C separated by a Y/C separation circuit 24, and the Y signal and C signal are supplied to a changeover switch circuit 25. On the other hand, the Y signal and C signal of the Y/C separated video signal are directly supplied to the changeover switch circuit 25.

In the changeover switch circuit 25, either the above-mentioned composite color video signal or the Y/C separated video signal is switched to the system controller 6.
Selected by control signals from.

The selected Y signal is sent to the decoder 26 and the A/D conversion circuit 2.
7 and are supplied to the synchronization signal separation circuit 28, respectively. Further, the selected C signal is supplied to the decoder 26.

In the decoder 26, chroma demodulation is performed based on the Y signal and the C signal to form an R-Y signal and a B-Y signal.
The Y signal and the BY signal are supplied to the A/D conversion circuit 27.

The A/D conversion circuit 27 A/D converts the Y signal, RY signal, and BY signal into 8-bit image data in synchronization with the clock supplied from the system controller 6.0 image data is processed by the image processing circuit. 29.

On the other hand, the synchronization signal separation circuit 28 separates vertical and horizontal synchronization signals from the Y signal. This synchronization signal is supplied to the timing forming circuit 30.

The timing forming circuit 30 forms, based on the above-mentioned synchronization signal, a timing control signal that defines the timing of writing and continuous output of a memory (not shown) in the image processing circuit 29. The timing control signal is supplied to the image processing circuit 29.

The image processing circuit 29, like the image processing circuit IO, writes and holds image data in a memory (not shown) for a predetermined period of time. At the same time, according to a control signal from the system controller 6, image data is thinned out and the image data is supplied to the D/A conversion circuit 31.

Note that the timing of reading image data from the memory of the image processing circuit 29 and the timing of outputting the thinned out image data from the image processing circuit 29 are supplied from the system controller 6 in accordance with the sampling interval described later. It can be set appropriately based on the control signal. The timing at which image data is output is supplied to the PLL 32.

The D/A conversion circuit 31 converts the image data into analog data again in synchronization with the clock supplied from the system controller 6. This image data is supplied to the encoder 33.

In the encoder 33, similarly to the encoder 14, the Y signal, the RY signal, and the BY signal are again converted into the Y signal and the C signal. The Y signal and C signal are supplied to the changeover switch 15.

On the other hand, the above-mentioned PLL 32 extracts a clock from the output timing of image data, and supplies this clock to the synchronization signal generation circuit 16.

Various signals are supplied from the keyboard 17 to the system controller 6, and the system controller 6 converts control signals and clocks based on the above-mentioned signals to an A/D conversion circuit 8.27 and a D/A conversion circuit 12.31.
, synchronous signal generation circuit 16, changeover switch circuit 5.25
, the image processing circuit 10.29, the changeover switch 15, etc.

The synchronization signal generation circuit 16 outputs a synchronization signal based on the clock from the system controller 6 and the clock supplied from the PLL 13.32. This synchronization signal is supplied to an addition circuit 34 and a burst signal generation circuit 35, respectively.

The selector switch 15 selects one of the video signals supplied in two systems, A and B, based on a control signal from the system controller 6, and the selected Y signal and C signal are sent to the adder circuit 3.
Supplied at 4.36.

The adder circuit 34 adds the synchronization signal to the Y signal.
The Y signal is supplied to a monitor 37. The addition circuit 36 is
The color burst signal supplied from the burst signal generation circuit 35 is added to the C signal, and the C signal is
7.

The monitor 37, as shown in FIG.
Based on the signal, the entire screen is divided into 9 small screens D1 to D9
Display. Still images are displayed over time on eight small screens DI to D8, and strobe playback is performed on the remaining small screen D9. In this case, still images from small screens D1 to D8 are displayed from the A system block. A video signal for display is supplied, and a video signal for strobe playback is supplied from the B system block to the small screen D9.

Next, multi-screen display of the video signal processing device will be explained with reference to FIGS. 2 to 4. It is assumed that either a composite color video signal or a Y/C separated video signal is supplied.

Fig. 2 shows the keyboard 17, Fig. 3 shows the time length T and interval Is [hereinafter referred to as sampling interval] of the video signal SP to be sampled, and Fig. 4 shows the multi-display and strobe playback. Indicates the state in which the

In FIG. 2, the keyboard 17 is provided with a memory accelerator button 40 (hereinafter referred to as MA button), a replay button 41, and a time controller 42. Note that 43 indicates other control buttons.

During normal playback of the video signal on the monitor 37, the MA button 40 is pressed when the user wishes to view an image, such as a golf swing, in more detail. At the same time, the sampling interval Is shown in FIG.
) to the desired value between 4.2 seconds and 4.2 seconds. This sampling interval Is is set by operating the time controller 42 in the direction of the arrow in FIG.

The MA button 40 outputs a signal corresponding to the selected sampling interval Is to the system controller 6. From the system controller 6, control signals and clocks corresponding to the above-mentioned signals are sent to an A/D conversion circuit 8.27, an image processing circuit 10.29,
It is output to the D/A conversion circuit 12.31, the synchronization signal generation circuit 16, the changeover switch 15, etc.

In the image processing circuit 1O129, based on the control signal from the system controller 6 and the timing control signal, digital image data for (1/30) seconds up to time tO-El shown in FIG. , B-Y signal] is recorded and held in a memory (not shown).

Note that the image processing circuit 10 not only holds this image data as described above, but also outputs it to the D/A conversion circuit X2 at a timing corresponding to the sampling interval !S.

The above-mentioned Y signal, R-Y signal, B-Y signal, etc. pass through the D/A conversion circuit 12, are converted into Y signals and C signals by the encoder 14, and are sent to the adder circuit 34 via the changeover switch 15.
．． 36.

The adder circuit 34 adds a synchronization signal to the Y signal, and the adder circuit 36 adds a color burst signal to the C signal.

The Y signal and C signal are each supplied to a monitor 37.

As a result, as shown in FIG. 4A, a still image P of the first sampled frame Fl is displayed on the small screen D1.
1 is displayed.

Next, at time t2 after a predetermined sampling interval Is has elapsed, the system controller 6 outputs a control signal in the same manner as during the first sampling. As a result, the image processing circuit 10 retains the image data of the still image P2 of the second sampled frame F2 in the memory of the image processing circuit 10.29.
image data is output at a timing corresponding to the sampling interval Is, and a still image P2 of frame F2 is displayed on the small screen D2.

Hereinafter, in the same manner, the predetermined sampling interval Is
The image data up to the eighth frame F8 is held in the memory of the image processing circuit 10129. Furthermore, since the image data up to frame F8 is sequentially output from the image processing circuit 10 at a timing corresponding to the sampling interval IS, still images P1 to P8 of frames F1 to F8 are displayed on the small screens D1 to D8, respectively. Still image P1~
The display order of P8 is the order indicated by the arrow in FIG. 4A. and a predetermined sampling interval I
At step s, the image data up to the ninth frame F9 is held in the memory of the image processing circuit 10.29. Furthermore, time t
From O to t15, that is, frame F1 on small screens D1 to D8
While the still image is being displayed at ~F8, the moving image PO that is normally reproduced is displayed on the small screen D9.

When the replay button 41 is pressed after time t16, the corresponding control signal is sent from the system controller 6 to the image processing circuit 2.
9. Output to the changeover switch 15 etc. and output to the image processing circuit 2
Image data is read from memory No. 9. That is, at the timing when the image data of the first to ninth frames Fl-F9 correspond to the sampling interval Is,
Read out sequentially. This image data is sequentially output to the D/A conversion circuit 31 after being thinned out to reduce the still images P1 to P9 to a size corresponding to the small screen D9. The above image data is transmitted to the D/A conversion circuit 31 and the encoder 3.
3. The signal is supplied to the monitor 37 via the selector switch 15 and the adder circuits 34 and 36.

As a result, the first to ninth frames F1 to F are displayed on the small screen D9 of the monitor 37, as shown in FIG. 4C.
Strobe reproduction of still images P1 to P9 of No. 9 is performed. That is, still images P1 to P9 are continuously displayed at each predetermined sampling interval Is.

As shown in FIG. 4C, the still images P1 to P8 of the sampled frames Fl-FB are displayed on the small screens D1 to D8 as time passes, and the still images P1 to P8 of the sampled frames Fl-FB are displayed on the small screen D9. Still image display of the ninth to ninth frames Fl-F9 is continuously performed at predetermined display intervals, and strobe playback is performed.

Here, when the MA button 40 is pressed, the image processing circuit 10.2
The image data in memory No. 9 is overwritten and the above steps are repeated again for another video signal.

Furthermore, when it is desired to change the display interval of strobe playback on the small screen D9, the desired display interval can be set by operating the time controller 42 before pressing the replay button 41.

Although this embodiment is explained using a video signal as an example, the present invention is not limited to this, and can be similarly applied to a television signal.

Furthermore, in this embodiment, an example is described in which the A system block outputs a video signal for displaying a still image, and the B system block outputs a video signal for strobe playback/display. , B. The functions of the blocks in both systems can also be interchanged.

〔Effect of the invention〕

The video signal processing device of the present invention stores a plurality of video signals of a predetermined time period in the recording means at predetermined intervals, and sequentially outputs the video signals using a control signal from the control means. This has the effect of simultaneously displaying a plurality of still images and continuously displaying still images (stroboscopic playback).

According to the embodiment, still images of each frame can be displayed on the eight small screens, still images of each frame can be displayed continuously on the central small screen, and strobe playback can be performed at any speed. Furthermore, the eight small screens can display still images of each sampled frame, and the central small screen can display moving images obtained during normal playback.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a schematic explanatory diagram of a keyboard, Fig. 3 is a route map showing sampling frame intervals, and Fig. 4 is a multi-screen display and strobe playback, respectively. FIG. Explanation of main symbols in the drawings 6: System controller, 10, 29: Image processing circuit, T: Time length, ■S: Sampling interval.

Claims (1)

[Scope of Claims] Video signal processing characterized by comprising a recording means for holding a plurality of video signals of a predetermined time at predetermined intervals, and a control means for sequentially outputting the video signals from the recording means. Device.