JPH029272A - Encoding device - Google Patents

Abstract

PURPOSE:To form an EOL signal with respect to a picture having various lengths without using a counter of an EOL generation picture by forming an EOL signal based on the DMA end by one line of the picture data to be encoded. CONSTITUTION:When the final word of one line of transfer word by one line set in advance is subject to DAM transfer, a DMA controller 11 sets a TC signal in addition to a DACK signal and a WR signal. Thus, when the changeover device 7 is switched to the position of the EOL and a data request signal PDR is sent from a parallel/serial converter 1, the EOL signal is set. When a CPU 10 detects it that the EOL signal is set, the EOL code is written in a transmission buffer area in the memory 12 to complete one line encoding. Thus, without a counter counting bit number subject to run length, or without counting the bit number by the software, the end of line is detected.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an encoding device that encodes image data.

[Conventional technology]

Conventionally, the run length was generated using hardware, and the MH
When encoding into code or MR code, count the number of bits of image data converted into run length for each main scanning line,
This bit number is the number of bits for one line (172 for A4 size)
8), a line end code (abbreviated as EOL code) was output. Therefore, it was necessary to count the number of run-length bits using a hardware counter or software.

In addition, in the encoding of conventional facsimile machines, CCD
The output analog signal is subjected to shading correction two-image processing and binarization processing in a binarization circuit, and is stored in a line buffer which is a serial memory. and,
The image signals accumulated in the line buffer are sent to a run-length counter as needed and converted into run-lengths, which are read by the CPU and subjected to MH and MR encoding.

[Problem that the invention is trying to solve] However,
In the conventional example above, when counting with a hardware counter, the number of bits in the main scanning direction varies depending on the document (A4: 1728 B4: 2048 A3
: 2560), a counter that can handle this would be complex and large-scale. Furthermore, counting by software slows down the encoding process, and as a result, a CPU with high processing power is required, leading to an increase in cost.

Further, a special serial memory is required as a line buffer, and a control circuit is also required when a general-purpose memory is used. With the recent increase in the capacity of general-purpose memory, the price per bit has fallen rapidly, and it is common to have a large-capacity memory as the main memory. However, having a separate dedicated memory with a high bit unit price as in the past is disadvantageous in terms of cost and space.

[Means for solving problems]

The present invention has been made in view of the above points, and includes a memory that stores image data, a parallel-serial converter that converts parallel image data into serial image data, and outputs a next parallel data request signal when the conversion is completed. , a run-length conversion circuit for converting serial image data into run lengths, and a DM (direct memory access) for transferring image data from the memory to the parallel-to-serial converter according to a request of the parallel-to-serial converter.
A controller, and the DMA controller has 1
The present invention provides an encoding device that forms an EnL signal based on a data request signal from the parallel-to-serial converter after generation of a signal output during transfer of the final word of a line.

It also includes a means for outputting binary image data obtained by reading a document to a system bus, a memory for storing the image data via the system bus, and a means for inputting image data from the memory via the system bus. a run-length conversion circuit that converts the image data into a run-length, stores the read image data in the memory connected to the system bus, transfers it from the memory to the run-length conversion circuit, and encodes the image data into a run-length. It provides equipment.

〔Example〕

The present invention will be explained below using preferred embodiments.

FIG. 2 is a diagram showing the configuration of a facsimile to which the present invention is applied. In FIG. 2, 10 is a CPU that controls the entire facsimile and encodes and decodes image data;
12 is a DMA controller that controls DMA transfer, and 12 is a buffer for image data storage, sending and receiving data, and CPU10.
13 is a run-length conversion circuit that converts parallel image data into a run-length, 14 is a system bus, and 15 is a C that reads a transmission document.
CD, 16 performs shading correction 2 image processing on the image signal from CCD 15.

A binarization circuit that performs processing such as binarization, 17 is a binarization circuit 1
This is a serial-to-parallel conversion circuit that converts serial image data from 6 to parallel data.

In the above configuration, the output of the CCD 15 is output from the binarization circuit 16.
The data is binarized and converted into parallel data by a serial-parallel conversion circuit 17. This parallel data is DMA-transferred to the line buffer area of the main memory 12 under the control of the DMA controller 11. When the CPU 10 activates the run-length conversion circuit 13, the run-length conversion circuit 13 issues a DMA transfer request DRQ to the DMA controller 11. The DMA controller 11 transfers the image data in the main memory 12 to the run length conversion circuit 13 in response to a request. The image data converted into run length is sent to CPUIO, and CPUIO performs MH encoding or MR encoding operation.

FIG. 1 is a diagram showing the configuration of the run-length conversion circuit 13. In the figure, 1 indicates the number of consecutive white and black images of the parallel serial image data from the memory 12 and the run-length conversion circuit 13. 3 is a 3-state buffer that outputs the counter value, which is the output of run-length counter 2, to the system bus 14 by the RD (read) signal from CPU10; 4 is a 3-state buffer in the run-length conversion circuit 13; Internal bus, 5 is an AND gate, 6 is a D-F for storing TC signal pulses, F (flip-flop), 7 is a parallel data request PDR of the parallel-to-serial converter l as DRQ (DMA request signal), or EOL. 8 is a delay circuit.

The encoding operation for one line in the above configuration will be explained along the flowchart of FIG. First, CPU10 in Sl
programs the number of words to be transferred for one line in the DMA controller 11 and permits DMA transfer.

Note that this number of transferred words is the image size to be encoded.

Determined by resolution, etc. Next, at 82, the run length conversion circuit 13 is activated. As a result, the parallel-serial converter 1 issues a data request PDR, and at this time, since the changeover switch 7 is on the DRQ side, a data request signal DRQ is issued to the DMA controller 11. DM
When the A controller 11 receives the DRQ, it stops the CPU l0, gains control of the bus 14, puts the memory 12 in the output state, and at the same time turns on the WR double signal D A CK signal to transfer the memory 12 to the parallel serial converter l. Writes the first image data word from.

When the image data word is written, the parallel-to-serial converter 1 turns off the data request PDR and outputs serial data to the run length counter 2 at the same time. When the parallel-to-serial conversion is completed, the parallel-to-serial converter 1 issues the DRQ again, and the process is repeated. At this time, CPU ], O outputs the RD multiplied signal C8 signal and
Enable state buffer 3 and connect RDY signal and E
The OL signal is read and checked. In the flowchart, S3. Looping S5.

When the image data from the parallel/serial converter changes from white to black or from black to white, the run length counter 2 outputs the RDY signal, so the process advances to S4 and the C
PU10 reads the run length from the 3-state buffer 3, encodes it into an MH code or MR code, and writes it into the transmission buffer memory area in the memory 12. Then S3 until the next run length is created. Return to the loop of S5. Thereafter, encoding is performed in S4 every time a run length occurs.

When the encoding progresses and the final word of one line of one line of transfer words preset in Sl is DMA transferred, the DMA controller 11 transmits the D A CK signal and the WR
Add the double signal and turn on the TC signal. As a result, D-
F and F6 are set, and the switch 7 is switched to the EOL side. After this, when the parallel-to-serial conversion is completed and the parallel-to-serial converter 1 outputs the data request signal PDR, the switch 7 causes the DRQ signal to be output without outputting the EO signal.
The L signal turns ON. When the CPU 10 detects that the EOL signal is turned ON in S5, it writes the EOL code into the transmission buffer area in the memory 12 in S6, thereby completing the encoding of one line.

Note that the transfer from the serial-parallel conversion circuit 17 to the memory 12 and the transfer from the memory I2 to the run-length conversion circuit 13 can also be performed by the CPU 10 by interrupt processing.

As explained above, the DMA controller 11
E
By using the OL signal, the end of the line can be detected without a counter for counting the number of run-length bits or without counting the number of bits using software.

Note that this embodiment has been explained using a facsimile machine as an example.
It goes without saying that the present invention is not limited to this, and can also be applied to other devices that use encoding that requires EOL generation, such as image file devices.

〔effect〕

As explained above, according to the present invention, by forming an EOL signal based on the completion of DMA for one line of image data to be encoded, various types of signals can be generated without using an image counter etc. for EOL generation. EOL for length images
It becomes possible to form a signal.

In addition, by storing the image signal in the memory of the CDU and sending the image data once again from this memory to the run-length counter, a part of the CPU memory can be used as a line buffer, and a dedicated line buffer can be used. Memory is no longer needed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a run-length conversion circuit according to the present invention, FIG. 2 is a block diagram of a facsimile machine, and FIG. 3 is a flow chart showing one line encoding operation. l... Parallel serial converter 2... Lanre:/Guess counter 3... 3-state buffer 6... D-F, F 7... Changeover switch 10... CP LT 11... DMA controller 12...Memory]3...Run length conversion circuit

Claims (2)

[Claims] (1) A memory that stores image data, a parallel-to-serial converter that converts parallel image data to serial image data and outputs the next parallel data request signal when the conversion is completed, and a run that converts serial image data to run length. a length conversion circuit; and a DMA controller that transfers image data from the memory to the parallel-serial converter by DMA (direct memory access) according to a request from the parallel-serial converter, and the DMA controller controls the final word of one line. An encoding device forming an EOL signal based on a data request signal of the parallel-to-serial converter after generation of a signal output during transfer. (2) means for outputting binary image data obtained by reading a document to a system bus; and storage means for storing the image data in a memory of a CPU via the system bus;
a run-length conversion circuit that inputs image data from the memory via a system bus and converts it into a run length; stores the read image data in the memory of the CPU connected to the system bus; An encoding device characterized in that data is transferred from a memory to the run-length conversion circuit and converted into a run-length.