JP3159483B2 - Image compression coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image compression encoding apparatus for compressing and encoding bitmap data output from a scanner in a facsimile apparatus at a high speed.
In particular, the present invention relates to an image compression encoding apparatus suitable for encoding large-capacity bitmap data at high speed.

[0002]

2. Description of the Related Art Conventionally, in a facsimile apparatus or the like, bitmap data from a scanner is converted to MH (modifi
A compression / decompression processor (hereinafter, referred to as CEP) is used to convert the data into compressed coded data such as ed Huffman code) and MR (modified READ code). In this case, the bitmap data from the scanner is input at a constant speed, but the output speed of the compression-encoded data from the CEP varies depending on the density of the image, and is usually lower than the data output speed from the scanner. is there. For this reason, the conventional image compression encoding apparatus is provided with an input buffer for temporarily storing bitmap data from the scanner.

[0003]

However, in the above-described conventional image compression encoding apparatus, when compressing and encoding large-capacity bitmap data such as A0 and A1 sizes, for example, a large-capacity data exceeding 30 MB is used as an input buffer. However, there is a problem that a bit telemap memory is required. In addition, since CEPs conventionally marketed assume image data from a scanner as input data,
The format of the input data to the CEP must be bitmap data. For this reason, even if the bitmap data input from the scanner is once converted to the run-length data, it must be converted from the run-length data to the bitmap data again, resulting in a problem that the processing and the circuit become complicated. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides an image compression encoding apparatus capable of reducing a buffer capacity and simplifying a process and a circuit. With the goal.

[0005]

According to the present invention, there is provided an image compression / encoding apparatus which converts bitmap data output from a scanner into run-length data sequentially, and a run-length converting means which converts the bitmap data into run-length data. A buffer circuit for sequentially storing the run-length data, and run-length / compression code conversion means for sequentially compression-encoding the run-length data given via the buffer circuit, wherein the run-length / compression code conversion means A code conversion table for converting run-length data into a compression-encoding pattern, and address generating means for generating an address for accessing the code conversion table based on the given run-length data.
And the code conversion table stores run-length data.
A table to convert to Modified Huffman code
The output is the makeup code and the terminating
Code, the number of coding bits, and the code
Coding pattern and the run layer corresponding to this coding pattern.
Address generating means,
The identification code output from the code conversion table is
The terminating code
From the given run-length data, the coding pattern
By sequentially subtracting the run lengths corresponding to
Characterized in der Rukoto which generates an address of the serial code conversion table.

[0006]

According to the present invention, the bitmap data supplied from the scanner is once compressed into run-length data by the run-length conversion means, and the subsequent processing is performed. Therefore, a large-capacity buffer is required. And never. In addition, according to the present invention, since data transfer within the device is performed in units of run length, the frequency of data transfer is lower than in the case of transferring bitmap data. Therefore, by transferring data in accordance with the processing capacity of the run-length / compression code conversion means, processing efficiency can be improved and high-speed processing can be performed.
Further, according to the present invention, since a compression code can be directly obtained by a table look-up method without first converting run-length data to bitmap data, run-length / bitmap conversion processing becomes unnecessary. In addition, the circuit of the conversion unit can be greatly simplified.

When a code conversion table of the MH code is provided as the run length / compression code conversion means, if the run length of the coding pattern output from the table is included as a table output, the next access is performed. The generation of the address to be performed becomes easy.

[0008]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an image compression encoding apparatus of a facsimile apparatus.

Scanner data in a bitmap format output from an image scanner including a contact type line image sensor and the like is sequentially input to a run length conversion circuit 1. The run-length conversion circuit 1 converts input scanner data into run-length data. The output of the run length conversion circuit 1 is a FIFO (First in First ou
t) The data is sequentially stored in the memory 2. FI
The output side of the FO memory 2 is connected to the CPU bus 3.

[0010] The CPU bus 3 includes a CPU 4 and a DR.
The AM buffer 5 is connected. The CPU 4 controls the overall operation of the apparatus, reads the run-length data stored in the FIFO memory 2 as appropriate, and sequentially stores the read run-length data in the DRAM buffer 6. A run length / compression code conversion circuit 6 is connected to the CPU bus 3. The run-length / compression code conversion circuit 6 converts the run-length data sequentially read from the DRAM buffer 5 under the control of the CPU 4 into compression-coded data such as MH, MR, and MMR, and sequentially stores the data in the DRAM buffer 5. Store. The CPU bus 3 has a SCSI interface circuit 7
Is connected, and transmits the compressed and coded data stored in the DRAM buffer 5 to a host computer (not shown) under the control of the CPU 4.

As shown in FIG. 2, the run-length / compression code conversion circuit 6 includes a code conversion table 21, a reference line data storage unit 22, a data operation circuit 23, an address generation unit 24, and an internal address for interconnecting these. It comprises a bus 25 and an internal data bus 26. The code conversion table 21 is a table for converting run-length data into MH codes. The reference line data storage unit 22 is configured by an SRAM that stores a reference line when performing MR and MMR encoding. In addition, the data operation unit 23 operates data output from the code conversion table 21 to generate 16-bit output data, and performs operations necessary for address generation. Also,
The address generator 24 generates an address to be given to the code conversion table 21.

Next, the operation of this system will be described. First, prior to a description of the operation of the system, an outline of MH, MR, and MMR codes generated from run-length data will be described.

(1) MH Code In the MH coding method, data of all scan lines is one-dimensionally coded. As shown in FIG. 3, the encoded data of one line is composed of an EOL (End of Line) code added to the head and a data code following the EOL (End of Line) code. After the last line of one page, an RTC consisting of six consecutive EOL codes
A sign is added. The EOL code is a 12-bit code represented by “000000000001”. Also, as shown in FIG. 3, when the number of code bits in one line is shorter than a predetermined bit length T, a fill bit ( Variable length 0) is added. The data code is composed of a variable length code representing a white or black run length. When the run length is 63 or less, the data code is represented by only one terminating code shown in FIG. 4, and when the run length is 64 or more, one or a plurality of data codes shown in FIGS. It is represented by a combination of a make-up code and one terminating code.

(2) MR Code In the MR encoding method, one scanning line is one-dimensionally encoded, and then two to four continuous scanning lines are two-dimensionally encoded. In the two-dimensional encoding process, a line immediately before an encoding line currently being encoded is referred to, and a positional relationship between a reference line and a changed pixel (a pixel that changes from black to white or white to black) of the encoding line is encoded. Become That is, as shown in FIG. 7, a0, a0 ', a1, a2, b1, and b2 are determined as follows.

A0; a pixel which becomes a starting point on the coding line a0 '; a pixel which becomes a0 in the next coding process a1; a first changed pixel having a color opposite to a0 on the reference line to the right of a0, a2 The first changed pixel b1 to the right of a0 on the coding line; the first changed pixel b2 to the right of a1 on the reference line; the first changed pixel to the right of a2 on the coding line; Sets the following three modes.

Pass Mode As shown in FIG. 7A, when a2 is on the right side of b1, the pass mode is set. In this case, as shown in FIG.
It is encoded as "0001".

Vertical mode As shown in FIG. 7B, the relative distance | a1 between a1 and a2
When a2 | is 3 or less, the mode is the vertical mode. In this case, V1 shown in FIG.
(0), VR (1), VR (2), VR (3), VL
It is encoded into seven codes of (1), VL (2), and VL (3). In VR (n), a2 is on the right side of a1 and VL (n)
Means that a2 is on the left side of a1, and parentheses indicate relative distances.

Horizontal mode As shown in FIG. 7C, the relative distance | a1 between a1 and a2
When a2 | is 4 or more, the horizontal mode is set. In this case, as shown in FIG. 8, the length of a0a2 is
It is coded to a value obtained by combining the H-coded data and the MH-coded data of the length of a2b2. In MR encoding, one-dimensional encoding and two-dimensional encoding are mixed, so
A tag bit is provided immediately after the EOL code to identify whether the subsequent data is one-dimensionally encoded or two-dimensionally encoded.

(3) MMR Code In the MMR coding method, all scan lines are two-dimensionally coded. When encoding the first line, a virtual all-white line is set as a reference line. On the last line of one page, two EOL codes are successively added as RTC codes, and then an adjustment bit (0) is added so that the number of bits of code data for one page is in 8-bit units. Add.

Next, the operation of the present system will be described.
Scanner data in a bitmap format output from an image scanner not shown in FIG. 1 is converted by a run-length conversion circuit 1 into, for example, 32-bit run-length data RL. Examples of the form of the run-length data RL include a form including a start point position and a run length, and a form including a start point position and an end point position. For example, in the case of bitmap data as shown in FIG.
The form shown in FIG. 10A is the form shown in FIG. 10B, and the latter form may be any form.

The output of the run length conversion circuit 1 is
It is stored in the IFO memory 2. When a predetermined amount of run-length data RL is stored in the FIFO memory 2, the FIFO
For example, a half-full status signal or the like is output from the memory 2, and the CPU 4 sees such a status signal and reads the run-length data RL from the FIFO memory 2.
Is read and stored in the DRAM buffer 5.

Next, the run length / compression code conversion circuit 6
Sequentially reads the run-length data RL stored in the DRAM buffer 5 and performs any one of MH, MR, and MMR encoding processing.

(1) Run Length → MH Coding FIG. 16 is a flowchart showing a process of converting the run length data RL to the MH code. First, an EOL code is generated by the EOL code processing (S1). continue,
The run-length data RL is read from the DRAM buffer 5 (S2), and as shown in FIG. 11, run-length data including a flag indicating white / black and a run length is calculated. . If the run length data is composed of data indicating the positions of the start point and the end point, the run length is calculated by subtracting the start point position from the end point position (S3).

Next, an address for accessing the code conversion table 21 is generated by the address generator 24 from the obtained run-length data (S4). The address is
For example, as shown in FIG. 12, the code conversion table 21 includes a fixed address indicating an area in which the RL / MH conversion code is stored, a white / black discrimination flag, and a lower address Y. That is, in the address generation unit 24, FIG.
As shown in (2), the run length to be encoded is compared with 2560 by a comparison circuit 31. If the run length exceeds 2560, 2560 is selected by the selection circuit 32 and the run length is 2560 or less. , The selection circuit 32 selects the run-length data RL. The address ADR is generated by combining the selection result Y, the fixed address, and the black / white determination flag by the address configuration circuit 33.

The address ADR generated by the address generator 24 is provided to the code conversion table 21 via the internal address bus 25. As a result, the code data CDA is read from the code conversion table 21 (S
5). As shown in FIG. 13, the code data CDA has an identification code I of a makeup code / terminating code.
, A coding length e of the variable length coding pattern, a coding pattern C, and a run length d indicated by the coding pattern C.

The code data CDA read from the code conversion table 21 is input to the data operation circuit 23 via the internal data bus 26. Data operation circuit 23
Is configured, for example, as shown in FIG. The coding pattern C is set in the shift register 41, and the coding bit number e is set in the counter. Since the MH conversion code is a variable-length code, data is packed in the shift register 43 while shifting the encoding pattern set in the shift register 41 bit by bit in order to unify the number of bits at the time of code output. S6) When 16-bit data is accumulated in the shift register 43 (when the output dc of the counter 44 becomes 16), the MH data code is written into the DRAM buffer 5 in 16-bit units (S6).
7, S8).

On the other hand, if the number of coded bits e becomes 0 in the course of this shift operation (S9), the identification code I of the makeup code and the terminating code is determined (S1).
0). If the identification code I indicates the terminating code, the next run-length data RL is read (S2), and the same processing is executed for the run-length data (S3 to S10). When the identification code I indicates a make-up code, the run length d obtained this time is subtracted by the subtractor 45 from the given run length data RL or the run length d obtained by the immediately preceding code read. This is output as the run length d to be encoded next (S3). This run length d is also supplied to the comparison circuit 31 in FIG. 14 and is used for generating the next address. Thereby, there is an advantage that generation of an address to be accessed next becomes easy. This process is repeated until the identification code I indicates the terminating code.

When the processing for one line is completed, the processing of steps S1 to S10 is executed for the next line (S10).
11, S12). When processing for one page is completed, RT
A C code is generated (S13). Through the above operation, the run-length data RL can be one-dimensionally encoded.

(2) Run Length → MR Coding FIGS. 17 and 18 show the case where the run length data RL to MH
It is a flowchart which shows the conversion process to a code. First,
Whether the run-length data is one-dimensionally encoded or two-dimensionally encoded is determined based on whether the data is the data of the first line (S21). At this time, the data of the line to be referred to is simultaneously written in the reference line data storage unit 22 composed of the SRAM.

When performing one-dimensional encoding (S22), the same processing as the MH encoding processing described above is executed (S23).
To S33). At this time, in the EOL code processing (S23), “1” is added as a tag bit immediately after the EOL code. When performing two-dimensional encoding (S22), “0” is added as a tag bit immediately after the EOL code in the EOL code processing (S41). Subsequently, the data of the reference line is read from the reference line data storage unit 22 (S4).
2) Read the run-length data RL of the encoding line to be converted from the DRAM buffer 5 (S43). Then, a run-length / two-dimensional code conversion process is executed (S44).

FIG. 20 is a flowchart showing details of the run-length / two-dimensional code conversion process. First, noticeable pixels a0, a1, a of the reference line and the encoding line
The pass mode, the vertical mode, and the horizontal mode are discriminated from the mutual positional relationship between S2, b1, and b2 (S6).
1). Based on this determination result, the data operation circuit 23 sets the two-dimensional code shown in FIG. 8 in the shift register 41 shown in FIG. 15 (S62). Like the MH encoding, the MR conversion code is also a variable length code, so that the data is shifted (S71) and the MR code is written to the DRAM buffer 5 by 16 bits in order to unify the number of bits at output to 16 bits. (S64, S65). On the other hand, if the number of encoded bits e becomes 0 in the course of this shift operation,
If the current mode is not the horizontal mode, the run-length / two-dimensional encoding conversion process ends (S66, S6).
7). If the current mode is the horizontal mode, the data arithmetic circuit 23 calculates the run length between a0 and a1, and executes the MH encoding process described above (S68 to S68).
S75). The same MH encoding process is executed for the run length between a1 and a2 (S77).

When the processing for one line is completed, the processing of steps S42 to S44 is executed for the next line (S45). When the processing for one page is completed, an RTC code is generated (S47). Through the above operation, the run-length data RL can be MR-encoded.

(3) Run Length → MMR Encoding FIG. 19 is a flowchart showing a process of converting the run length data RL into the MMR code. In the case of the MMR encoding, only the part of the two-dimensional conversion processing in the MR encoding processing is performed (S51 to S58), and thus the details thereof are omitted.

The compression encoded data stored in the DRAM buffer 5 is sequentially read out by the CPU 4 and transferred to a host computer or the like via the SCSI interface 7.

As described above, according to the apparatus of this embodiment, the bitmap data supplied from the scanner is once compressed into run-length data by the run-length conversion circuit 1, and then the subsequent processing is performed. From, FIF
It does not require a large-capacity O-buffer 2 and
Since the DRAM buffer 5 also only stores run-length data and compression code data, a large capacity is not required. Therefore, it is possible to sufficiently cope with A0 and A1 size drawings. Moreover, in the present apparatus, since data is transferred in run-length units, the data transfer frequency is lower than in the case of transferring bitmap data. For this reason, the load on the CPU 4 is greatly reduced.

Further, according to the apparatus of this embodiment, since the run-length data is directly converted into MH, MR, and MMR codes, a conventional compression / decompression processor which accepts only bitmap data is used. In comparison with the above, the conversion process can be omitted by one step, the process can be simplified, and the circuit configuration can be simplified.

The present invention is not limited to the embodiment described above. In the above embodiment, the converted compressed code data is written to the DRAM buffer 5.
The compression code data output from the run-length / compression code conversion circuit 6 may be stored in a FIFO buffer, or may be sequentially output to the outside via an interface circuit.

[0038]

As described above, according to the present invention, the bitmap data supplied from the scanner is compressed into run-length data, buffered, and the subsequent processing is performed. There is no need for a large buffer. Moreover, according to the present invention, the buffering is performed in units of run length, so that the data transfer frequency is lower than in the case of transferring bitmap data. For this reason, data can be transferred in accordance with the processing capacity of the run-length / compression code conversion means, and the processing efficiency is improved to enable high-speed processing.

Further, according to the present invention, the compression code can be directly obtained by the table look-up method without temporarily converting the run-length data into bitmap data, so that the run-length / bitmap conversion processing is unnecessary. Therefore, the circuit of the processing and conversion unit can be greatly simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an image compression encoding apparatus of a facsimile apparatus.

FIG. 2 is a block diagram showing a more detailed configuration of a run-length / compression code conversion circuit in the device.

FIG. 3 is a diagram showing a data format of the MH encoding method.

FIG. 4 is a diagram showing a terminating code in the MH encoding method.

FIG. 5 is a diagram illustrating a make-up code in the MH coding method.

FIG. 6 is a diagram showing a make-up code in the MH coding method.

FIG. 7 is a diagram for explaining three modes in the MR encoding method.

FIG. 8 is a diagram showing a conversion code in the MR encoding method.

FIG. 9 is a diagram illustrating an example of image data from a scanner.

FIG. 10 is a diagram showing run-length data converted from the image data.

FIG. 11 is a diagram showing run lengths calculated from the run length data.

FIG. 12 is a diagram showing a format of an address generated by an address generator of FIG. 2;

FIG. 13 is a diagram showing a format of code data output from the code conversion table of FIG. 2;

FIG. 14 is a block diagram showing a main configuration of the address generation unit.

FIG. 15 is a block diagram showing a configuration of a part of the data operation circuit of FIG. 2;

FIG. 16 is a flowchart showing a run-length / MH code conversion procedure.

FIG. 17 is a flowchart showing the first half of a run-length / MR code conversion procedure.

FIG. 18 is a flowchart showing the latter half of the run-length / MR code conversion procedure.

FIG. 19 is a flowchart showing a run-length / MMR code conversion procedure.

FIG. 20 shows run lengths in FIGS. 17 and 19;
It is a flowchart which shows the detail of a two-dimensional code conversion process.

[Explanation of symbols]

1. Run length conversion circuit 2. FIFO memory 3.
CPU bus, 4 CPU, 5 DRAM buffer, 6 CPU
Run length / compression code conversion circuit, 7 SCSI interface, 21 code conversion table, 22 reference line data storage unit, 23 data operation circuit, 24 address generation unit, 25 internal address bus, 26 internal data bus .

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/41-1/419 G06T 9/00 H03M 7/46-7/48

Claims (3)

(57) [Claims] 1. A run-length converting means for sequentially converting bitmap data output from a scanner into run-length data; a buffer circuit for sequentially storing the run-length data converted by the run-length converting means; Run-length / compression code conversion means for sequentially compressing and encoding run-length data given via the CPU, wherein the run-length / compression code conversion means converts the run-length data into a compression coding pattern. If, der that and an address generating means for generating an address for accessing said code conversion table on the basis of the run given length data is, the code conversion table, the run-length data model
Is a table to be converted into a modified Huffman code,
Its output is the makeup code and the terminating code.
Code, the number of coded bits,
The pattern and the run length corresponding to this encoded pattern
And the address generating means is configured to read the address from the code conversion table.
The output identification code is the terminating code.
Until it shows the run-length
The run length corresponding to the coding pattern from the data
By sequentially subtracting, the code conversion table
Image compression coding apparatus according to claim der Rukoto thereby generating a dress. 2. A method according to claim 1 Symbol placement picture compression encoding apparatus and further comprising a memory for sequentially storing the run length data stored in the buffer circuit. 3. The image compression encoding apparatus according to claim 2 , wherein said memory stores compressed data converted by said run-length / compression code conversion means sequentially.