JPH0541808A - Picture compression encoder - Google Patents

Abstract

PURPOSE:To realize the picture compression encoder in which the buffer capacity is saved and the picture and the circuit are simplified. CONSTITUTION:Scanner data of bit map form outputted from a picture scanner is given to a run length conversion circuit 1, in which the data is converted into run length data. An output of the run length conversion circuit 1 is sequentially stored in an FIFO memory 2. A CPU 4 reads a run length data stored in the FIFO memory 2 properly and stores the data to a DRAM buffer 5. A run length compression code conversion circuit 6 converts the run length data read sequentially from the DRAM buffer 5 into compression coding data such as MH, MR and MMR under the control of the CPU 4 and stores the result sequentially to the DRAM buffer 5. The compression coding data stored in the DRAM buffer 5 is sent to a host computer (not shown in figure) via an SCSI I/F7 under the control of the CPU 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image compression coding apparatus for compressing bit map data output from a scanner at high speed in a facsimile machine or the like,
In particular, the present invention relates to an image compression encoding device suitable for high-speed encoding of large-capacity bitmap data.

[0002]

2. Description of the Related Art Conventionally, in a facsimile apparatus or the like, bitmap data from a scanner is converted into MH (modifi).
A compression / expansion processor (hereinafter, referred to as CEP) is used to convert compression-encoded data such as ed Huffman code) and MR (modified READ code). In this case, the bitmap data from the scanner is input at a constant speed, but the output speed of the compression-encoded data from the CEP differs depending on the density of the image, and is usually lower than the data output speed from the scanner. is there. Therefore, the conventional image compression encoding device is provided with an input buffer for temporarily storing the bitmap data from the scanner.

[0003]

However, in the above-mentioned conventional image compression encoding apparatus, when compression encoding large-capacity bitmap data such as A0 and A1 sizes, a large capacity exceeding 30 MB is used as an input buffer. There is a problem that the bit temap memory of is required. In addition, since the CEP that is commercially available in the past assumes image data from the scanner as input data,
The form of input data to the CEP must be bitmap data. Therefore, even if the bit map data input from the scanner is once converted into the run length data, the run length data must be converted into the bit map data again, which causes a problem that the processing and the circuit are complicated. ..

The present invention has been made in view of the above problems, and provides an image compression coding apparatus capable of reducing the buffer capacity and simplifying the processing and the circuit. With the goal.

[0005]

An image compression coding apparatus according to the present invention comprises a run length conversion means for sequentially converting bit map data output from a scanner into run length data, and the run length conversion means. The run length / compression code conversion means for sequentially compressing and encoding the run length data given via the buffer circuit, and the run length / compression code conversion means. A code conversion table for converting the run length data into a compression coding pattern, and an address generating means for generating an address for accessing the code conversion table based on the given run length data and the output of the code conversion table. It is characterized by being equipped with.

[0006]

According to the present invention, the bitmap data supplied from the scanner is once compressed into run-length data by the run-length conversion means, and the subsequent processing is performed, so that a large capacity buffer is required. There is nothing to do. Moreover, according to the present invention, since the data transfer inside the device is performed in units of run lengths, the data transfer frequency is lower than that in the case of transferring bitmap data. Therefore, by transferring the data in accordance with the processing capacity of the run length / compression code conversion means, the processing efficiency can be improved and high speed processing becomes possible.
Further, according to the present invention, the compression code can be directly obtained by the table lookup method without once converting the run-length data into the bitmap data, so that the run-length bitmap conversion processing becomes unnecessary, Also, the circuit of the conversion unit can be greatly simplified.

When a code conversion table for MH codes is provided as the run length / compression code conversion means, if the run length of the coding pattern output from the table is included as the table output, the next access is made. It becomes easy to generate an address to be used.

[0008]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an image compression coding apparatus of a facsimile machine.

The scanner data in the bitmap format output from the image scanner including the contact type line image sensor is sequentially input to the run length conversion circuit 1. The run length conversion circuit 1 converts the input scanner data into run length data. The output of the run length conversion circuit 1 is a FIFO (First in First Out).
t) Sequentially stored in the memory 2. FI
The output side of the FO memory 2 is connected to the CPU bus 3.

The CPU bus 3 has a CPU 4 and a DR.
The AM buffer 5 is connected. The CPU 4 controls the entire apparatus, and appropriately reads the run length data stored in the FIFO memory 2 and sequentially stores it in the DRAM buffer 6. A run length / compression code conversion circuit 6 is connected to the CPU bus 3. The run length / compression code conversion circuit 6 converts the run length data sequentially read from the DRAM buffer 5 under the control of the CPU 4 into compression coded data such as MH, MR, and MMR, and sequentially outputs to the DRAM buffer 5. Store. The CPU bus 3 has a SCSI interface circuit 7
Are connected, and the compression-encoded data stored in the DRAM buffer 5 is transmitted to a host computer (not shown) under the control of the CPU 4.

As shown in FIG. 2, the run length / compression code conversion circuit 6 includes a code conversion table 21, a reference line data storage unit 22, a data operation circuit 23, an address generation unit 24, and an internal address for interconnecting them. It comprises a bus 25 and an internal data bus 26. The code conversion table 21 is a table for converting run length data into MH code. The reference line data storage unit 22 is composed of an SRAM that stores reference lines when performing MR and MMR encoding. In addition, the data operation unit 23 operates the data output from the code conversion table 21 to generate 16-bit output data, and executes an operation necessary for address generation. Also,
The address generator 24 generates an address to be given to the code conversion table 21.

Next, the operation of this system will be described. First, before describing the operation of the system, an outline of MH, MR, and MMR codes generated from run length data will be described.

(1) MH Code In the MH coding method, data of all scanning lines is one-dimensionally coded. As shown in FIG. 3, the encoded data of one line consists of an EOL (End of line) code added to the beginning and a data code that follows it. RTC consisting of 6 consecutive EOL codes after the last line of one page
A code is added. The EOL code is a 12-bit code represented by "000000000001". Further, as shown in FIG. 3, when the code bit number of one line is shorter than a predetermined bit length T, the fill bit ( Variable length 0) is added. The data code is composed of a variable length code representing a white or black run length. When the run length is 63 or less, the data code is represented by only one terminating code shown in FIG. 4, and when the run length is 64 or more, one or a plurality of data codes shown in FIGS. It is represented by a combination of a make-up code and one terminating code.

(2) MR code In the MR coding method, one scanning line is one-dimensionally encoded, and then two to four continuous scanning lines are two-dimensionally encoded. In the two-dimensional encoding process, the line immediately before the currently encoded line is referred to and the positional relationship between the reference line and the changed pixel (pixel that changes from black to white or from white to black) is encoded. Turn into. That is, as shown in FIG. 7, a0, a0 ', a1, a2, b1, b2 are determined as follows.

A0: a pixel that is a starting point on the encoding line a0 '; a pixel that becomes a0 in the next encoding process a1; a first change pixel a2 opposite in color to a0 on the reference line to the right of a0 The first change pixel b1 on the encoding line to the right of a0; the first change pixel b2 on the reference line to the right of a1; the first change pixel on the encoding line to the right of a2. The following three modes are set by.

Pass Mode As shown in FIG. 7A, when a2 is on the right side of b1, the pass mode is set. In this case, as shown in FIG.
It is encoded into "0001".

Vertical Mode As shown in FIG. 7B, the relative distance between a1 and a2 | a1
When a2 | is 3 or less, the vertical mode is set. In this case, according to the relative distance between a1 and a2, V shown in FIG.
(0), VR (1), VR (2), VR (3), VL
It is encoded into seven codes of (1), VL (2), and VL (3). In VR (n), a2 is on the right side of a1 and VL (n)
Means that a2 is on the left side of a1, and the relative distance is shown in parentheses.

Horizontal mode As shown in FIG. 7 (c), the relative distance between a1 and a2 | a1
When a2 | is 4 or more, the horizontal mode is set. In this case, as shown in FIG. 8, the length of a0a2 is set to "001" by M.
It is encoded into a value obtained by combining the H-encoded one and the MH-encoded a2b2 length. In MR encoding, one-dimensional encoding processing and two-dimensional encoding processing coexist, so
A tag bit is provided immediately after the EOL code to identify whether the following data is one-dimensionally encoded or two-dimensionally encoded.

(3) MMR Code In the MMR coding method, all scanning lines are two-dimensionally coded. When encoding the first line, a virtual all-white line is set as a reference line. In the last line of one page, two EOL codes are consecutively added as RTC codes, and thereafter, an adjustment bit (0) is added so that the number of bits of code data for one page is in units of 8 bits. Add.

Next, the operation of this system will be described.
The bitmap format scanner data output from the image scanner (not shown in FIG. 1) is converted by the run length conversion circuit 1 into, for example, 32-bit run length data RL. As the form of the run length data RL, there are a form including a start point position and a run length, a form including a start point position and an end point position, and the like. For example, in the case of bitmap data as shown in FIG. 9, the former form is shown in FIG.
The form of (a) and the latter form are the forms of FIG. 10 (b), but either form may be adopted.

The outputs of the run length conversion circuit 1 are sequentially F
It is stored in the IFO memory 2. When a predetermined amount of run length data RL is stored in the FIFO memory 2, the FIFO
Since, for example, a half-full status signal or the like is output from the memory 2, the CPU 4 sees such a status signal, and checks the run length data RL from the FIFO memory 2.
Is read out and stored in the DRAM buffer 5.

Next, the run length / compression code conversion circuit 6
Performs sequential reading of the run length data RL stored in the DRAM buffer 5 and performs an encoding process for any one of MH, MR and MMR.

(1) Run Length → MH Coding FIG. 16 is a flowchart showing a conversion process from run length data RL to MH code. First, the EOL code is generated by the EOL code processing (S1). continue,
The run length data RL is read from the DRAM buffer 5 (S2), and as shown in FIG. 11, run length data composed of a flag indicating white / black and a run length is calculated. .. When the run length data is composed of data indicating the positions of the start point and the end point, the start point position is subtracted from the end point position to calculate the run length (S3).

Next, the address generator 24 generates an address for accessing the code conversion table 21 from the obtained run length data (S4). The address is
For example, as shown in FIG. 12, it is composed of a fixed address indicating an area where the RL / MH conversion code of the code conversion table 21 is stored, a white / black discrimination flag, and a lower address Y. That is, in the address generator 24,
As shown in, the comparison circuit 31 compares the run length to be encoded with 2560, and when the run length exceeds 2560, the selection circuit 32 selects 2560, and when the run length is 2560 or less. , The selection circuit 32 selects the run length data RL. The selection result Y, the fixed address, and the black-and-white discrimination flag are combined by the address configuration circuit 33 to generate the address ADR.

The address ADR generated by the address generator 24 is given to the code conversion table 21 via the internal address bus 25. As a result, the code data CDA is read from the code conversion table 21 (S
5). The code data CDA is, as shown in FIG. 13, an identification code I of a makeup code / terminating code.
And the number of coding bits e of the variable length coding pattern, the coding pattern C, and the run length d shown by the coding pattern C.

The code data CDA read from the code conversion table 21 is input to the data operation circuit 23 via the internal data bus 26. Data operation circuit 23
Is configured as shown in FIG. 15, for example. The coding pattern C is set in the shift register 41, and the coding bit number e is set in the counter 42. Since the MH conversion code is a variable length code, in order to unify the number of bits at the time of code output, data is packed in the shift register 43 while shifting the coding pattern set in the shift register 41 bit by bit ( S16) When 16-bit data is stored in the shift register 43 (when the output dc of the counter 44 reaches 16), the MH data code is written in 16-bit units in the DRAM buffer 5 (S6).
7, S8).

On the other hand, in the process of this shift operation, when the number of encoded bits e becomes 0 (S9), the identification code I of the make-up code and the terminating code is determined (S1).
0). If the identification code I indicates a terminating code, the next run length data RL is read (S2), and the same processing is executed for that run length data (S3 to S10). When the identification code I indicates a make-up code, the subtracter 45 subtracts the run length d obtained this time from the given run length data RL or the run length d obtained by the immediately preceding code read. Then, this is output as the run length d to be encoded next (S3). This run length d is also supplied to the comparison circuit 31 of FIG. 14 and is used for generation of the next address. This has the advantage of facilitating the generation of the address to be accessed next. This process is repeated until the identification code I shows the terminating code.

When the processing for one line is completed, the processing of steps S1 to S10 is executed for the next line (S).
11, S12). After processing one page, RT
A C code is generated (S13). By the above operation, the run length data RL can be one-dimensionally encoded.

(2) Run Length → MR Coding FIG. 17 and FIG. 18 show run length data RL to MH.
It is a flowchart which shows the conversion process to a code. First,
It is determined whether the run length data is one-dimensionally encoded or two-dimensionally encoded based on whether or not it is the data of the first line (S21). At the same time, the data of the line to be referenced is written in the reference line data storage unit 22 composed of SRAM.

When performing one-dimensional encoding (S22), the same processing as the above-mentioned MH encoding processing is executed (S23).
~ S33). At this time, in the EOL code processing (S23), "1" is added as a tag bit immediately after the EOL code. When performing two-dimensional coding (S22), "0" is added as a tag bit immediately after the EOL code in the EOL coding process (S41). Then, the reference line data is read from the reference line data storage unit 22 (S4
2) Read the run length data RL of the encoding line to be converted from the DRAM buffer 5 (S43). Then, the run length / two-dimensional code conversion processing is executed (S44).

FIG. 20 is a flowchart showing details of the run length / two-dimensional code conversion processing. First, the pixels a0, a1, and a on the reference line and the encoding line that should be noted
The pass mode, the vertical mode, and the horizontal mode are discriminated from the mutual positional relationship between 2, b1, and b2 (S6).
1). Based on this determination result, the data operation circuit 23 sets the two-dimensional code shown in FIG. 8 in the shift register 41 shown in FIG. 15 (S62). Similar to the MH encoding, the MR conversion code is also a variable length code. Therefore, in order to unify the number of bits at the time of output to 16 bits, the data is shifted (S71) and the MR code is written to the DRAM buffer 5 by 16 bits. (S64, S65). On the other hand, if the number of encoded bits e becomes 0 in the process of this shift operation,
If the current mode is not the horizontal mode, the run length / two-dimensional encoding conversion process is terminated (S66, S6).
7). When the current mode is the horizontal mode, the data arithmetic circuit 23 calculates the run length between a0 and a1 and executes the MH encoding process described above (S68-).
S75). Similar MH encoding processing is executed for the run length between a1 and a2 (S77).

When the processing for one line is completed, the processing of steps S42 to S44 is executed for the next line (S45). When the processing for one page is completed, the RTC code is generated (S47). With the above operation, the run length data RL can be MR-coded.

(3) Run Length → MMR Encoding FIG. 19 is a flow chart showing the conversion process from run length data RL to MMR code. In the case of MMR encoding, only the two-dimensional conversion processing part in the MR encoding processing is performed (S51 to S58), and therefore its details are omitted.

In this way, the compression encoded data stored in the DRAM buffer 5 is sequentially read by the CPU 4 and transferred to the host computer or the like via the SCSI interface 7.

As described above, according to the apparatus of this embodiment, the run-length conversion circuit 1 temporarily compresses the bitmap data supplied from the scanner into run-length data, and then performs the subsequent processing. From FIF
It does not require a large capacity O buffer 2, and
Since the DRAM buffer 5 also only stores run length data and compressed code data, it does not require a large capacity. Therefore, it is possible to sufficiently deal with A0 and A1 size drawings. Moreover, in this device, since data is transferred in run length units, the frequency of data transfer is lower than that in the case of transferring bitmap data. Therefore, the load on the CPU 4 is also significantly reduced.

Further, according to the apparatus of the present embodiment, the run length data is directly converted into the MH, MR and MMR code. Therefore, when the conventional compression / expansion processor which accepts only the bitmap data is used. Compared with, the conversion process is further reduced, the process is simplified and the circuit configuration is simplified.

The present invention is not limited to the above embodiment. In the above embodiment, the converted compressed code data is written in the DRAM buffer 5, but
The compressed code data output from the run length / compressed code conversion circuit 6 may be stored in the FIFO buffer or may be sequentially output to the outside via the interface circuit.

[0038]

As described above, according to the present invention, the bitmap data supplied from the scanner is compressed into run-length data, buffered, and the subsequent processing is performed. No need for large buffers. Moreover, according to the present invention, since buffering is performed in units of run lengths, the data transfer frequency is lower than that in the case of transferring bitmap data. Therefore, data can be transferred according to the processing capability of the run length / compression code conversion means, the processing efficiency is improved, and high-speed processing is possible.

Further, according to the present invention, since the compression code can be directly obtained by the table lookup method without converting the run length data into the bitmap data once, the run length / bitmap conversion process is not required. Therefore, the circuit of the processing and conversion unit can be greatly simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an image compression encoding device of a facsimile device.

FIG. 2 is a block diagram showing a more detailed configuration of a run length / compression code conversion circuit in the device.

FIG. 3 is a diagram showing a data format of an MH encoding method.

FIG. 4 is a diagram showing a terminating code in the MH coding system.

FIG. 5 is a diagram showing a make-up code in the MH coding method.

FIG. 6 is a diagram showing a makeup code in the MH coding method.

FIG. 7 is a diagram for explaining three modes in the MR encoding system.

FIG. 8 is a diagram showing a conversion code in the MR encoding system.

FIG. 9 is a diagram showing an example of image data from a scanner.

FIG. 10 is a diagram showing run-length data converted from the image data.

FIG. 11 is a diagram showing a run length calculated from the same run length data.

FIG. 12 is a diagram showing a format of an address generated by the address generator of FIG.

FIG. 13 is a diagram showing a format of code data output from the code conversion table of FIG.

FIG. 14 is a block diagram showing a main configuration of the address generating unit.

FIG. 15 is a block diagram showing a partial configuration of the data arithmetic circuit of FIG.

FIG. 16 is a flowchart showing a run length / MH code conversion procedure.

FIG. 17 is a flowchart showing the first half of the run length / MR code conversion procedure.

FIG. 18 is a flowchart showing the latter half of the run length / MR code conversion procedure.

FIG. 19 is a flowchart showing a run length / MMR code conversion procedure.

FIG. 20 shows the run lengths in FIGS. 17 and 19.
It is a flow chart which shows the details of two-dimensional code conversion processing.

[Explanation of symbols]

1 ... Run length conversion circuit, 2 ... FIFO memory, 3 ...
CPU bus, 4 ... CPU, 5 ... DRAM buffer, 6 ...
Run length / compression code conversion circuit, 7 ... SCSI interface, 21 ... Code conversion table, 22 ... Reference line data storage unit, 23 ... Data operation circuit, 24 ... Address generation unit, 25 ... Internal address bus, 26 ... Internal data bus ..

Claims (4)

[Claims] 1. A run length conversion means for sequentially converting bit map data output from a scanner into run length data, a buffer circuit for sequentially storing the run length data converted by the run length conversion means, and this buffer circuit. Run length / compression code conversion means for sequentially compressing and encoding run length data given via the run length / compression code conversion means, wherein the run length / compression code conversion means converts the run length data into a compression encoding pattern. And an address generating means for generating an address for accessing the code conversion table based on given run length data and the output of the code conversion table. apparatus. 2. The code conversion table is a table for converting run-length data into a modified Hoffman code, and an output thereof is an identification code for identifying a makeup code and a terminating code, and a coded bit number. , An encoding pattern and a run length corresponding to the encoding pattern, and the address generating means stores the identification code until the identification code output from the code conversion table indicates the terminating code. 2. The image compression encoding apparatus according to claim 1, wherein the run length corresponding to the encoding pattern is sequentially subtracted from the given run length data to generate the address of the code conversion table. 3. The image compression encoding apparatus according to claim 1, further comprising a memory that sequentially stores the run length data stored in the buffer circuit. 4. The image compression encoding apparatus according to claim 3, wherein the memory sequentially stores the compression encoded data converted by the run length / compression encoding conversion means.