JPH0292111A - Analog switching circuit and display using same - Google Patents

Abstract

PURPOSE:To drive the driving element of an output step for a high voltage signal with a low voltage by providing a resistance between a source and a gate and making a driving signal impressed to the gate into a high voltage signal to level-shift a low voltage input signal. CONSTITUTION:An N channel element Q2 of an electric field effect transistor is used as a driving element, a load is connected to a source side, a high voltage pulse signal is impressed from a drain side, and then, in order to conduct and interrupt the high voltage pulse signal to a source side in accordance with the low voltage signal, a low voltage signal superimposed to a high voltage is generated, a current source is controlled by using this and the current flows at a resistance 6 connected between the gate and source of an electric field effect transistor Q2. Thus, by generating the potential difference between the gate and source, the electric field effect transistor Q2 is controlled. Thus, an analog switching circuit, in which the driving element of an output step can be drived for the high voltage signal by a low voltage, can be obtained.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an analog switch circuit for conducting or cutting off continuous or intermittent high-voltage signals, and a display device using the same, and particularly to The present invention relates to an analog switch circuit suitable for controlling voltage pulse signals and a display device using the same.

[Conventional technology]

Conventionally, circuits that conduct or interrupt continuous signals using semiconductor devices generally conduct at high speed, as described in Ryuyo's How to Use rFETs (CQ Publishing, p. 198).

Junction type field effect transistors and MO8 type field effect transistors are used as semiconductor elements for blocking.

In this case, in the P-channel type, a signal source is injected from the source side, a load is connected to the train side, and a gate voltage is applied such that the gate voltage is higher than the source only during the conduction period. That is, the resistance between the drain and the source decreases during the period when the signal is applied to the gate, and the transistor becomes conductive, making use of the effect that the signal applied to the source conducts to the drain side.

[Problem to be solved by the invention]

The above-mentioned conventional technology is generally configured to conduct or cut off voltages up to about 20 to 30V, and no consideration is given to conducting or cutting off higher voltage signals. When used for displaying a plasma display panel, a high voltage of 200 to 300 μm is applied, resulting in dielectric breakdown between the gate and source.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above problems in the conventional technology,
An object of the present invention is to provide an analog switch circuit that can drive an output stage drive element with a low voltage in response to a high voltage signal, and a display device using the same.

[Means to solve the problem]

The above object of the present invention is to provide a field effect transistor as a voltage control element, a transistor as a current control element, etc.
Achieved by an analog switch circuit characterized in that a terminal control element is used as a drive element, and the gate or base voltage is controlled by a low voltage signal superimposed on a high voltage, and a display device using the same. be done.

[Effect]

For example, if an N-channel field effect transistor element is used as a driving element, a load is connected to the source side, and a high voltage pulse signal is applied from the drain side, the high voltage pulse signal is applied to the source according to the low voltage signal. conduction to the side,
To cut it off, create a low voltage signal superimposed on the high voltage, use this to control the current source, and cause current to flow through the resistor connected between the gate and source of the field effect transistor.
Thereby, the field effect transistor can be controlled by creating a potential difference between the gate and the source.

This operation is similar for transistors as well. Further, even when a P-channel element is used, the same operation can be performed.

The analog switch circuit according to the present invention can be suitably used in a display control circuit of a display device that applies a high voltage signal generated in accordance with an image signal to a display element. Further, in this case, even greater effects can be obtained if used in combination with a known power recovery circuit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an analog switch circuit showing one embodiment of the present invention, and FIG. 2 is a timing chart showing its operation timing.

In FIG. 1, Ql is a PNPN transistor (hereinafter simply referred to as a "transistor") as the above-mentioned bipolar transistor for the current circuit, and Q2 is an N-channel M as a drive element that conducts or cuts off a high voltage signal.
It shows an O8FET (hereinafter simply referred to as rFETJ), and CQ shows a capacitive load.

Note that 1 is an input terminal for a low voltage input signal vA, 2 is a photocoupler, 4 is a speed-up circuit for removing the accumulation effect of transistor Q1, 7 is an input terminal to which a high voltage pulse VD is applied, and 8 is an input terminal originally for FET Q2. Parasitic body-drain diode 9 indicates ground. ■, 4
．． vF and VL are power supplies, and 3, 5, and 6.26 are resistances.

In the basic circuit shown in this embodiment, FET Q2 serves as an analog switch, and FET Q2 is switched according to the low voltage input signal vA.
2 gate voltage■. ■ Due to high voltage pulse. It has the function of conducting and interrupting conduction, and when conductive, applies power from the drain D side to the source S side to supply power to the capacitive load CQ.

The operation will be explained below according to the time chart shown in FIG.

First, the T1 section of the low voltage input signal vA that changes in a pulse-like manner will be described. T of low voltage input signal vA at input terminal 1
Apply one section. This input signal is superimposed on a high voltage via a photocoupler 2.

The photocoupler 2 operates by applying a power supply VL to the terminal 22 via the limiting resistor 26 at the voltage applied to the input terminal 1, and causing the voltage to flow from the terminal 21 to the ground 9 via the light emitting element.

The light emitted thereby enters the light receiving element. In order to drive this light receiving element with a high voltage, the positive side of a high voltage power source VH is connected to the terminal 23, and the negative side of the power source VF is connected to the terminal 24. As a result, the light receiving element operates in a state floating from the ground 9.

When the light receiving element is incident with light, it operates a digital gate at an output stage. That is, according to the low voltage input signal ■9, the output terminal 25 of the photocoupler 2 is connected to the high voltage power supply V.
) A current flows from the power source vF through the limiting resistor 3 on
As a result, the voltage VHF shown in FIG. 2 appears.

This output voltage VHF is applied to the base B of transistor Q1. Here, in order to increase the switching speed of the transistor Q1, a speed-up circuit 4 is inserted on the base B side. This speed-up circuit 4 has a configuration in which a resistor and a capacitor are connected in parallel.

Since the transistor Q1 operates with a grounded emitter, the output voltage V)I of the photocoupler 2 is applied to the base B.
The "L" level (V+1-VF) of F is applied and turns on. The voltage of the emitter E increases by about 0.7 V from the base voltage in the case of a silicon element.

■ This emitter voltage and high voltage power supply. The difference is applied to the resistor 5, and a current 10 flows.

Here, the operation in the high voltage pulse vDOTL section shown in FIG. 2 will be explained.

Current from collector C of transistor Q1 ■. flows out, and while charging the gate input capacitance C1 of FET Q2, it passes through resistor 6 from the source S of FET Q2 to the aforementioned body drain diode 8 to the “L” level (VDL) of the high voltage pulse. Flow into. Here, when the body drain diode 8 is an N channel, the source S
The side becomes the anode, and the drain D side becomes the cathode. FE
The condition for turning on TQ2 is V in the following equation (1). The value of is equal to or higher than the threshold value (VT)l) of FETQ2.

FIG. 3 shows an equivalent circuit for charging the gate input capacitance C3 of FET Q2. The gate voltage Va at this time is determined by the following formula.

V c = I o R (1-e - “” (1)
Here, τ=C, R, R are the values of the resistor 6 in FIG. indicates the current.

The above τ indicates the time constant of the rising edge of FET C2. Assuming that the resistor 6 is, for example, 30Ω and C1 is, for example, 100PF, τ is 3 μsec.

As can be seen from equation (1), the current 10 and the time constant τ can be determined independently. In order to operate FET C2 at high speed, it is necessary to make the rising time constant τ as small as possible.

Specifically, since the gate input capacitance C is determined by the structure of the element, the resistor 6 must be made small. but,
When the resistor 6 is made smaller, the voltage between the gate G and source S of the FET C2 becomes less than the threshold value (vT, 4), and it is no longer sufficiently conductive. Electrician there. ] Increase the voltage between the gate G and source S to exceed the above threshold value. However, if this voltage is made too high, the voltage between the gate G and the source S will exceed the withstand voltage (Vaemax) and cause damage, so to prevent this, the Zener diode ZD
is connected in parallel with the resistor 6 between the gate G and the source S.

As a result, the gate G can be driven at high speed, the resistance 6 between the drain D and the source S is reduced, and the FET C2, which is an analog switch element, becomes conductive.

Next, the operation in the TH section of the high voltage pulse vn shown in FIG. 2 will be explained.

FET C2 is conducting. The “H” level (vDH) of the high voltage pulsed train voltage VD applied to the terminal 7 of the drain D is applied from the drain D to the source S,
The capacitive load Cρ is charged.

At the same time, the gate voltage Vc of FET C2 is changed to the high voltage Va
Raise it to H. The voltage at the source S rises to the "H" level (VS) I) of the v6 waveform in FIG. This also charges the capacitive load C1+.

FET C2 maintains a conductive state until the charge accumulated in the capacitive load CQ described above is discharged. When the charge accumulated in the capacitive load CO is discharged, the transistor Q1
Now, the voltages at collector C and terminal 10 become the same, and the circuit is turned off. High voltage pulse V applied to the drain D of FET C2. TL, T.

In order to repeat this, the transistor Q1 is also Turns on and off.

Next, the T2 section of the low voltage input signal 1 in FIG. 2 will be explained.

By applying the If HII level (■L) of the low voltage input signal vA to the input terminal 1 in FIG. 1, a high voltage VH is applied to the output terminal 25 of the photocoupler 2. Transistor Q1 and FET C2 are turned off.

The charges accumulated in the capacitive load Co and the gate input capacitance C1 pass through the body-drain diode 8, and the high voltage pulsed drain voltage vn on the train D side is LL L.
It turns T towards I+ level (■DL) and discharges in the section. As a result, the output voltage v6 of the source S is V6 in FIG.
It becomes an s waveform. When the charge accumulated in the capacitive load on the source S side is gradually discharged, the peak value of the pulse becomes P in Figure 2.
It becomes low like L, P2, and becomes v6 level.

According to the above embodiment, when a high voltage of 200 to 300 V is applied, it is possible to drive an analog switch, which conventionally required a more complicated configuration, by driving the drive element of the output stage with a low voltage. , can have a simple configuration.

Next, as the above-mentioned bipolar transistor for the current circuit, we will use an NPN transistor (hereinafter simply referred to as a "transistor").
) Qll, and a P-channel FET (hereinafter simply referred to as rFET) C21 as an analog switch element.
The cases in which these are used will be explained with reference to FIGS. 4 and 5.

Specifically, a low voltage input signal V is input to the input terminal 400 in FIG.
Conduction section T11 and cutoff section T2 of FETC 21 when a high voltage pulse-like source voltage is applied to the source S input terminal 403 of FETC 21 for 7 days, respectively.
1 will be explained.

In the input signal VB of FIG. 5, in the Tl1 interval.

A ground voltage Vφ is applied to the transistor Qll,
Turn on. At this time, the emitter E of the transistor Qll
A bias voltage v-5 for operation is applied to the side. V from ■φ to the emitter E side of the transistor Qll.
A lower level voltage is applied only to BE. A voltage (Vap V-s) is applied to both ends of the resistor RE attached to the emitter side, and a current ■o flows regardless of the high voltage pulse applied to the source S input terminal 403. Thereby, the transistor Qll and the resistor RE constitute a current source.

The current 10 flows from the source voltage v8 in the form of a high voltage pulse applied to the source S side, passes through the resistor 401, passes from the collector C of the transistor Qll to the emitter E, and flows through the power source v-
Flows into 5. A voltage is generated across resistor 401 by current 10, and when this voltage is within the threshold voltage of FET Q21, FET Q21 is turned on. The conditions for turning on follow the above equation (1). When FET Q21 is turned on and a high voltage pulse-like source voltage ■8 IIH'' level (V S H) is applied to the source input terminal 403, since the emitter E side of the transistor Qll is close to the ground level, the collector C, A high voltage is applied between the emitter E. Therefore, a transistor with high breakdown voltage is used as the transistor Qll.

When the FET Q21 is turned on, the resistance value between source S and drain 0 decreases, and the high voltage pulsed source voltage Vs applied to the source input terminal 403 is transferred to the output terminal 4.
05 to indicate that the so-called FETQ21 has become conductive. As a result, the drain voltage (■) becomes the output voltage that conducts from the drain D of the FET Q21 to the capacitive load CQ connected to the output terminal 405. II H11
Charges are accumulated depending on the level (VDH).

Next, the cutoff section T21 of the input signal VB will be explained.

When a voltage of v-5 is applied to the input terminal VB, the transistor Qll is turned off. Therefore, FET Q21 is also turned off. The charge charged to the capacitive load CQ in the T11 section is
During the T21 interval, the high voltage pulse-like source voltage ve is brought to “L” level (
V e L ). As a result, the charge accumulated in the capacitive load becomes 110 ++, and the output terminal 40
The voltage appearing at 5 will also be 110''.

In this way, in the Tl1 section of the low voltage input signal VB, the FE
TQ21 operates by repeatedly conducting and cutting off. Fourth
In the figure, Zener diode 402 is FETQ2
The purpose of this is to protect the breakdown voltage between the gate G and source S of 1.

In the above embodiments, a capacitive load has been described as the load of the analog switch, but the same applies to a resistive or inductive load.

Next, a case where a voltage hold circuit is added to the analog switch circuit shown in FIG. 1 will be described based on FIGS. 6 and 7.

A case will be described in which an N-channel FET (hereinafter simply referred to as rFETJ) Q3 is used as a voltage hold circuit element.

The transistor Q1, which is a current source element, performs the same function as the transistor Q1 shown in FIG.
Here, a voltage VH shown in FIG. 7 is applied to the input terminal 80.
F is applied. In section T1, similarly to section T1 shown in FIG. 2, FET Q2 is turned on, and a high voltage pulsed drain voltage V is applied to the drain D side. is applied to the capacitive load C, as the source voltage (18) on the source S side.

Next, in section T2, FET Q2 is turned off similarly to section T2 shown in FIG. The charge accumulated in the gate input capacitance and capacitive load during the T1 period passes through the body drain diode 8, resulting in a high voltage pulse train voltage ■. is discharged toward the "L" level (Vat, ). At this time, in order to fix the potential on the source S side of the FET Q2, the hold input signal 2 shown in FIG. 7 is applied to the gate G input terminal 81 of the FET Q3 as a voltage hold element. ■Turn on FET Q3 by the "H" level of 8.

As a result, the potential ■6 of the source S of FET Q2 becomes F
The drain D potential of ET Q3 becomes ■. Therefore, the seventh
As shown in the figure, the potential ■8 of the source S of FET Q2 is
'L' level (vE) is fixed and held.Here, an N-channel FET was used as FET Q2 for explanation, but a P-channel FET is also explained in the same way.
It is possible to operate it by adding a voltage hold circuit. Also, it is not a FET, but a transistor (NPN, PNP
) can also function in the same way.

FIG. 8 is a circuit configuration diagram showing another embodiment of the present invention. Earlier, in the circuit shown in FIG. 1, the FET Q2 was switched by the signal from the high voltage source side, but in the circuit of this embodiment, the FET Q2 was switched by the signal from the ground voltage side.
This is what switches Q2. Resistor 6 and Zener diode ZD function in the same manner as described in FIG.

P-channel FET Q3 is an element for switching current 10, similar to transistor Q1 shown in FIG.
The drive of this element is level-shifted so that it can be controlled by a signal voltage between the ground voltage and 76 by a P-channel FET Q4 and an N-channel FET Q5, which constitute a current mirror circuit with the FET Q3 described above.

■H is the above FET Q4. This is a high-voltage power supply for sending current to the current mirror circuit composed of Q3, and plays the same role as shown in Figure 1. Also, the drain voltage V
. The same waveform as shown in FIG. 2 is applied to . 11 is N
A signal circuit for driving channel FET Q5, which includes, for example, a shift register circuit and a latch circuit, and has the function of converting serially input image signals from serial to parallel and outputting them in parallel.The power supply of this signal circuit The voltage is a low voltage power supply VL.

In this circuit, as described later, the element isolation semiconductor layer is set to a voltage lower than the ground voltage, and even if the output voltage V
. This prevents the PN junction for element isolation from being forward biased even if UT drops below the ground voltage.

Note that the diode D1 in FIG. 8 functions as a hold circuit provided to suppress the amount of drop in the output voltage VOUT below the ground voltage.

FIG. 9 shows a configuration example of a step-down circuit that can be used in the circuit shown in FIG. 8. Clock signal V applied to capacitor C2. LK and this V. LK to N channel F
An inverter circuit consisting of an ET Q6 and a P-channel FET Q7 uses a signal whose sign is inverted and applied to the cathode side of the diode D2, and uses the charge pump principle to control the voltage of the P-type semiconductor layer for element isolation. It is possible to lower the voltage by about 7μ below the ground voltage.

FIG. 10 shows a sectional view of a state in which the FET Q2 and diode D shown in FIG. 8 are integrated into an integrated circuit. As mentioned above, the diode D has an output voltage ■. The UT functions as a hold circuit to suppress the amount of voltage drop below the ground voltage. In the circuit shown in FIG. 10, a P-type semiconductor layer 1 for element isolation is used.
003.1006 is set to a voltage lower than the ground voltage, and even if the output voltage VOUT falls below the ground voltage, the PN junctions 1003 and 1006 for element isolation are
04 is prevented from being forward biased.

More specifically, this figure is a cross-sectional view of the semiconductor device showing the connection point of VSUB shown in FIGS. 8 and 9, and a wiring diagram of the power supply. is separated by a P-type semiconductor substrate 1003 and a P-type diffusion layer 1006. On the left side of this diagram, N
A vertical MoS transistor is shown in which the source is the type diffusion layer 1011, the body is the P type diffusion layer 1010, and the drain is the N type diffusion layer 1007 and the N type buried layer 1004. On the right side, the P type diffusion layer 1010 is used as the anode. and N-type diffusion layer 1
8 shows a cross-sectional view of the diode D1 of FIG. 8 with 005.1004.1007 as the cathode.

The cross-sectional view of this semiconductor device itself has been known for a long time, but the feature of this configuration is that the P-type semiconductor layers 1006 and 1003 for element isolation are not at the same voltage as the ground voltage, but at vl, VEII is set lower by 2
This is a unique point for JB. For example, the output voltage V in FIG.
. When UT drops below ground voltage, the cathode region (1005, 1004) of the diode on the right side in FIG.
, 1007) has fallen below the ground voltage.

When the P-type semiconductor substrate is set to the ground voltage as in the conventional case, the PN junction between the P-type layer 1003 and the cathode region is forward biased, and current flows to the P-type semiconductor layer 1003 for element isolation. This configuration can prevent the problem of causing the device isolation PN junctions of adjacent devices to also be forward biased, causing malfunctions.

In addition, if the junction capacitance with respect to the substrate is shown in the example of Fig. 10,
MOS transistor drain region 1004 and substrate 10
Since the capacitance with 03 is lowered, there is also the effect that the element separated by the PN junction operates at high speed.

The voltage of the P-type semiconductor layer for element isolation is lower than the ground voltage by v
In order to set the voltage Vl'1tlB of the P-type semiconductor layer for element isolation as low as 142, an external power supply may be used, but if a step-down circuit as shown in FIG. The purpose can be achieved without using an external negative voltage source.

FIG. 11 is a cross-sectional view and a power supply connection diagram showing another example of the substrate voltage application method for the above-described semiconductor device.

The semiconductor device shown in this figure is similar to the one shown in the left side of FIG. 10, which has a vertical MOS transistor (on the left side in the figure) with an N-type substrate as a drain, and elements separated by a P-type epitaxial layer 1002 and a P-type diffusion layer 1006. This is a semiconductor device in which a vertical MOS transistor with a similar configuration coexists, and a method of applying a substrate voltage to this device is shown.

In this figure, as mentioned above, the P-type epitaxial layer 1
Since the P-type diffusion layer 1002 and the P-type semiconductor layer 1006 are P-type semiconductor layers for element isolation, this region is connected to a voltage lower than the ground voltage. In this configuration example, a parasitic bipolar transistor having an N-type layer 1000 as an emitter, a P-type layer 1002 as a base, and an N-type layer 1004 as a collector has a structure that is inherently easy to operate.

As mentioned above, if the P-type semiconductor layer used for element isolation in a PN junction isolated semiconductor integrated circuit device is lowered below the ground voltage, even if the output terminal drops below the ground voltage due to the load condition, the ground voltage cannot be lowered any further. This setting has the effect of forward biasing the PN junction for element isolation, thereby preventing parasitic elements from turning on and malfunctioning.

Next, an example in which the present analog switch circuit is used in a display device will be explained using FIGS. 12 and 13. Note that in this embodiment, a discharge cell is used as the capacitive load.

When driving a discharge cell with an image signal, the discharge cell is
As shown in FIG. 12, the electrodes are arranged vertically and horizontally, and each electrode is driven. The discharge cell of this embodiment has a three-electrode structure, as shown in FIG. 12, and consists of an anode electrode A, a cathode electrode, and a sub-anode electrode SA. In this example, the discharge cell is
As shown in FIG. 2, a case where the cells are arranged in three rows and columns will be explained.

The basic configuration of the display device consists of an anode drive system that supplies the anode electrode A, a scanning signal generator 614 that generates a signal to be applied to the cathode electrode, and a display signal generator 613 that applies the signal to the sub-anode electrode SA. There is. here,
The anode drive system includes a recovery circuit 600 that generates a high voltage pulse 7P and at the same time recovers power, and an anode electrode A.
It consists of an analog switch circuit group 60 having a pulse distribution function for supplying pulse distribution signals to each line, and a sampling pulse signal generation circuit 615 for supplying a pulse distribution signal.

Generally, when driving a capacitive load, a transient current flows at the rise of a high voltage pulse to charge the load capacitance and the stray capacitance of the circuit. On the other hand, when the high voltage pulse falls, the charge accumulated in the capacitance is discharged, so
Transient current flows.

Since the discharge cell as a load is also a capacitive load, transient current flows and power consumption becomes significantly large.

In order to reduce the power consumption of display devices such as those described above, a power recovery circuit is generally used. Here, the power recovery circuit is composed of a coil, a capacitor, and a switching element, as described in, for example, Japanese Patent Laid-Open No. 132997/1983, and is configured to prevent the electric charge charged in the load from being consumed by a resistor. This is a circuit that accumulates in the above capacitor.

In order to efficiently perform the above power recovery, one power recovery circuit is provided to recover the high voltage signal from each anode electrode A.
Alternatively, distribution to each anode electrode A may be performed. For this purpose, a pulse distributor that can bidirectionally collect and distribute high voltage signals is required. The aforementioned analog switch according to the present invention can be used for this purpose as shown below.

In the configuration example shown in FIG. 12, a power recovery circuit is used to reduce the power of the signal applied to the anode electrode A.
An analog switch circuit group 60 is provided at the subsequent stage. Hereinafter, a case in which a discharge cell is lit using an image signal will be described in detail.

When lighting an image signal in a discharge cell, a method is generally used in which luminance is converted into a time length and displayed, such as an intra-field time division method. This method divides one field into seven types of periods and calculates the length ratio of each period.
2°=21=22:23:24:25:26 (bit O
~6). By combining these seven types of periods, 27=128 levels of gradation can be displayed.

FIG. 13 shows a time chart based on this method. In order to light up the discharge cell, a voltage must be applied to the anode electrode A, the cathode electrode, and the sub-anode electrode SA. Furthermore, in order to express brightness information, a Townsend pulse (■) is used to sustain the discharge in the anode electrode A. need to be applied. The number of Townsend pulses vT is allocated according to the intra-field time division scheme described above.

FIG. 13 shows a waveform vAT□~V representing the above-mentioned allocated section.
AT3 is shown. Here, from OH to 2 in 1 field.
It shows up to the 4th H. In addition, here, IH is 63.
Let it be 5×10-' seconds.

The section TD in FIG. 13 will be explained below.

At this time, the discharge cell shown in FIG.
It is in a state where the information is turned on. That is, anode electrode A
When the first line A1 of is in the selected state at vAl and the Vex pulse voltage 70 is applied to the first column SAI of the sub-anode electrodes SA, the discharge cells 604 are lit. However, it is assumed that a pulse voltage VK1 given to the first line 1 is applied to the cathode electrode K.

Similarly, when the operation proceeds according to the second line and the second column, the third line and the third column, and the time chart of FIG. 13, the pulse voltages 71, 72.7
3 and 74, voltage pulse train V T on anode electrode A
x + V T2 + V T2, one voltage pulse on the cathode electrode, xltVKzt and V K 31, discharge cells 604, 605, 606, 608
and 611 are lit. This state is shown with diagonal lines in FIG.

The display signal generating section 613 generates voltage pulses V e x , g V B □, and v83 according to the brightness signal of the image.

Further, the scanning signal generating section 614 generates a voltage pulse V Kl-I V K21 V applied to each line of the cathode electrode.
Generate K3. Furthermore, the voltage pulse vA in FIG.
□+VA2+VA3 is generated by the sampling pulse generation circuit 615. The recovery circuit 600 recovers power and generates the high voltage pulse TP shown in FIG.

The analog switch circuit group 60 extracts the continuous pulse series vTP from the recovery circuit 600 and converts it into pulses vA1 to VA.
3 to obtain Townsend pulse vT. The analog switch circuit 601 in the analog switch circuit group 60 receives the high voltage pulse VTP from the recovery circuit 600 at the terminal 62, and receives the sampling pulse signal VA1 at the terminal 61 on the control line C1 of the sampling pulse generation circuit 615. , conducts or cuts off the high voltage pulse VTP and outputs it as a Townsend pulse vT onto the output line A1.

Analog switch circuits 602 and 603 in the analog switch circuit group 60 operate similarly.

Therefore, the waveform shown in FIG. 13 is applied to the anode electrode A and the cathode electrode K, the selected discharge cell is lit according to the signal of the sub-anode electrode SA, and an image can be reproduced on the display device.

Since power recovery circuits require inductors, they are generally ICs.
Therefore, providing a recovery circuit for each anode electrode is not preferable when implementing an anode drive circuit into an IC. On the other hand, when the analog switch circuit according to the present invention is provided, only one power recovery circuit is required, so there is an effect that the anode drive circuit can be easily integrated into an IC.

Further, in the above embodiments, a discharge cell is used as the display element, but other display elements that apply pulse voltage intermittently in a time-series manner, such as EL (electroluminescence), may also be used.

It goes without saying that it can also be used to drive panels such as liquid crystals.

〔Effect of the invention〕

As described above, according to the present invention, a three-terminal control element such as a field effect transistor as a voltage control element and a transistor as a current control element is used as a drive element, and the voltage of the gate or base is increased above a high voltage. Since it is configured to be controlled by a superimposed low voltage signal, it has the remarkable effect of realizing an analog switch circuit that can drive the drive element of the output stage with a low voltage in response to a high voltage signal. be.

Further, when the analog switch circuit according to the present invention is used as a display element driving device, there is an effect that the display element driving device can be easily made into a semiconductor and can be made into an IC. In this case, since it can be used in combination with the power recovery circuit of the image display device, it is also effective in reducing the display power of the image display device.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram showing an embodiment of the present invention, Fig. 2 is a timing chart showing its operation timing, Fig. 3 is an equivalent circuit diagram of the circuit shown in Fig. 1 during charging, and Fig. 4 is A circuit configuration diagram showing another embodiment of the present invention, FIG. 5 is a timing chart showing its operation, FIG. 6 is a circuit configuration diagram of an analog switch including a voltage hold circuit, and FIG. 7 is a timing chart showing its operation. , FIG. 8 is a circuit configuration diagram showing another embodiment of the present invention, FIG. 9 is a diagram showing an example of the configuration of a step-down circuit that can be used in the circuit shown in FIG. 8, and FIG. 11 is a cross-sectional view showing a state in which the circuit shown in FIG. 11 is integrated, and FIG.
FIG. 12 is a configuration diagram of a drive circuit for a display device as an application example of the present invention, and FIG. 13 is a timing chart showing its operation. 1: Input terminal, 2: Photocoupler, 8: Body drain diode, 9 Nigerland, Ql e PNP transistor, Q2: N-channel FET, Io: Current, CD
: capacitive load, ZD: Zener diode, vA: low voltage input signal, vD drain voltage, ■o: gate voltage. Patent applicant: Hitachi, Ltd.

Claims (1)

[Claims] 1. In an analog switch circuit configured to input a high voltage pulse to the drain side of an N-channel FET and apply a switching drive signal to the gate, the source,
An analog switch circuit characterized in that at least a resistor is provided between the gates, and a drive signal applied to the gate is a high voltage signal level-shifted from a low voltage input signal. 2. In an analog switch circuit configured to input a high voltage pulse to the source side of a P-channel FET and apply a switching drive signal to the gate, at least a resistor is provided between the source and the gate, and a high voltage pulse is applied to the gate. An analog switch circuit characterized in that a drive signal is a high voltage signal level-shifted from a low voltage input signal. 3. The drive signal applied to the gate is one in which a low voltage input signal is level-shifted to a high voltage signal via an optical coupling element, and the high voltage signal is converted into a current signal via a current control element. The analog switch circuit according to claim 1 or claim 2, characterized in that: 4. In an analog switch circuit configured such that a high voltage pulse is input to the collector side of an NPN transistor and a switching drive signal is applied to the base, at least a resistor is provided between the emitter and the base, and a drive signal is applied to the base. An analog switch circuit characterized in that the signal is a high voltage signal obtained by level shifting a low voltage input signal. 5. In an analog switch circuit configured to input a high voltage pulse to the emitter side of a PNP transistor and apply a switching drive signal to the base, at least a resistor is provided between the emitter and the base, and the drive signal applied to the base is An analog switch circuit characterized in that the signal is a high voltage signal obtained by level shifting a low voltage input signal. 6. The drive signal applied to the base is one in which a low voltage input signal is level-shifted to a high voltage signal via an optical coupling element, and the high voltage signal is converted into a current signal via a current control element. The analog switch circuit according to claim 4 or claim 5. 7. When the gate input capacitance of the FET is Ci, the resistance between the gate and source is R, and the high voltage pulse period is T, then R
4. The analog switch circuit according to claim 1, wherein <T/C_i. 8. When the base input capacitance of the transistor is C_i, the resistance between the base and the emitter is R, and the high voltage pulse period is T, R<T/C_i. The analog switch circuit described in any of the above. 9. When the gate threshold voltage of the FET is V_T_H, the withstand voltage between the gate and source is V_G_Smax, the resistance between the gate and source is R, the gate input capacitance is C_i, the high voltage pulse period is T, and the current is I_0. , above V_T_
Between H, R, C_i, T, I_0, and V_G_Smax, V_T_H/(1_-e-T/CiR)<I_0R<
4. The analog switch circuit according to claim 1, wherein V_G_Smax/(1_-e-T/CiR) holds true. 10. The base threshold voltage of the transistor is V_T_H
, the withstand voltage between the base and emitter is V_G_Smax, the resistance between the base and emitter is R, and the base input capacitance is C_i
, when the high voltage pulse period is T and the current is 1_0, the above V_T_H, R, C_i, T, I_0 and V_G_
During Smax, V_T_H/(1_-e-T/CiR)<I_0R<V
7. The analog switch circuit according to claim 4, wherein _G_Smax/(1_-e-T/CiR) holds true. 11. The gate threshold voltage of the FET is V_T_H, the withstand voltage between the gate and the source is V_G_Smax, the resistance between the gate and the source is R, the gate input capacitance is Ci, the application time difference between the gate applied voltage and the high voltage pulse is t_0, and the current I_
0, the above V_T_H, R, C_i, t_0,
V_T_H/(1_-e-T_0/CiR)<I_0R
4. The analog switch circuit according to claim 1, wherein <V_G_Smax/(1_-e-T_0/CiR) holds true. 12. The base threshold voltage of the transistor is V_T_H
, the withstand voltage between the base and emitter is V_G_Smax, the resistance between the base and emitter is R, and the base input capacitance is C_i
, the application time difference between the base applied voltage and the high voltage pulse is t_0
, when the current is I_0, the above V_T_H, R, C_
Between i, t_0, I_0, V_G_Smax, V_T
_H/(1_-e-T_0/CiR)<I_0R<V_
7. The analog switch circuit according to claim 4, wherein G_Smax/(1_-e-T_0/CiR) holds true. 13. The analog switch circuit according to claim 1, further comprising a capacitive load connected to the source side of the FET, and a voltage hold circuit connected in parallel with the capacitive load. 14. Connect a capacitive load to the drain side of the FET,
3. The analog switch circuit according to claim 2, further comprising a voltage hold circuit connected in parallel with said capacitive load. 15. The analog switch circuit according to claim 13 or 14, wherein an input signal is applied to the voltage hold circuit to hold the FET for a period in which the FET is turned on. 16. The analog switch circuit according to claim 4, wherein a capacitive load is connected to the emitter side of the transistor, and a voltage hold circuit is connected in parallel with the capacitive load. 17. The analog switch circuit according to claim 5, wherein a capacitive load is connected to the collector side of the transistor, and a voltage hold circuit is connected in parallel with the capacitive load. 18. The analog switch circuit according to any one of claims 1 to 17, wherein the semiconductor layer used for element isolation is configured to have a potential lower than a ground potential when integrated into an integrated circuit. 19. The analog switch circuit according to claim 18, wherein a charge pump circuit is used as means for lowering the potential of the semiconductor layer used for element isolation below ground potential. 20. A display device of a type in which discharge cells are driven by image signals, characterized in that the analog switch circuit according to any one of claims 1 to 17 is used as display signal generating means. 21. The display device according to claim 18, further comprising a power recovery circuit in addition to the analog switch circuit.