JPH0291355U - - Google Patents

Info

Publication number
JPH0291355U
JPH0291355U JP1988170701U JP17070188U JPH0291355U JP H0291355 U JPH0291355 U JP H0291355U JP 1988170701 U JP1988170701 U JP 1988170701U JP 17070188 U JP17070188 U JP 17070188U JP H0291355 U JPH0291355 U JP H0291355U
Authority
JP
Japan
Prior art keywords
semiconductor element
die pad
lead frame
pad part
element chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988170701U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988170701U priority Critical patent/JPH0291355U/ja
Publication of JPH0291355U publication Critical patent/JPH0291355U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａは本考案の第１の実施例によるリード
フレームダイパツド部の外観斜視図、第１図ｂは
そのダイボンデイング後の模式断面図、第２図は
本考案の別の実施例によるダイパツド部外観斜視
図、第３図は従来技術における半導体素子チツプ
をリードフレームダイパツド部に導電性接着剤よ
り取り付けた構造の外観斜視図、第４図は接着剤
硬化前のリードフレームダイパツド部断面図、第
５図は接着剤硬化後のリードフレームダイパツド
部断面図である。 １：リードフレームダイパツド部、２：半導体
素子チツプ、３：導電性接着剤、４：リードフレ
ームステツチ部、５：デインプル状の穴、６：網
目状の穴。 FIG. 1a is an external perspective view of a lead frame die pad according to a first embodiment of the present invention, FIG. 1b is a schematic sectional view after die bonding, and FIG. 2 is a diagram showing another embodiment of the present invention. Fig. 3 is an external perspective view of a conventional structure in which a semiconductor chip is attached to a lead frame die pad using a conductive adhesive, and Fig. 4 is a perspective view of the lead frame die pad before the adhesive hardens. 5 is a cross-sectional view of the lead frame die pad after the adhesive has hardened. 1: Lead frame die pad part, 2: Semiconductor element chip, 3: Conductive adhesive, 4: Lead frame stitch part, 5: Dimple-shaped hole, 6: Mesh-shaped hole.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 導電性接着剤により半導体素子チツプをダイボ
ンデイングする基板リードフレームにおいて、そ
のダイパツド部の半導体素子チツプ取付面に、デ
インプル状または網目状にダイパツド部を貫通し
ない穴を備えることを特徴とする半導体素子基板
リードフレーム。 A semiconductor element substrate in which a semiconductor element chip is die-bonded using a conductive adhesive, wherein the semiconductor element chip mounting surface of the die pad part is provided with a dimple-shaped or mesh-shaped hole that does not penetrate through the die pad part. Lead frame.
JP1988170701U 1988-12-29 1988-12-29 Pending JPH0291355U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988170701U JPH0291355U (en) 1988-12-29 1988-12-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988170701U JPH0291355U (en) 1988-12-29 1988-12-29

Publications (1)

Publication Number Publication Date
JPH0291355U true JPH0291355U (en) 1990-07-19

Family

ID=31461875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988170701U Pending JPH0291355U (en) 1988-12-29 1988-12-29

Country Status (1)

Country Link
JP (1) JPH0291355U (en)

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